Fairchild DM7473 service manual

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DM7473
Dual Master-Slave J-K Flip-Flops

with Clear and Complementary Outputs

DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

September 1986
Revised February 2000

General Description

This device contains two inde pendent positive pulse trig­gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-fl ops afte r a complet e clock
pulse. While the clock is LOW the slave is isolated from the
master. On the positive transition of the clock, the data
from the J and K inputs is tra nsferred to the master. While
the clock is HIGH the J and K inpu ts are disabled. On the

negative transition of the clock, the data from the ma ster i s
transferred to the slave. The logic states of the J and K
inputs must not be allowed to change wh ile the clock is
HIGH. Data transfers to the outputs on the falling edge of
the clock pulse. A LOW logic level on the clear input will
reset the outputs regard less of the logic sta tes of the other
inputs.

Ordering Code:

Order Number Package Number Package Description

DM7473N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Connection Diagram Function Table

Inputs Outputs

CLR CLK J K Q Q

LXXXL H



H
H




H



H

H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level



= Posit ive pulse d ata. the J and K inpu ts must be held const ant while

the clock is HIGH. D ata is transferred to the outpu ts on the falling
edge of the clock pulse.

= The output logic level befor e the indicated input conditions were

Q

0

established.

Toggle = Each output changes to the complement of its previous level on

each HIGH level clock pulse.

LL Q0Q
HL H L
LH L H
H H Toggle

0

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Absolute Maximum Ratings(Note 1)

Supply Voltage 7V

DM7473

Input Voltage 5.5V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C

Note 1: The “Absolute Maximum Ratin gs” are those v alues beyon d which
the safety of the dev ice cannot be guaranteed. T he device sh ould not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the c ondit ions
for actual device operation.

Recommended Operating Conditions

Symbol Parameter Min Nom Max Units

V
V
V
I
I
f
t

CC
IH

IL
OH
OL
CLK
W

Supply Voltage 4.75 5 5.25 V
HIGH Level Input Voltage 2 V
LOW Level Input Voltage 0.8 V
HIGH Level Output Current −0.4 mA
LOW Level Ou tput Current 16 mA
Clock Frequency (Note 3) 0 15 MHz
Pulse Width Clock HIGH 20
(Note 3) Clock LOW 47 ns

Clear LOW 25

t

SU

t

H

T

A

Note 2: The symbol (↑, ↓) indicates the edge of the cl oc k pulse is used for referenc e: (↑) for rising ed ge, (↓) for falling edge.
Note 3: T

Input Setup Time (Note 2)(Note 3) 0↑ ns
Input Hold Time (Note 2)(Note 3) 0↓ ns
Free Air Operating Temperature 0 70 °C

= 25°C and VCC = 5V.

A

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ (Note 4) Max Units

V

I

V

OH

V

OL

I

I

I

IH

I

IL

I

OS

I

CC

Note 4: All typicals are at VCC = 5V, TA = 25°C.
Note 5: Not more than one output should be shorted at a time.
Note 6: With all outputs OPEN, I

Input Clamp Voltage VCC = Min, II = −12 mA −1.5 V
HIGH Level VCC = Min, IOH = Max
Output Voltage VIL = Max, VIH = Min
LOW Level VCC = Min, IOL = Max
Output Voltage VIH = Min, VIL = Max
Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA
HIGH Level VCC = Max J, K 40
Input Current VI = 2.4V Clock 80 µA

LOW Level Input VCC = Max J, K −1.6
Current VI = 0.4V Clock −3.2 mA

Short Circuit Output Current VCC = Max (Note 5) −18 −55 mA
Supply Current VCC = Max, (Note 6) 18 34 mA

is measured with the Q and Q outputs HIGH in turn. At the t im e of m easurement the clock input grounded.

CC

Clear 80

Clear −3.2

2.4 3.4 V

0.2 0.4 V

Switching Characteristics at V

Symbol Parameter

f

MAX

t

PHL

t

PLH

t

PHL

t

PLH

Maximum Clock Frequency 15 MHz
Propagation Delay Time HIGH-to-LOW Level Output Clear to Q 40 ns

Propagation Delay Time LOW-to-HIGH Level Output Clear to Q 25 ns
Propagation Delay Time HIGH-to-LOW Level Output Clock to Q or Q 40 ns
Propagation Delay Time LOW-to-HIGH Level Output Clock to Q or Q 25 ns

= 5V and TA = 25°C

CC

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From (Input)

To (Output) Min Max

RL = 400Ω, CL = 15 pF

Units