Fairchild DM74164 service manual
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DM74164
8-Bit Serial In/Parallel Out Shift Registers
DM74164 8-Bit Serial In/Parallel Out Shift Registers
September 1986
Revised February 2000
General Description
These 8-bit shift regi sters feature gated serial inpu ts and
an asynchronous clear. A LOW logic level at either serial
input inhibits entry o f th e n ew d ata , and resets the first fl ipflop to the LOW level at the next clock pulse, thus providing
complete control over incoming data. A HIGH logic level on
either input enables the other input, which will then dete rmine the state of the first f lip-flop. Data at the serial inputs
may be changed while the cloc k is HIG H or LOW, but only
information meeting th e setup and ho ld time require ments
will be entered. Clocking occurs on the LOW-to-HIGH level
transition of the clock input. All inputs are diode-clamped to
minimize transmission-line effects.
Features
■ Gated (enable/disable) serial inputs
■ Fully buffered clock and serial inputs
■ Asynchronous clear
■ Typical clock frequency 36 MHz
■ Typical power dissipation 185 mW
Ordering Code:
Order Number Package Number Package Description
DM74164 N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram Function Table
Inputs Outputs
Q
Clear Clock A B
LXXXLL…L
HLXXQ
H ↑ HHHQAn…Q
H ↑ LX L QAn…Q
H ↑ XL L QAn…Q
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don’t Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH level
, QB0, QH0 = The level of QA, QB, or QH, respectively, before the
Q
A0
indicated steady-state input conditions were established.
, QGn = The level of QA or QG before the most recent ↑ transition of the
Q
An
clock; indicates a one-bit shift.
Q
A
A0QB0
B
Q
…
H
…Q
H0
Gn
Gn
Gn
© 2000 Fairchild Semiconductor Corporation DS006552 www.fairchildsemi.com
Logic Diagram
DM74164
Timing Diagram
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