Fairchild CD4051BC, CD4052BC, CD4053BC Datasheet

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November 1983 Revised August 2000

CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer •

Dual 4-Channel Analog Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer

CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Mul tiplexer/Demultiplexe r • Dual 4-Channel Analog

Multiplexer/Demultiplexer • Triple 2-Channel Analog Mult iplexer/Demultiplexer

General Description

The CD4051BC, CD4 052BC, an d CD405 3BC anal og multiplexers/demultiplexers are digitally controlled analog switches having low “ON” impedance and very low “OFF” leakage currents. Cont rol of analog signals up to 15V

can be achieved by d igital s ignal amplit udes o f 3−15V. For example, if V

nals from 0

−5V. The multiplexer circuits dissipate extremely low qui-

escent power over the full V voltage ranges, independent of the logic state of the control

signals. When a logical “1” is present at the inhibit input terminal all channels are “OFF”.

CD4051BC is a single 8-c hannel multiplexe r having three binary control input s. A , B, and C, and an i nh ibit i n put . T he three binary signals select 1 of 8 channels to be turned “ON” and connect the input to the output.

CD4052BC is a differential 4-channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input sig nals select 1 or 4 pairs of channels to be turned on and connect the differen tial analog inputs to the differential outputs.

CD4053BC is a triple 2-channel multiplexer having three separate digital con trol inputs, A, B , and C, and an i nhibit input. Each control in put selects one of a pair of ch annels which are connected in a single-pole double-throw configuration.

= 5V, V

−5V to +5V can be contro lled by dig ital input s of

= 0V and V

DD−VSS

= −5V, analog sig-

and V

DD−VEE

supply

Features

■ Wide range of digital and analog signal levels: digital 3 – 15V, analog to 15V

■ Low “ON” resistance: 80Ω (typ.) over entire 15V

p-p

signal-i nput range for V

■ High “OFF” resistance: channel leakage of

■ Logic level conversion for digital addressing signals of 3 – 15V (V

to 15 V

■ Matched switch characteristics:

∆R

■ Very low quiescent power dissipation under all digital-control input and supply conditions: 1

µ W (typ.) at V

■ Binary address decoding on chip

− V

p-p

= 5Ω (typ.) for V

p-p

− V

= 15V

±10 pA (typ.) at V

= 3 – 15V) to switch analog signals

= 15V)

− V

= V

= 15V

− V

= 10V

− V

p-p

= 10V

Ordering Code:

Order Number Package Number Package Description

CD4051BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow CD4051BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4051BCMTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide CD4051BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide CD4052BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow CD4052BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4052BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide CD4053BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow CD4053BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4053BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also availab l e in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

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Connection Diagrams

Pin Assignments for DIP and SOIC

CD4051BC CD4052BC

CD4051BC • CD4052BC • CD4053BC

CD4053BC

Truth Table

INPUT STATES “ON” CHANNELS

INHIBIT C B A CD4051B CD4052B CD4053B

0 0 0 0 0 0X, 0Y cx, bx, ax 0 0 0 1 1 1X, 1Y cx, bx, ay 0 0 1 0 2 2X, 2Y cx, by, ax 0 0 1 1 3 3X, 3Y cx, by, ay 0 1 0 0 4 cy, bx, ax 0 1 0 1 5 cy, bx, ay 01106 cy, by, ax 01117 cy, by, ay

*Don’t Care condition.

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1 * * * NONE NONE NONE

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Logic Diagrams

CD4051BC • CD4052BC • CD4053BC

CD4051BC

CD4052BC

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Logic Diagrams (Continued)

CD4051BC • CD4052BC • CD4053BC

CD4053BC

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Absolute Maximum Ratings(Note 1) Recommended Operating

DC Supply Voltage (V Input Voltage (VIN) −0.5 VDC to V

) −0.5 VDC to +18 V

+0.5 V

Storage Temperature

Range (T

Power Dissipation (P

) −65°C to +150°C

)

Dual-In-Line 700 mW Small Outline 500 mW

Lead Temperature (T

)

(soldering, 10 seconds) 260

Conditions

DC Supply Voltage (V

) +5 VDC to +15 V

Input Voltage (VIN) 0V to VDD V Operating Temperature Range (TA)

CD4051BC/CD4052BC/CD4053BC

Note 1: “Absolute Maximum Ratings” are those values bey ond which the safety of the device cannot be guaranteed. Except for “Operating T emperature Range” they are not meant to imply that the devic es should be operated at these limits. Th e Electrical Charact eristics tables provide conditions for actual device operation.

°C

DC Electrical Characteristics (Note 2)

Symbol Parameter Conditions

Control A, B, C and Inhibit

Input Current V

Quiescent Device Current V

= 15V, V

= 0V

= 15V, V

= 15V

= 5V 20 20 150 µA

= 10V 40 40 300 µA

= 15V 80 80 600 µA

Signal Inputs (VIS) and Outputs (VOS)

“ON” Resistance (Peak RL = 10 kΩ V

for V

≤ V

≤ VDD) (any channel V

selected) or V

∆R

∆ “ON” Resistance RL = 10 kΩ V

Between Any Two (any channel V Channels selected) or V

“OFF” Channel Leakage VDD=7.5V, VEE=−7.5V Current, any channel “OFF” O/I=±7.5V, I/O=0V ±50 ±0.01 ±50 ±500 nA “OFF” Channel Leakage Inhibit = 7.5V CD4051 ±200 ±0.08 ±200 ±2000 nA Current, all channels V “OFF” (Common V

= 7.5V,

= −7.5V, D4052 ±200 ±0.04 ±200 ±2000 nA

OUT/IN) O/I = 0V

I/O = ±7.5V CD4053 ±200 ±0.02 ±200 ±2000 nA

Control Inputs A, B, C and Inhibit

V V V or V V V V or V V

DD EE

EE DD EE

= 0V

= 2.5V, = −2.5V

= 5V,

= 0V = 5V, = −5V

= 10V,

= 0V = 7.5V, = −7.5V

= 15V,

= 0V = 2.5V, = −2.5V

= 5V,

= 0V = 5V = −5V

= 10V,

= 0V = 7.5V, = −7.5V

= 15V,

= 0V

−40°C +25°+85°C

Min Max Min Typ Max Min Max

−0.1

−0.1 −10

0.1 10

−5

0.1 1.0 µA

850 270 1050 1200 Ω

330 120 400 520 Ω

210 80 240 300 Ω

10 Ω

5 Ω

CD4051BC • CD4052BC • CD4053BC

DC DC

−40°C to +85°C

Units

−1.0 µA

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DC Electrical Characteristics (Continued)

Symbol Parameter Conditions

LOW Level Input Voltage V

= VSS RL = 1 kΩ to V

IIS<2 µA on all OFF Channels

= VDD thru 1 kΩ

= 5V 1.5 1.5 1.5 V

= 10V 3.0 3.0 3.0 V

= 15V 4.0 4.0 4.0 V

HIGH Level Input Voltage V

Input Current V

= 5 3.5 3.5 3 .5 V

= 10 7 7 7 V

= 15 11 11 11 V

= 15V, V

= 0V

= 15V, V

VIN = 15V

Note 2: All voltages measured with respect to VSS unless otherw ise specifie d.

CD4051BC • CD4052BC • CD4053BC

= 0V

−40°C +25°+85°C

Min Max Min Typ Max Min Max

−5

−0.1 −10

0.1 10

−0.1 −1.0 µA

−5

0.1 1.0 µA

Units

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AC Electrical Characteristics (Note 3)

= 25°C, tr = t

Symbol Parameter Conditions V

PZH,

PZL

PHZ,

PLZ

OUT

IOS

Signal Inputs (VIS) and Outputs (VOS)

PHL

PLH

Control Inputs, A, B, C and Inhibit

PHL,

PLH

Note 3: AC Parameters are guaranteed by DC correl at ed testing. Note 4: A, B are two arbitrary channels with A turned “ON” and B “OFF”.

= 20 ns, unless otherwise specified.

Propagation Delay Time from V

= V

= 0V 5V 600 1200 ns

Inhibit to Signal Output RL = 1 kΩ 10V 225 450 ns (channel turning on) C Propagation Delay Time from V

= 50 pF 15V 160 320 ns

= V

= 0V 5V 210 420 ns

Inhibit to Signal Output RL = 1 kΩ 10V 100 200 ns (channel turning off) C

= 50 pF 15V 75 150 ns

Input Capacitance

Control input 57.5pF

Signal Input (IN/OUT) 10 15 pF Output Capacitance (common OUT/IN)

CD4051 10V 30 pF

CD4052 V

= V

= 0V 10V 15 pF

CD4053 10V 8 pF Feedthrough Capacitance 0.2 pF Power Dissipation Capacitance

CD4051 110 pF

CD4052 140 pF

CD4053 70 pF

Sine Wave Response R (Distortion) f

Frequency Response, Channel R “ON” (Sine Wave Input) 20 log10 VOS/V Feedthrough, Channel “OFF” R

Crosstalk Between Any Two R

= 10 kΩ

= 1 kHz 10V 0.04 %

= 5 V

p-p

= V

= 0V

= 1 kΩ, V

20 log

= 1 kΩ, V

= 0V, V

= −3 dB

= V

= −40 dB

10 VOS/VIS

= VSS = 0V, VIS(A) = 5V

= 5V

, 10V 40 MHz

p-p

= 0V, V

= 5V

, 10V 10 MHz

p-p

Channels (frequency at 40 dB) 20 log10 VOS(B)/VIS(A) = −40 dB (Note 4) Propagation Delay Signal V

= V

= 0V 5V 25 55 ns

Input to Signal Output CL = 50 pF 10V 15 35 ns

Control Input to Signal V

= V

= 0V, RL = 10 kΩ at both ends

Crosstalk of channel. 10V 65 mV (peak)

Input Square Wave Amplitude = 10V

Propagation Delay Time from V

= V

= 0V 5V 500 1000 ns

Address to Signal Output CL = 50 pF 10V 180 360 ns (channels “ON” or “OFF”) 15V 120 240 ns

Min Typ Max Units

10V 3 MHz

15V 10 25 ns

CD4051BC • CD4052BC • CD4053BC

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Special Considerations

In certain applications the external load-resistor current may include both V

avoid drawing V

and signal-line components. To

current when switch current f lows into

IN/OUT pin, the voltage drop across the bidirectional

Typical Performance Characteristics

“ON” Resistance vs Signal

Vo ltage for T

= 25°C

CD4051BC • CD4052BC • CD4053BC

switch must not exceed 0.6V at T

> 25°C (calculated from R

≤ 25°C, or 0.4V at

values shown). No V

current will flow through RL if the switch current flows into OUT/IN pin.

“ON” Resistance as a

Function of Temperature for

− V

= 10V

“ON” Resistance as a

Function of Temperature for

− V

= 15V

“ON” Resistance as a

Function of Temperature for

− V

= 5V

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Switching Time Wavef orms

CD4051BC • CD4052BC • CD4053BC

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Physical Dimensions inches (millimeters) unless otherwise noted

CD4051BC • CD4052BC • CD4053BC

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

CD4051BC • CD4052BC • CD4053BC

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

CD4051BC • CD4052BC • CD4053BC

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

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Package Number MTC16

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

CD4051BC • CD4052BC • CD40 53BC Single 8-Channel Analog Mul tiplexer/Demultiplexe r • Dual 4-Channel Anal og

Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provide d in the l abe ling, can be reasonably expected to result in a significant injury to the user.

Package Number N16E

2. A critical componen t in any com ponen t of a life s uppor t device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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