Fairchild 74VHC4066 service manual

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74VHC4066 Quad Analog Switch
74VHC4066 Quad Analog Switch
April 1994 Revised January 2000
General Description
These devices are di gitally controlled a nalog switches uti­lizing advanced silicon-gate CMOS technology. These
switches have low “on” resista nce and low “off” leakages. They are bidirectional switches, thus any analog inp ut m ay be used as an output and visa-versa. Also the 4066 switches contain linearization circuitry which lowers the “on” resistance and increases switch linearity. The 4066 devices allow control of u p to 12V (peak) analog signals with digital control signals of th e same r ange. Each switch has its own control input which disables ea ch switch when low. All analog inputs and outpu ts and digital inputs are protected from electro static damage by diode s to V
ground.
CC
Features
Typical switch enable time: 15 ns
Wide analog input voltage range: 0–12V
Low “on” resistance: 30 typ. ('4066)
Low quiescent current: 80 µA maximum (74VHC)
Matched switch characteristics
Individual switch controls
Pin and function compatible with the 74HC4066
and
Ordering Code:
Order Number Package Number Package Description
74VHC4066M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74VHC4066MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC4066N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code.
Connection Diagram
Schematic Diagram
Top View
Truth T able
Input Switch
CTL I/O–O/I
L “OFF” H“ON
© 2000 Fairchild Semiconductor Corporation DS011677 www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC) 0.5 to +15V
DC Control Input Voltage (V
74VHC4066
DC Switch I/O Voltage (V Clamp Diode Current (I DC Output Current, per pin (I
or GND Current, per pin
DC V
CC
) ±50 mA
(I
CC
Storage Temperature Range (T Power Dissipation (P
S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds) 260°C
) 1.5 to V
IN
)V
IO
, IOK) ±20 mA
IK
OUT
STG
) (Note 3) 600 mW
D
)
L
0.5 to VCC + 0.5V
EE
) ±25 mA
) 65°C to +150°C
CC
Recommended Operating Conditions
+ 1.5V
Supply Voltage (V DC Input or Output Voltage 0 V
, V
(V
IN
OUT
Operating Temperature Range (T Input Rise or Fall Times (t
= 2.0V 1000 ns
V
CC
= 4.5V 500 ns
V
CC
= 9.0V 400 ns
V
CC
Note 1: Absolute Maximum Ratings are those values beyond which dam­age to the device may occur.
Note 2: Unless otherwise specified all voltages are refe renced to ground. Note 3: Power Dissipation tem perature de rating — pla stic “N” pac kage:
12 mW/°C from 65 °C to 85°C.
)212V
CC
)
) 40 +85 °C
A
, tf)
r
Min Max Units
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions
V
IH
V
IL
R
ON
R
ON
I
IN
I
IZ
I
IZ
I
CC
Note 4: For a pow er supply of 5V ± 10% the worst case on resistance (RON) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case V for CMOS at the higher voltage and so the 5. 5V values should be used.
Note 5: At supply voltages (V these devices be us ed to transmit digital only w hen using these supply v oltages.
Minimum HIGH Level 2.0V 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 V
Maximum LOW Level 2.0V 0.5 0.5 V Input Voltage 4.5V 1.35 1.35 V
Maximum “ON” Resistance V See (Note 5) V
Maximum “ON” Resistance V Matching V
Maximum Control V Input Current VCC = 2 6V Maximum Switch “OFF” V Leakage Current V
Maximum Switch “ON” V Leakage Current V
Maximum Quiescent V Supply Current I
and VIL occur at V
IH
– GND) ap proaching 2V the analog swit c h on resistance becomes extremely non-linear. Therefore it is recommended that
CC
= VIH, IS = 2.0 mA 4.5V 100 170 200
CTL
= VCC to GND 9.0V 50 85 105
IS
(
Figure 1
) 12.0V 30 70 85
V
= VIH, IS = 2.0 mA 4.5V 50 80 100
CTL
V
= VCC or GND 9.0V 35 60 7 5
IS
(
Figure 1
) 12.0V 20 40 60
= V
CTL
IH
= VCC to GND 9.0V 5 10 15
IS
= VCC or GND ±0.05 ±0.5 µA
IN
= VCC or GND 6.0V 10 ±60 ±600 nA
OS
= GND or V
IS
V
CTL
= VCC to GND 6.0V 10 ±40 ±150 nA
IS CTL
VOS = OPEN (
= VCC or GND 6.0V 1.0 10 µA
IN
OUT
= 5.5V and 4.5V res pectively. (The VIH value at 5.5V is 3.85V.) The worst ca s e leakage current occ urs
CC
CC
= VIL (
Figure 2
) 12.0V 20 ±100 ±1000 nA
= V
IH
Figure 3
) 12.0V 20 ±60 ±300 nA
= 0 µA 9.0V 2.0 20 µA
V
CC
9.0V 6.3 5.3 V
12.0V 8.4 8.4 V
9.0V 2.7 2.7 V
12.0V 3.6 3.6 V
2.0V 120 180 215
4.5V 10 15 20
12.0V 5 10 15
9.0V 15 ±80 ±800 nA
9.0V 15 ±50 ±200 nA
12.0V 4.0 40 µA
TA=25°CT
Typ Guaranteed Limits
=−40 to 85°C
A
CC
V
Units
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AC Electrical Characteristics
VCC = 2.0V6.0V VEE = 0V12V, CL = 50 pF (unless otherwise specified)
Symbol Parameter Conditions
t
, t
PHL
t
PZL
t
PHZ
THD Total Harmonic RL = 10 kΩ, CL = 50 pF,
C
IN
C
IN
C
IN
C
PD
Note 6: Adjust 0 dBm for F = 1 kHz (Null RL/RON Attenuation). Note 7: V Note 8: Adjust input fo r 0 dBm.
Maximum Propagation 3.3V 25 30 20 ns
PLH
Delay Switch In to Out 4.5V 5 10 13 ns
, t
Maximum Switch Turn RL = 1 kΩ 3.3V 30 58 73 ns
PZH
“ON” Delay 4.5V 12 20 25 ns
, t
Maximum Switch Turn RL = 1 kΩ 3.3V 60 100 125 ns
PLZ
“OFF” Delay 4.5V 25 36 45 ns
Minimum Frequency RL = 600 4.5V 40 MHz Response (
Figure 7
)V
= 2 VPP at (VCC/2) 9.0V 100 MHz
IS
20 log(VO/VI) = −3 dB (Note 6)(Note 7) Crosstalk Between RL = 600Ω, F = 1 MHz any Two Switches (Note 7)(Note 8) 4.5V 52 dB (
Figure 8
)9.0V−50 dB Peak Control to Switch RL = 600Ω, F = 1 MHz 4.5V 100 mV Feedthrough Noise CL = 50 pF 9.0V 250 mV (
Figure 9
) Switch OFF Signal RL = 600Ω, F = 1 MHz Feedthrough V
(CT) VIL
Isolation (Note 7)(Note 8) 4.5V −42 dB (
Figure 10
)9.0V−44 dB
Distortion F = 1 kHz (
Figure 11
)V
= 4 V
IS
PP
V
= 8 V
IS
PP
Maximum Control 5 10 10 pF Input Capacitance Maximum Switch 20 pF Input Capacitance Maximum Feedthrough V
= GND 0.5 pF
CTL
Capacitance Power Dissipation 15 pF Capacitance
is centered at VCC/2.
IS
V
CC
TA=25°CT
Typ Guaranteed Limits
=−40 to 85°C
A
Units
9.0V 4 8 10 ns
12.0V 3 7 11 ns
9.0V 6 12 15 ns
12.0V 5 10 13 ns
9.0V 20 32 40 ns
12.0V 15 30 38
4.5V .013 %
9.0V .008 %
74VHC4066
3 www.fairchildsemi.com
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