Fairchild 74VHC273 service manual

tm

74VHC273 Octal D-Type Flip-Flop

April 2007

74VHC273
Octal D-Type Flip-Flop

Features

■

High Speed: f
Low power dissipation: I

■

■

High noise immunity: V

■

Power down protection is provided on all inputs
Low noise: V

■

■

Pin and function compatible with 74HC273
Leadless DQFN Package

■

=

165MHz (typ) at V

MAX

NIH

=

0.9V (max)

OLP

=

4µA (max) at T

CC

=

V

NIL

=

28% V

CC

=

5V

=

25°C

A

(min)

CC

General Description

The VHC273 is an advanced high speed CMOS Octal
D-type flip-flop fabricated with silicon gate CMOS tech­nology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.

The register has a common buffered Clock (CP) which is
fully edge-triggered. The state of each D input, one setup
time before the LOW-to-HIGH clock transition, is trans­ferred to the corresponding flip-flop's Q output. The
Master Reset (MR

) input will clear all flip-flops simulta­neously. All outputs will be forced LOW independently of
Clock or Data inputs by a LOW voltage level on the MR
input.

An input protection circuit insures that 0V to 7V can be
applied to the inputs pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.

Ordering Information

Package

Order Number

74VHC273M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74VHC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC273BQ
(Preliminary)

74VHC273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number. Pb-Free package per JEDEC J-STD-020B.

Number Package Description

MLP020B

(Preliminary)

20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 4.5mm

Wide

©1994 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC273 Rev. 1.5

74VHC273 Octal D-Type Flip-Flop

Connection Diagrams

Pin Assignments for

PDIP, SOIC, SOP, and TSSOP

Pad Assignments for DQFN

Logic Symbols

IEEE/IEC

(Top Through View)

Pin Descriptions

Pin Names Description

D

–D

0

7

MR

CP Clock Pulse Input

–Q

Q

0

7

Data Inputs

Master Reset

Data Outputs

Function Table

Operating

Mode

Reset (Clear) L X X L

Load ‘1’ H H H

Load ‘0’ H L L

H

=

HIGH Voltage Level

L

=

LOW Voltage Level

X

=

Immaterial

=

LOW-to-HIGH Transition

Inputs Outputs

MR CP D

n

Q

n

©1994 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC273 Rev. 1.5 2

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.

Figure 1.

74VHC273 Octal D-Type Flip-Flop

©1994 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC273 Rev. 1.5 3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.

Symbol Parameter Rating

V

V

V

I

I

OUT

I

T

CC

IN

OUT

I

IK

OK

CC

STG

T

Supply Voltage –0.5V to +7.0V

DC Input Voltage –0.5V to +7.0V

DC Output Voltage –0.5V to V

Input Diode Current –20mA

Output Diode Current ±20mA

DC Output Current ±25mA

DC V

/GND Current ±75mA

CC

Storage Temperature –65°C to +150°C

Lead Temperature (Soldering, 10 seconds) 260°C

L

CC

+ 0.5V

74VHC273 Octal D-Type Flip-Flop

Recommended Operating Conditions

(1)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Rating

V

CC

V

IN

V

OUT

T

OPR

t

, t

r

Note:

1. Unused inputs must be held HIGH or LOW. They may not float.

Supply Voltage 2.0V to +5.5V

Input Voltage 0V to +5.5V

Output Voltage 0V to V

Operating Temperature –40°C to +85°C

Input Rise and Fall Time,

f

=

V

CC

V

CC

3.3V ± 0.3V

=

5.0V ± 0.5V

0ns/V

0ns/V

∼

100ns/V

∼

20ns/V

CC

©1994 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC273 Rev. 1.5 4