Fairchild 74VHC175 service manual
tm
74VHC175 Quad D-Type Flip-Flop
May 2007
74VHC175
Quad D-Type Flip-Flop
Features
■
High Speed: f
Low power dissipation: I
■
■
High noise immunity: V
■
Power down protection is provided on all inputs
Low noise: V
■
■
Pin and function compatible with 74HC175
=
210MHz (Typ.) at V
MAX
CC
NIH
=
0.8V (Max.)
OLP
=
4µA (Max.) at T
=
V
=
28% V
NIL
CC
CC
=
5V
=
25°C
A
(Min.)
General Description
The VHC175 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The VHC175 is a high-speed quad D-type flip-flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on
the D inputs is stored during the LOW-to-HIGH clock
transition. Both true and complemented outputs of each
flip-flop are provided. A Master Reset input resets all flipflops, independent of the Clock or D inputs, when LOW.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.
Ordering Information
Package
Order Number
74VHC175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number.
Number Package Description
Wide
Connection Diagram Pin Description
Pin Names Description
D
–D
0
3
CP Clock Pulse Input
MR Master Reset Input
–Q
Q
0
3
Q
–Q
0
3
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC175 Rev. 1.2
Data Inputs
Tr ue Outputs
Complement Outputs
74VHC175 Quad D-Type Flip-Flop
Logic Symbol
IEEE/IEC
Functional Description
The VHC175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q
and Master Reset are common. The four flip-flops will
store the state of their individual D inputs on the LOW-toHIGH clock (CP) transition, causing individual Q and Q
outputs to follow. A LOW input on the Master Reset (MR)
will force all Q outputs LOW and Q
pendent of Clock or Data inputs. The VHC175 is useful
for general logic applications where a common Master
Reset and Clock are acceptable.
outputs. The Clock
outputs HIGH inde-
Truth Table
Inputs @ t
MR
D
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
t
=
Bit Time before Clock Pulse
n
=
Bit Time after Clock Pulse
t
n+1
,
n
=
H Outputs @ t
n
LLH
HHL
Q
n
n+1
Q
n
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC175 Rev. 1.2 2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Rating
V
V
V
I
I
OUT
I
T
CC
IN
OUT
I
IK
OK
CC
STG
T
Supply Voltage –0.5V to +7.0V
DC Input Voltage –0.5V to +7.0V
DC Output Voltage –0.5V to V
CC
+ 0.5V
Input Diode Current –20mA
Output Diode Current ±20mA
DC Output Current ±25mA
DC V
/ GND Current ±50mA
CC
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 seconds) 260°C
L
74VHC175 Quad D-Type Flip-Flop
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
V
CC
V
IN
V
OUT
T
OPR
t
, t
r
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
Supply Voltage 2.0V to +5.5V
Input Voltage 0V to +5.5V
Output Voltage 0V to V
Operating Temperature –40°C to +85°C
Input Rise and Fall Time,
f
=
V
CC
V
CC
3.3V ± 0.3V
=
5.0V ± 0.5V
0ns/V
0ns/V
∼
100ns/V
∼
20ns/V
CC
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC175 Rev. 1.2 3
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