Fairchild 74VHC14 service manual

74VHC14
Hex Schmitt Inverter

General Description

The VHC14 is an advanced high speed CMOS Hex
Schmitt Inverter fabricated with silicon gate CMOS technol
ogy. It achieves the high speed operation similar to equiva­lent Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. Pin configuration and function are the
same as the VHC04 but the inputs have hysteresis
between the positive-going and negative-going input
thresholds, which are capable of transforming slowly
changing input signals into sharply defined, jitter-free out
put signals, thus providing greater noise margin than con­ventional inverters.

An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir
cuit prevents device destruction due to mismatched supply
and input voltages.

Features

■ High Speed: tPD = 5.5 ns (typ) at VCC = 5V

-

■ Low power dissipation: ICC = 2 μA (Max) at TA = 25°C

■ High noise immunity: V

■ Power down protection is provided on all inputs

■ Low noise: V

■ Pin and function compatible with 74HC14

-

-

-

OLP

= V

NIH

= 0.8V (Max)

= 28% VCC (Min)

NIL

Ordering Code:

Order Number

74VHC14M
(Note 1)

74VHC14MX_NL
(Note 2)

74VHC14SJ
(Note 1)

74VHC14MTC
(Note 1)

74VHC14MTC_NL
(Note 3)

74VHC14MTCX_NL
(Note 2)

74VHC14N
(Obsolete)

Pb-Free package per JEDEC J-STD-020B.

Note 1: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Note 2: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only.

Note 3: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B).

Package

Number

M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Narrow

4.4mm Wide

4.4mm Wide

Package Description

© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com

Logic Symbol/s

IEEE/IEC

Pin Descriptions

Pin Names Description

A

n

O

n

Inputs

Outputs

Connection Diagram/s

Truth Table/s

A O

L H

H L

www.fairchildsemi.com 2

Absolute Maximum Ratings(Note 4)

Supply Voltage (VCC) −0.5V to +7.0V

DC Input Voltage (VIN) −0.5V to +7.0V

DC Output Voltage (V

) −0.5V to VCC + 0.5V

OUT

Input Diode Current (IIK) −20 mA

Output Diode Current (IOK) ±20 mA

DC Output Current (I

) ±25 mA

OUT

DC VCC/GND Current (ICC) ±50 mA

Storage Temperature (T

) −65°C to +150°C

STG

Lead Temperature (TL)

Soldering (10 seconds) 260°C

DC Electrical Characteristics

Symbol Parameter

V

P

V

N

V

H

V

OH

V

OL

I

IN

I

CC

Positive Threshold Voltage 3.0 2.20 2.20

Negative Threshold Voltage 3.0 0.90 0.90

Hysteresis Voltage 3.0 0.30 1.20 0.30 1.20

HIGH Level Output Voltage 2.0 1.9 2.0 1.9 VIN =V

LOW Level Output Voltage 2.0 0.0 0.1 0.1 VIN = V

Input Leakage Current 0–5.5 ±0.1 ±1.0 μA VIN = 5.5V or GND

Quiescent Supply Current 5.5 2.0 20.0 μA VIN = VCC or GND

V

CC

Min Typ Max Min Max

4.5 3.15 3.15 V

5.5 3.85 3.85

4.5 1.35 1.35 V

5.5 1.65 1.65

4.5 0.40 1.40 0.40 1.40 V

5.5 0.50 1.60 0.50 1.60

3.0 2.9 3.0 2.9 V IOH = −50 μA

4.5 4.4 4.5 4.4

3.0 2.58 2.48

4.5 3.94 3.80 IOH = −8 mA

3.0 0.0 0.1 0.1 V IOL = 50 μA

4.5 0.0 0.1 0.1

3.0 0.36 0.44

4.5 0.36 0.44 IOL = 8 mA

Recommended Operating
Conditions (Note 5)

Supply Voltage (VCC) +2.0V to +5.5V

Input Voltage (VIN) 0V to +5.5V

Output Voltage (V

Operating Temperature (T

Note 4: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. The data book specifica
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari
ables. Fairchild does not recommend operation outside databook specifica­tions.

Note 5: Unused inputs must be held HIGH or LOW. They may not float.

TA = 25°C TA = −40°C to +85°C

) 0V to V

OUT

) −40°C to +85°C

OPR

Units Conditions

V

V

CC

-

-

IL

IOH = −4 mA

IH

IOL = 4 mA

Noise Characteristics

Symbol Parameter

V

OLP

(Note 6)

V

OLV

(Note 6)

V

IHD

(Note 6)

V

ILD

(Note 6)

Note 6: Parameter guaranteed by design.

Quiet Output Maximum Dynamic V

Quiet Output Minimum Dynamic V

Minimum HIGH Level Dynamic Input Voltage

Maximum LOW Level Dynamic Input Voltage

V

CC

OL

OL

5.0 0.4 0.8 V

5.0 −0.4 −0.8 V

5.0 3.5 V

5.0 1.5 V

TA = 25°C

Typ Limits

Units Conditions

CL = 50 pF

CL = 50 pF

CL = 50 pF

CL = 50 pF

3 www.fairchildsemi.com