Fairchild 74VHC125 service manual
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74VHC125 — Quad Buffer with 3-STATE Outputs
December 2007
74VHC125
Quad Buffer with 3-STATE Outputs
Features
■
High Speed: t
Lower power dissipation: I
■
T
25°C
A
■
High noise immunity: V
Power down protection is provided on all inputs
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Low noise: V
Pin and function compatible with 74HC125
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3.8ns (Typ.) at V
PD
NIH
0.8V (Max.)
OLP
4 µA (Max.) at
CC
V
28% V
NIL
CC
5V
CC
(Min.)
General Description
The VHC125 contains four independent non-inverting
buffers with 3-STATE outputs. It is an advanced highspeed CMOS device fabricated with silicon gate CMOS
technology and achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining
the CMOS low power dissipation.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.
Ordering Information
Package
Order Number
74VHC125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
74VHC125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Number Package Description
Narrow
4.4mm Wide
All packages are lead free per JEDEC: J-STD-020B standard.
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC125 Rev. 1.4.0
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74VHC125 — Quad Buffer with 3-STATE Outputs
Connection Diagram
Pin Description
Pin Names Description
A
, B
n
n
O
n
Inputs
Outputs
Logic Symbol
IEEE/IEC
Function Table
Inputs Output
A
n
LL L
LH H
HX Z
HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
X = Immaterial
B
n
O
n
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC125 Rev. 1.4.0 2
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Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Rating
V
V
V
I
I
OUT
I
T
CC
IN
OUT
I
IK
OK
CC
STG
T
Supply Voltage –0.5V to +7.0V
DC Input Voltage –0.5V to +7.0V
DC Output Voltage –0.5V to V
Input Diode Current –20mA
Output Diode Current ±20mA
DC Output Current ±25mA
DC V
/ GND Current ±50mA
CC
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 seconds) 260°C
L
CC
+ 0.5V
74VHC125 — Quad Buffer with 3-STATE Outputs
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
V
CC
V
IN
V
OUT
T
OPR
t
, t
r
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
Supply Voltage 2.0V to +5.5V
Input Voltage 0V to +5.5V
Output Voltage 0V to V
Operating Temperature –40°C to +85°C
Input Rise and Fall Time,
f
V
CC
V
CC
3.3V ± 0.3V
5.0V ± 0.5V
0ns/V ∼ 100ns/V
0ns/V ∼ 20ns/V
CC
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC125 Rev. 1.4.0 3
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