Fairchild 74VHC00 service manual
74VHC00
Quad 2-Input NAND Gate
74VHC00 Quad 2-Input NAND Gate
October 1992
Revised February 2005
General Description
The VHC00 is an advanced high-speed CMOS 2-Input
NAND Gate fabricated with silicon gate CMOS technology.
It achieves the high-spe ed operation similar to eq uivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The internal circuit is composed of 3
stages, including buffer output, which provide high noise
immunity and stable output. An input protection circuit
insures that 0V to 7V can be ap pl ied to th e i n pu t p ins w it hout regard to the supply voltage. This device can be used
to interface 5V to 3V systems and two supply systems such
as battery backup. This circuit prevents de vice destruction
due to mismatched supply and input voltages.
Features
■ High Speed: t
■ High noise immunity: V
■ Power down protection is provided on all inputs
■ Low noise: V
■ Low power dissipation: I
■ Pin and function compatible with 74HC00
3.7ns (typ) at TA 25qC
PD
V
28% VCC (min)
NIL
2 PA (max) at TA 25qC
CC
0.8V (max)
OLP
NIH
Ordering Code:
Order Number
74VHC00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC00MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC00SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC00MTCX_NL
(Note 1)
74VHC00N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free pac k age (per JEDEC J-S T D -020B). Device availa ble in Tape and Reel only.
Logic Symbol
Package
Number
MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Package Description
Connection Diagram
IEEE/IEC
Truth T able
Pin Descriptions
Pin Names Description
A
, B
n
n
O
n
© 2005 Fairchild Semiconductor Corporation DS011504 www.fairchildsemi.com
Inputs
Outputs
ABO
LLH
LHH
HLH
HHL
Absolute Maximum Ratings(Note 2) Recommended Operating
Supply Voltage (VCC)
DC Input Voltage (V
74VHC00
DC Output Voltage (V
Input Diode Current (I
Output Diode Current (I
DC Output Current (I
/GND Current (ICC)
DC V
CC
Storage Temperature (T
Lead Temperature (T
IN
)
OUT
IK
OUT
L
)
)
)
OK
)
)
STG
)
(Soldering, 10 seconds) 260
0.5V to 7.0V
0.5V to 7.0V
0.5V to VCC 0.5V
20 mA
r
20 mA
r
25 mA
r
50 mA
65q
C to 150qC
Conditions
Supply Voltage (V
Input Voltage (V
Output Voltage (V
Operating Temperature (T
Input Rise and Fall Time (t
3.3V r 0.3V 0 ns/V a 100 ns/V
V
CC
5.0V r 0.5V 0 ns/V a 20 ns/V
V
CC
Note 2: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
q
C
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temper ature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications.
Note 3: Unused inputs mus t be held HIGH or LOW. They may not float.
(Note 3)
) 2.0V to 5.5V
CC
)0V to 5.5V
IN
) 0V to V
OUT
OPR
, tf)
r
)
DC Electrical Characteristics
Symbol Parameter
V
HIGH Level 2.0 1.50 1.50
IH
Input Voltage 3.0 5.5 0.7 V
V
LOW Level 2.0 0.50 0.50
IL
Input Voltage 3.0 5.5 0.3 V
V
HIGH Level 2.0 1.9 2.0 1.9
OH
Output Voltage 3.0 2.9 3.0 2.9 or V
V
LOW Level 2.0 0.0 0.1 0.1
OL
Output Voltage 3.0 0.0 0.1 0.1 or V
I
Input Leakage Current 0 5.5
IN
I
Quiescent Supply Current 5.5 2.0 20.0
CC
V
CC
(V)
4.5 4.4 4.5 4.4
3.0 2.58 2.48
4.5 3.94 3.80 IOH 8mA
4.5 0.0 0.1 0.1
3.0 0.36 0.44
4.5 0.36 0.44 I
TA 25qCT
Min Typ Max Min Max
CC
r
CC
0.1
40qC to 85qC
A
0.7 V
CC
0.3 V
Units Conditions
CC
r
1.0
40q
C to 85qC
V
V
VIN VIHIOH 50 PA
V
IL
I
V
VIN VIHIOL 50 PA
V
V
P
AVIN 5.5V or GND
P
AVIN VCC or GND
OH
IL
I
OL
OL
CC
4mA
4 mA
8 mA
Noise Characteristics
V
Symbol Parameter
V
Quiet Output Maximum 5.0 0.3 0.8 V CL 50 pF
OLP
(Note 4) Dynamic V
V
Quiet Output Minimum 5.0
OLV
(Note 4) Dynamic V
V
Minimum HIGH Level 5.0 3.5 V CL 50 pF
IHD
(Note 4) Dynamic Input Voltage
V
Maximum LOW Level 5.0 1.5 V CL 50 pF
ILD
(Note 4) Dynamic Input Voltage
Note 4: Parameter guaranteed by design
OL
OL
(V)
CC
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TA 25qC
Typ Limit
0.3
0.8 V CL 50 pF
Units Conditions
AC Electrical Characteristics
25qCT
Symbol Parameter
t
PLH
t
PHL
Propagation 3.3 r 0.3 5.5 7.9 1.0 9.5
Delay 8.0 11.4 1.0 13.0 CL 50 pF
V
CC
(V)
T
A
Min Typ Max Min Max
5.0 r 0.5 3.7 5.5 1.0 6.5
5.2 7.5 1.0 8.5 C
C
IN
C
PD
Input Capacitance 4 10 10 pF VCC Open
Power Dissipation 19 pF (Note 5)
Capacitance
Note 5: CPD is defined as the value of the internal equivalent capacitance w hich is calculated f rom the operating current consumption without load. Average
operating current ca n be obtained from the eq uation: I
(opr.) CPD * VCC * fIN ICC/4 (per gate).
CC
40qC to 85qC
A
Units Conditions
CL 15 pF
ns
C
15 pF
L
ns
50 pF
L
74VHC00
3 www.fairchildsemi.com
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