Fairchild 74VCX32244 service manual
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74VCX32244
Low Voltage 32-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX32244 contains thirty-two non-inverting buffers
with 3-STATE outputs to be empl oyed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for 8-bit, 16-bit or full 32-bit operation.
The 74VCX32244 is designed for low voltage (1.2V to
3.6V) V
The 74VCX32244 i s fabricated with an advanc ed CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
applications with I/O capability up to 3.6V.
CC
September 2000
Revised November 2002
Features
■ 1.2V to 3.6V VCC supply operation
■ 3.6V tolerant inputs and outputs
■ t
PD
2.5 ns max for 3.0V to 3.6V V
■ Power-off high impedance inputs and outputs
■ Supports live insertion and withdrawal (Note 1)
■ Static Drive (I
±24 mA @ 3.0V V
■ Uses patented noise/EMI reductio n circuitr y
■ Latch-up performance exce eds 300 mA
■ ESD performance:
Human body model
Machine model
■ Packages in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state d uring power up or power
down, OE
should be tied to VCC through a pull-up r esistor; the min imum
value of the res istor is d eter mine d by the cu rre nt-sou rcin g ca pa bility of t he
driver.
OH/IOL
)
CC
> 200V
CC
> 2000V
74VCX32244 Low Voltage 32-Bit Buffer/Line Driver wit h 3.6V Tolerant Inputs and Outputs
Ordering Code:
Order Number Package Number Package Description
74VCX32244G
(Note 2)(Note 3)
Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
BGA96A 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Logic Symbol
© 2002 Fairchild Semiconductor Corporation DS500416 www.fairchildsemi.com
Connection Diagram
74VCX32244
(Top Thru View)
Pin Descriptions
Pin Names Description
OE
I
0–I31
O
0–O31
n
Output Enable Input (Active LOW)
Inputs
Outputs
FBGA Pin Assignments
123456
A O
B O3O2GND GND I
C O5O4V
D O7O6GND GND I
E O9O8GND GND I
F O11O10V
G O13O12GND GND I
H O14O15OE4OE3I
J O17O16OE5OE6I
K O19018GND GND I
L O21O20V
M O23O22GND GND I
N O
P O
R O
T O30O31OE8OE7I
O0OE1OE2I
1
CCVCCI4
CCVCCI10I11
CCVCCI20I21
25O24
27O26VCCVCCI26I27
29O28
GND GND I
GND GND I
0
2
6
8
12I13
15I14
16I17
18I19
22I23
24I25
28I29
31I30
Truth Tables
Inputs Outputs
OE
1
LL L
LH H
HX Z
OE
2
LL L
LH H
HX Z
OE
3
LL L
LH H
HX Z
OE
4
LL L
LH H
HX Z
OE
5
LL L
LH H
HX Z
I
1
I
3
I
5
I
7
I
9
OE
6
LL L
LH H
HX Z
OE
7
LL L
LH H
HX Z
OE
8
LL L
LH H
HX Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
I0-I
3
O0-O
Inputs Outputs
I4-I
7
O4-O
Inputs Outputs
I8-I
11
O8–O
Inputs Outputs
I12-I
15
O12-O
Inputs Outputs
I16-I
19
O16-O
Inputs Outputs
I20-I
23
O20-O
Inputs Outputs
I24-I
27
O24-O
Inputs Outputs
I28-I
31
O28-O
3
7
11
15
19
23
27
31
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Functional Description
The 74VCX32244 contai ns thirty-two non- inverting buffers
with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble fun ction i ng ide ntically, but independent of each other. The control pins may be shorted
together to obtain full 32-bit op eration.The 3-STATE out-
Logic Diagrams
Byte 1 Byte 2
Byte 3 Byte 4
puts are controlled by an Output Enable (OE
is LOW, the outputs are in the 2-state mode. W hen
OE
n
is HIGH, the standard outputs are in the high imped-
OE
n
ance mode but this does not interfere with entering new
data into the inputs.
) input. When
n
74VCX32244
Note: Please note that these diagrams are provided only for the unders t anding of logic operatio ns and should not be used to estimate propagation delays.
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