Fairchild 74VCX16244 service manual
74VCX16244
Low Voltage 16-Bit Buffer/Line Driver with
3.6V Tolerant Inputs and Outputs
74VCX16244 Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
October 1996
Revised June 2005
General Description
The VCX16244 contain s sixteen non-inve rting buffers with
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The 74VCX16244 is designed for low voltage (1.2V to
3.6V) V
The 74VCX16244 i s fabricated with an advanc ed CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
applications with I/O capability up to 3.6V.
CC
Features
■ 1.2V to 3.6V V
■ 3.6V tolerant inputs and outputs
■ t
PD
2.5 ns max for 3.0V to 3.6V V
■ Power-off high impedance inputs and outputs
■ Supports live insertion and withdrawal (Note 1)
■ Static Drive (I
r
24 mA @ 3.0V V
■ Uses proprietary noise/EMI reductio n circui tr y
■ Latch-up performance exce eds 300 mA
■ ESD performance:
Human body model
Machine model ! 200V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE
should be tied to VCC through a pull-up r esistor; the min imum
value of the resistor is dete rmined by the current -sourci ng capabilit y of the
driver.
supply operation
CC
)
OH/IOL
CC
Ordering Code:
Order Number Package Number Package Description
74VCX16244G
(Note 2)(Note 3)
74VCX16244MTD
(Note 3)
Note 2: Ordering Code “G” indicates Tray.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix let te r “X” to the ordering code.
BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
!
2000V
CC
© 2005 Fairchild Semiconductor Corporation DS012168 www.fairchildsemi.com
Logic Symbol
74VCX16244
Pin Descriptions
Pin Names Description
OE
n
I
0–I15
O
0–O15
NC No Connect
Output Enable Input (Active LOW)
Inputs
Outputs
Connection Diagrams
Pin Assignment for TSSOP
Pin Assignment for FBGA
FBGA Pin Assignments
123456
A O
B O
C O
D O
E O
F O
G O
H O
J O
NC OE1OE2NC I
0
O1NC NC I
2
O3V
4
6
8
10
12O11VCCVCCI11
14O13
15
CCVCCI3
O5GND GND I
O7GND GND I
O9GND GND I
NC NC I
NC OE4OE3NC I
Truth Tables
Inputs Outputs
OE
1
I0–I
3
LL L
LH H
HX Z
Inputs Outputs
OE
3
I8-I
11
LL L
LH H
HX Z
Inputs Outputs
OE
2
I4-I
7
LL L
LH H
HX Z
O0–O
O8–O
O4-O
1
5
7
9
13I14
3
11
7
0
I
2
I
4
I
6
I
8
I
10
I
12
15
(Top Thru View)
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Inputs Outputs
OE
4
I12-I
15
O12-O
LL L
LH H
HX Z
H HIGH Voltage Level
LOW Voltage Level
L
X
Immaterial (HIGH or LOW, inputs may not float)
High Impedance
Z
15
Functional Description
The 74VCX16244 contains sixteen non-inverting buffers
with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble fun ction i ng ide nti ca lly, but independent of each other. The control pins may be shorted
together to obtain full 16-bit operation.The 3-STATE out-
Logic Diagram
puts are controlled by an Output Enable (OE
is LOW, the outputs are in the 2-state mode. When
OE
n
is HIGH, the standard outputs are in th e high imped-
OE
n
ance mode but this does not interfere with entering new
data into the inputs.
) input. When
n
74VCX16244
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