Fairchild 74LVX541 service manual

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74LVX541 Low Voltage Octal Buffer/Line Driver with

3-STATE Outputs

74LVX541 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

September 1999 Revised April 2005

General Description

The LVX541 is an octal non-inverting buffer and line driv er designed to be employed as a memory address driver, clock driver and bus or iented tra nsmitter or receive r which provides improved PC board density. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.

Features

■ Input voltage translation from 5V to 3V

■ Ideal for low power/low noise 3.3V applications

■ Guaranteed simultaneous switching noise level and

dynamic threshold performan ce

Ordering Code:

Order Number Package Number Package Description

74LVX541M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVX541SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Surface mount packages are also availab le on Tape and Reel. Specify by appending the suffix let t er “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B.

Connection Diagram Logic Symbol

IEEE/IEC

Pin Descriptions Truth Table

Pin Names Descriptions

, OE

OE

1

I

- I

0

7

- O

O

0

3-STATE Output Enable Inputs

2

Inputs 3-STATE Outputs

7

OE

LLHH HXXZ XHXZ LLLL

H HIGH Voltage Level X Immaterial

LOW Voltage Level Z High Impedance

L

Inputs

OE

1

2

Outputs

I

Absolute Maximum Ratings(Note 1) Recommended Operating

Supply Voltage (VCC) DC Input Diode Current (I

74LVX541

V

0.5V

I

DC Input Voltage (V DC Output Diode Current (I

V

0.5V

O

VCC  0.5V

V

O

DC Output Voltage (V

)

IK

)

I

)

OK

)

O



0.5V to 7.0V



0.5V to VCC  0.5V

DC Output Source

or Sink Current (I

or Ground Current

DC V

CC

(I

or I

CC

GND

Storage Temperature (T

)

O

)

STG

)

65q

C to 150qC

Power Dissipation 180 mW



20 mA



0.5V to 7V



20 mA



20 mA

r

25 mA

r

75 mA

Conditions

Supply Voltage (V Input Voltage (V Output Voltage (V Operating Temperature (TA) Input Rise and Fall Time (

Note 1: The “Absolute Maximum Ratings” are those values bey ond which the safety of the d evice cannot be guaranteed. The device sh ould not be operated at these limi ts. The parametric values define d in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recomme nded O peratin g Cond itions ” table w ill def ine th e cond itions for actual device operation.

Note 2: Unused inputs mus t be held HIGH or LOW. They may not float

(Note 2)

) 2.0V to 3.6V

CC

)0V to 5.5V

I

) 0V to V

O

't/'

V) 0 ns/V to 100 ns/V

DC Electrical Characteristics

Symbol Parameter

V

I

OZ

I

IN

I

CC

HIGH Level Input 2.0 1.5 1.5

IH

LOW Level Input 2.0 0.5 0.5

IL

HIGH Level Output 2.0 1.9 2.0 1.9 IOH 50 PA

OH

Voltage 3.0 2.9 3.0 2.9 V VIN VIH or VILIOH 50 PA

LOW Level Output 2.0 0.0 0.1 0.1 IOL 50 PA

OL

Voltage 3.0 0.0 0.1 0.1 V VIN VIH or VILIOL 50 PA

3-STATE Output OFF-State Current V Input Leakage Current 3.6 Quiescent Supply Current 3.6 4.0 40.0

V

CC

3.6 2.4 2.4

3.6 0.8 0.8

3.0 2.58 2.48 IOH 4 mA

3.0 0.36 0.44 I

3.6

TA 25qCT

Min Typ Max Min Max

r

0.25

r

0.1

40qC to 85qC

A

r

Units Conditions

VVoltage 3.0 2.0 2.0

VVoltage 3.0 0.8 0.8

2.5

P

A

1.0

P

AVIN 5.5V or GND

P

AVIN VCC or GND

40q

VIN VIH or V

VCC or GND

OUT

C to 85qC

4 mA

OL

IL

CC

Noise Characteristics

Symbol Parameter

V

OLP

V

OLV

V

IHD

V

ILD

Note 3: Input tr tf 3 ns.

Quiet Output Maximum Dynamic V Quiet Output Minimum Dynamic V Minimum HIGH Level Dynamic Input Voltage 3.3 2.0 V CL 50 pF Maximum HIGH Level Dynamic Input Voltage 3.3 0.8 V CL 50 pF

(Note 3)

OL

V

CC

(V) Typ Limits

3.3 0.5 0.8 V CL 50 pF

3.3

www.fairchildsemi.com 2



0.5

TA 25qC

Units Conditions



0.8 V CL 50 pF

AC Electrical Characteristics

Symbol Parameter

t

PLH

t

PHL

t

PZL

t

PZH

t

PLZ

t

PHZ

t

OSLH

t

OSHL

Note 4: Parameter guaranteed by design. t

Propagation Delay 2.7 6.1 11.3 1.0 13.5 Time 8.6 14.9 1.0 17.0 CL 50 pF

3-STATE Output 2.7 7.1 13.8 1.0 16.5 Enable Time RL 1 k

3-STATE Output 2.7 11.6 17.9 1.0 20.0 Disable Time 3.3 r 0.3 10.7 15.4 1.0 17.5 RL 1 k Output to Output 2.7 1.5 1.5 Skew (Note 4) 3.3 1.5 1.5

V

CC

(V) Min Typ Max Min Max

3.3 r 0.3 4.7 7.0 1.0 8.5 C

3.3 r 0.3 6.8 10.5 1.0 12.5 C

|t

PLHm

 t

PLHn

OSLH

TA 25qCT

7.2 10.5 1.0 12.0 C

9.6 17.3 1.0 20.0 C

9.3 14.0 1.0 16.0 CL 50 pF

|; t

|t

 t

OSHL

PHLm

PHLn

|.

40qC to 85qC

A

Units Conditions

CL 15 pF

ns

15 pF

L

50 pF

L

CL 15 pF

50 pF

L

RL 1 k

ns

15 pF

L

1 k

R

L

R

1 k

L

CL 50 pF

ns

CL 50 pF

ns

Capacitance

Symbol Parameter

C

IN

C

OUT

C

PD

Note 5: CPD is defined as the value of the internal equiv alent capacitance which is calculated from the operating current co ns umption without load.

Input Capacitance 4 10 10 pF Output Capacitance 6 pF Power Dissipation Capacitance (Note 5) 19 pF

Average operating current can be obtained by the equation: I

TA 25qCT

Min Typ Max Min Max

C

PD

CC(opr.)

40qC to 85qC

A

x VCC x fIN  I

8 (per bit)

CC

74LVX541

:

Units

3 www.fairchildsemi.com