Fairchild 74LVT16245 service manual

January 1999
Revised June 2005

74LVT16245 • 74LVTH16245
Low Voltage 16-Bit Transceiver with 3-STATE Outputs

74LVT16245 • 74LVTH16245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs

General Description

The LVT16245 and LVTH16245 contain sixteen non-invert­ing bidirectional buffers with 3-STATE outputs and is
intended for bus orien ted applications. The de vice is byte
controlled. Each byte has separate control inputs which
can be shorted toget her for full 16-bit ope ration. The T/R
inputs determine the direction of data flow through the
device. The OE
placing them in a high impedance state.

The LVTH16245 data inputs include bushold, elim inating
the need for external pull-up resistors to hold unused
inputs.

These non-inverting transceivers are designed for low-volt­age (3.3V) V

vide a TTL interface to a 5V environment. Th e LVT16245
and LVTH16245 are fabricated with an adva nced B iCMOS
technology to achieve high speed ope ration similar to 5V
ABT while maintaining low power dissipation.

inputs disable both the A and B por ts by

applications, but with the capability to pro-

CC

Features

■ Input and output interface capability to systems at

5V V

CC

■ Bushold data inputs eliminate the need for external

pull-up resistors to hold unus ed inputs (74LVTH16245),
also available without bushold feature (74LVT16245).

■ Live insertion/extraction per mi tt ed

■ Power Up/Down high impedance provides glitch-free

bus loading

■ Outputs source/sink

■ Functionally compatible with the 74 series 16245

■ Latch-up performance exce eds 500 mA

■ ESD performance:

Human-body model !2000V
Machine model
Charged-device !1000V

■ Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

Ordering Code:

Order Number

74LVT16245GX
(Note 1)

74LVT16245MEA
(Note 2)

74LVT16245MTD
(Note 2)

74LVTH16245GX
(Note 1)

74LVTH16245MEA
(Note 2)

74LVTH16245MTD
(Note 2)

Note 1: BGA package available in Tape and Reel only.
Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter “X” t o t he ordering code.

Package

Number

BGA54A

(Preliminary)

MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC M O-153, 6.1mm Wide

BGA54A

(Preliminary)

MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC M O-153, 6.1mm Wide

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]

Package Descript ion



32 mA/64 mA

!

200V

Logic Symbol

© 2005 Fairchild Semiconductor Corporation DS500152 www.fairchildsemi.com

Connection Diagrams

Pin Descriptions

Pin Assignment for SSOP and TSSOP

74LVT16245 • 74LVTH16245

Pin Assignment for FBGA

(Top Thru View)

Pin Names Description

OE
T/R
A

0–A15

B

0–B15

n

n

Output Enable Input (Active LOW)
Transmit/Receive Input

Side A Inputs/3-STATE Outputs
Side B Inputs/3-STATE Outputs

NC No Connect

FBGA Pin Assignments

123456

A B
B B
C B
D B
E B
F B

G B

H B
J B

NC T/R1OE1NC A

0

B1NC NC A

2

B3V

4
6

8
10
12B11VCCVCCA11A12
14B13

15

CCVCCA3

B5GND GND A
B7GND GND A
B9GND GND A9A

NC NC A

NC T/R2OE2NC A

Truth Tables

Inputs

OE1T/R

1

L L Bus B0–B7 Data to Bus A0–A
L H Bus A0–A7 Data to Bus B0–B
H X HIGH–Z State on A0–A7,B0–B

Inputs

T/R

OE

2

2

L L Bus B8–B15 Data to Bus A8–A
L H Bus A8–A15 Data to Bus B8–B
H X HIGH–Z State on A8–A15,B8–B

H HIGH Voltage Level

LOW Voltage Level

L
X

Immaterial
High Impedance

Z

Outputs

Outputs

A

1

A
A

5

A

7

13A14

7
7

7

15
15

15

0
2
4
6
8

10

15

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Functional Description

The LVT16245 and LVTH16245 contain sixteen non-inverting bidirectional buffers with 3-STA TE outputs. The device is byte
controlled with each byte funct ioning iden tically, but independent of the other. The control pins can be short ed together to
obtain full 16-bit operation.

Logic Diagrams

Note: Please note that these diagrams are provided only for the understan ding of logic operations and should not be used to estimate propagation delay s .

74LVT16245 • 74LVTH16245

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