Fairchild 74LCX574 service manual

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±

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74LCX574 Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

February 2006

74LCX574
Low Voltage Octal D-Type Flip-Flop
with 5V Tolerant Inputs and Outputs

Features

5V tolerant inputs and outputs

■

■

2.3V–3.6V V

7.5ns t

■

■

■

■

■

■

■

PD

Power down high impedance inputs and outputs
Supports live insertion/withdrawal

24mA output drive (V
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds JEDEC 78 conditions
ESD performance
– Human body model > 2000V
– Machine model > 200V
Leadless Pb-Free DQFN package

■

specifications provided

CC

max (V

3.3V), 10 µ A I

CC

CC

3.0V)

max

CC

1

General Description

The LCX574 is a high-speed, low power octal flip-flop
with a buffered common Clock (CP) and a buffered
common Output Enable (OE

). The information presented
to the D inputs is stored in the flip-flops on the LOW-to­HIGH Clock (CP) transition.

The LCX574 is functionally identical to the LCX374
except for the pinouts.

The LCX574 is designed for low voltage applications with
capability of interfacing to a 5V signal environment. The
LCX574 is fabricated with an advanced CMOS tech­nology to achieve high speed operation while maintain­ing CMOS low power dissipation.

Ordering Information

Package

Order Number

74LCX574WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LCX574WM_NL

74LCX574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX574BQX

74LCX574MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74LCX574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

74LCX574MTC_NL

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.

Notes:

1. To Ensure the high impedance state during power up or down, OE
value of the resistor is determined by the current-sourcing capability of the driver.

2. DQFN package available in Tape and Reel only

3. “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

2

Number Package Description

3

M20B Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"

Wide

MLP020B Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),

JEDEC MO-241, 2.5 x 4.5mm

Wide

3

MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

should be tied to V

through a pull-up resistor: the minimum

CC

©2006 Fairchild Semiconductor Corporation

74LCX574 Rev. 2.0.0

1

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H =

74LCX574 Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

Logic Symbol

D0D1D2D3D4D5D6D

CP
OE

O

O

0

1O2O3O4O5O6O7

Connection Diagrams

Pin Assignments for

SOIC, SOP, SSOP, TSSOP

OE

1

D

2

0

D

3

1

4

D

2

D

5

3

D

4

6

D

7

5

D

8

6

D

9

7

GND

10

Pad Assignments for DQFN

V

OE

120

D

2

0

D

3

1

D

4

2

D

5

3

D

6

4

D

7

5

D

8

6

D

9

7

10 11

GND

(Top Vie w)

CP

CC

Pin Descriptions

Pin Names Description

7

D

–D

0

7

Data Inputs
CP Clock Pulse Input
OE
O

–O

0

7

3-STATE Output Enable Input

3-STATE Outputs

Truth Table

Inputs Internal Outputs

CP D Q O

20

V

CC

O

19

0

O

18

1

17

O

2

O

16

3

O

4

15

O

14

5

O

13

6

O

12

7

11

CP

HHLNCZHold
HHHNCZHold
HLHZLoad
HHLZLoad

LLHLData Available
LHLHData Available
LHLNCNCNo Change in Data
LHHNCNCNo Change in Data

n

HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

19

O

0

18

O

1

17

O

2

16

O

3

15

O

4

14

O

5

13

O

6

12

O

7

= LOW-to-HIGH Transition
NC = No Change

Functional Description

The LCX574 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com­mon to all flip-flops. The eight flip-flops will store the state
of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) tran­sition. With the Output Enable (OE
the eight flip-flops are available at the outputs. When OE
is HIGH, the outputs go to the high impedance state.
Operation of the OE

input does not affect the loading of

the flip-flops.

FunctionOE

) LOW, the contents of

Logic Diagram

D

0

CP

C

D

Q

OE

O

0

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propaga­tion delays.

74LCX574 Rev. 2.0.0

D

1

CDQCDQCDQCDQCDQCDQCD

O

1

D

2

O

2

D

3

O

3

D

4

O

4

D

5

O

5

D

6

O

6

D

Q

O

7

2

7

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−

−

−

−

+

<

−

<

−

>

+

±

±

±

−

°

=

±

=

±

=

Absolute Maximum Ratings

The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The
device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are
not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the
conditions for actual device operation.

Symbol Parameter Conditions Value Units

V
V
V

I

IK

I

OK

I

O

I

CC

I

GND

T

STG

CC
I
O

Supply V oltage
DC Input Voltage
DC Output Voltage Output in 3-STATE

Output in HIGH or LOW State
DC Input Diode Current V
DC Output Diode Current V

GND

I

GND

O

V

V

O

CC

DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature

0.5 to + 7.0 V

0.5 to + 7.0 V

0.5 to + 7.0 V

4

0.5 to V

CC

0.5
50 mA
50 mA
50
50 mA

100 mA
100 mA

65 to + 150

C

±

−

° C ∆

∆

=

=

74LCX574 Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

Recommended Operating Conditions

5

Symbol Parameter Conditions Min. Max. Units

V

CC

V

I

V

O

I

/

OH

T

A

t

/

Notes:

4. I

O

5. Unused inputs must be held HIGH or LOW. They may not float.

Supply V oltage Operating 2.0 3.6 V

Data Retention 1.5 3.6
Input V oltage 0 5.5 V
Output Voltage HIGH or LOW State 0 V

3-STATE 0 5.5

I

Output Current V

OL

Free-Air Operating Temperature

V Input Edge Rate V

Absolute Maximum Rating must be observed.

3.0V − 3.6V

CC

2.7V − 3.0V

V

CC

V

2.3V − 2.7V

CC

0.8V – 2.0V, V

IN

40 85

3.0V 0 10 ns

CC

CC

24 mA
12

8

V

/

V

74LCX574 Rev. 2.0.0

3

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DC Electrical Characteristics

Symbol Parameter Conditions V

V

V

V

V

I

I

I

OZ

I

OFF

I

CC

∆I

IH

IL

OH

OL

CC

HIGH Level Input Voltage 2.3 − 2.7 1.7 V

LOW Level Input Voltage 2.3 − 2.7 0.7 V

HIGH Level Output Voltage IOH = −100µA 2.3 − 3.6 VCC − 0.2 V

= −8mA 2.3 1.8

I

OH

= −12mA 2.7 2.2

I

OH

= −18mA 3.0 2.4

I

OH

= −24mA 3.0 2.2

I

OH

LOW Level Output Voltage IOL = 100µA 2.3 − 3.6 0.2 V

= 8mA 2.3 0.6

I

OL

= 12mA 2.7 0.4

I

OL

= 16mA 3.0 0.4

I

OL

= 24mA 3.0 0.55

I

OL

Input Leakage Current 0 ≤ VI ≤ 5.5V 2.3 − 3.6 ±5.0 µA
3-STATE Output Leakage 0 ≤ VO ≤ 5.5V,

V

= VIH or V

I

IL

Power-Off Leakage Current VI or VO = 5.5V 0 10 µA
Quiescent Supply Current VI = VCC or GND 2.3 − 3.6 10 µA

3.6V ≤ V

, VO ≤ 5.5V

I

6

Increase in ICC per Input VIH = VCC −0.6V 2.3 − 3.6 500 µA

TA = −40°C to +85°C

(V)

CC

2.7 − 3.6 2.0

2.7 − 3.6 0.8

2.3 − 3.6 ±5.0 µA

2.3 − 3.6 ±10

UnitsMin. Max.

74LCX574 Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

AC Electrical Characteristics

TA = −40°C to +85°C, RL = 500 Ω

VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5 ± 0.2V

CL = 50 pF CL = 50 pF CL = 30 pF

Symbol Parameter

f

MAX

t

PHL

, t

t

PZL

, t

t

PLZ

t

S

t

H

t

W

t

OSHL

t

OSLH

Notes:

6. Outputs disabled or 3-STATE only.

7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the
same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
HIGH (t

74LCX574 Rev. 2.0.0

Maximum Clock Frequency 150 MHz

, t

Propagation Delay,

PLH

CP to O
Output Enable Time 1.5 8.5 1.5 9.5 1.5 10.5 ns

PZH

Output Disable Time 1.5 6.5 1.5 7.0 1.5 7.8 ns

PHZ

n

Setup Time 2.5 2.5 4.0 ns
Hold Time 1.5 1.5 2.0 ns
Pulse Width 3.3 3.3 4.0 ns

,

Output to Output Skew

).

OSLH

7

Min. Max. Min. Max. Min. Max.

1.5 8.5 1.5 9.5 1.5 10.5 ns

1.0 ns

) or LOW-to-

OSHL

4

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Units

Dynamic Switching Characteristics

TA = 25°C

Symbol Parameter Conditions VCC (V)

V

V

OLP

OLV

Quiet Output Dynamic Peak VOLCL = 50pF, VIH = 3.3V, VIL = 0V 3.3 0.8 V

= 30pF, VIH = 2.5V, VIL = 0V 2.5 0.6

C

L

Quiet Output Dynamic Valley V

= 50pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 V

OL CL

= 30pF, VIH = 2.5V, VIL = 0V 2.5 −0.6

C

L

Capacitance

Symbol Parameter Conditions Typical Units

C
C
C

IN
OUT
PD

Input Capacitance VCC = Open, VI = 0V or V
Output Capacitance VCC = 3.3V, VI = 0V or V

CC

CC

7pF
8pF

Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 25 pF

74LCX574 Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

UnitsTypical

74LCX574 Rev. 2.0.0

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