Fairchild 74LCX244 service manual

74LCX244
Low Voltage Buffer/Line Driver

with 5V Tolerant Inputs and Outputs

74LCX244 Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs

February 1994
Revised March 2005

General Description

The LCX244 contains eight non-inverting buffers with
3-STATE out p uts. The device may be em pl oy e d as a me m­ory address driver, clock driver and bus-oriented tra nsmit­ter/receiver. The LCX244 is designe d for low voltage (2.5V
or 3.3V) V

5V signal environment.
The LCX244 is fabrica ted with an advanced CMOS tech-

nology to achieve high speed operation whil e maintaining
CMOS low power dissipation.

applications with capability of interfacing to a

CC

Features

■ 5V tolerant inputs and outputs

■ 2.3V to 3.6V V

■ 6.5 ns t

■ Power down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■

■ Implements patented noise/EMI reduction circuitry

■ Latch-up performance exce eds 500 mA

■ ESD performance:

■ Leadless DQFN Pb-Free package

Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up res istor: the m inimu m value or t he

resistor is determined by the current-so urc ing capability of the driv er.

PD

r

24 mA output drive (VCC 3.0V)

Human body model
Machine model

specifications provided

CC

max (VCC 3.3V), 10 PA ICC max

!

200V

Ordering Code:

Order Number

74LCX244WM
(Note 2)

74LCX244WMX_NL
(Note 4)

74LCX244SJ
(Note 2)

74LCX244BQX
(Note 3)

74LCX244MSA
(Note 2)

74LCX244MTC
(Note 2)

74LCX244MTC_NL
(Note 4)

74LCX244MTCX_NL
(Note 4)

Pb-Free package per JEDEC J-STD-020B.

Note 2: Devices also available in Tape and Reel. Specify by appending the suffix let te r “X” to the ordering code.
Note 3: DQFN package available in Tape and Reel only.
Note 4: “_NL” indicates Pb-Free pac kage (per JEDEC J-STD-020B). Pleas e use order number as indicated.

Package

Number

M20B 20-Lead Small Outline Integrated Circ uit (SOIC), JEDEC MS-013, 0.30 0" Wide

M20B Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MLP020B Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MSA20 20-Lead Shrink Small Outli ne Package (SSOP), JEDEC MO-150, 5.3mm Wide

MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

MO-241, 2.5 x 4.5mm

Wide

Wide

Package Description

!

2000V

© 2005 Fairchild Semiconductor Corporation DS500107 www.fairchildsemi.com

Logic Symbol

Pin Descriptions

IEEE/IEC

74LCX244

Connection Diagrams

Pin Assignments for

SOIC, SOP, SSOP, and TSSOP

Pin Names Description

OE

, OE23-STATE Output Enable In puts

1

I0 – I

7

O

– O

0

7

Truth Tables

Inputs Outputs

OE

1In

LL L
LH H

HX Z

Inputs Outputs

OE2I

n

LL L
LH H

H HIGH Voltage Level
L
X
Z

HX Z

LOW Voltage Level
Immaterial
High Impedance

Inputs

Outputs

(Pins 12, 14, 16, 18)

(Pins 3, 5, 7, 9)

Pad Assignments for DQFN

(Top Through View)

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Absolute Maximum Ratings(Note 5)

Symbol Parameter Value Conditions Units

V
V
V

I

IK

I

OK

I

O

I

CC

I

GND

T

CC
I
O

STG

Supply Voltage
DC Input Voltage
DC Output Voltage

DC Input Diode Current
DC Output Diode Current

DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature



0.5 to 7.0 V



0.5 to 7.0 V



0.5 to 7.0 Output in 3-STATE



0.5 to VCC  0.5 Output in HIGH or LOW State (Note 6)



50 VI  GND mA



50 VO  GND



50 VO ! V

r

50 mA

r

100 mA

r

100 mA



65 to 150

CC

mA

Recommended Operating Conditions (Note 7)

Symbol Parameter Min Max Units

V

CC

V

I

V

O

I

OH/IOL

T

A

't/'

Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The para metric va lues defined in the Elec trical Cha racteristic s tables are n ot guarantee d at the A bsolute Ma ximum R atings . The “Recom-
mended Operating Conditions” table will define the c onditions for actual de v ic e operation.

Note 6: I
Note 7: Unused inputs or I/Os mus t b e held HIGH or LOW. They may not f loat.

Supply Voltage Operating 2.0 3.6

Data Retention 1.5 3.6

V

Input Voltage 0 5.5 V
Output Voltage HIGH or LOW State 0 V

3-STATE 0 5.5

Output Current VCC 3.0V to 3.6V

2.7V to 3.0V

CC

V

2.3V to 2.7V

Free-Air Operating Temperature

CC



40 85

CC

r

24

r

12

r

8

V

mAV

q

C

V Input Edge Rate, VIN 0.8V to 2.0V, VCC 3.0V 0 10 ns/V

Absolute Maximum Rating must be observed.

O

V

q

C

74LCX244

DC Electrical Characteristics

Symbol Parameter Conditions

V

V

V

V

I
I

I

IH

IL

OH

OL

I
OZ

OFF

HIGH Level Input Voltage 2.3 to 2.7 1.7

LOW Level Input Voltage 2.3 to 2.7 0.7

HIGH Level Output Voltage IOH 100 PA 2.3 to 3.6 VCC  0.2

LOW Level Output Voltage IOL 100 PA 2.3 to 3.6 0.2

Input Leakage Current 0 d VI d 5.5V 2.3 to 3.6
3-STATE Output Leakage 0 d VO d 5.5V

Power-Off Leakage Current VI or VO 5.5V 0 10

IOH 8 mA 2.3 1.8
IOH 12 mA 2.7 2.2
IOH 18 mA 3.0 2.4
IOH 24 mA 3.0 2.2

IOL 8 mA 2.3 0.6
IOL 12 mA 2.7 0.4
IOL 16 mA 3.0 0.4
IOL 24 mA 3.0 0.55

VI VIH or V

IL

3 www.fairchildsemi.com

V

TA 40qC to 85qC

CC

(V) Min Max

2.7 to 3.6 2.0

2.7 to 3.6 0.8

r

2.3 to 3.6

r

5.0

5.0

Units

V

V

V

V

P

P

P

A

A

A

DC Electrical Characteristics (Continued)

V

TA 40qC to 85qC

Symbol Parameter Conditions

74LCX244

I

CC

'

I

Note 8: Outputs disabled or 3-STATE only.

Quiescent Supply Current VI VCC or GND 2.3  3.6 10

, VO d 5.5V (Note 8) 2.3  3.6

3.6V d V

Increase in ICC per Input VIH VCC 0.6V 2.3  3.6 500

CC

I

CC

(V) Min Max

r

10

AC Electrical Characteristics

TA 40qC to 85qC, RL 500

3.3V r 0.3V VCC 2.7V VCC 2.5V r 0.2

V

Symbol Parameter

CC

C

50 pF CL 50 pF CL 30 pF

L

Min Max Min Max Min Max

t

PHL

t

PLH

t

PZL

t

PZH

t

PLZ

t

PHZ

t

OSHL

t

OSLH

Note 9: Skew is defined as the absolute value of the difference between t he actual propagat ion delay for any t w o separate outputs of t he same device. The
specification applies to any outputs swi tching in the same direc t ion, either HIGH-to- LOW (t

Propagation Delay 1.5 6.5 1.5 7.5 1.5 7.8
Data to Output 1.5 6.5 1.5 7.5 1.5 7.8
Output Enable Time 1.5 8.0 1.5 9.0 1.5 10.0

1.5 8.0 1.5 9.0 1.5 10.0

Output Disable Time 1.5 7.0 1.5 8.0 1.5 8.4

1.57.01.58.01.58.4

Output to Output Skew
(Note 9)

1.0

1.0

) or LOW-to-HIGH (t

OSHL

OSLH

:

).

Dynamic Switching Characteristics

Symbol Parameter Conditions

V

OLP

V

OLV

Quiet Output Dynamic Peak V

Quiet Output Dynamic Valley V

OL

OL

CL 50 pF, VIH 3.3V, VIL 0V 3.3 0.8
C

30 pF, VIH 2.5V, VIL 0V 2.5 0.6

L

CL 50 pF, VIH 3.3V, VIL 0V 3.3
C

30 pF, VIH 2.5V, VIL 0V 2.5

L

V

(V) Typical

CCTA

25qC



0.8



0.6

Units

P

P

Units

ns

ns

ns

ns

Units

V

V

A

A

Capacitance

Symbol Parameter Conditions Typical Units

C

IN

C

OUT

C

PD

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Input Capacitance VCC Open, VI 0V or V
Output Capacitance VCC 3.3V, VI 0V or V

CC

CC

7.0 pF

8.0 pF

Power Dissipation Capacitance VCC 3.3V, VI 0V or VCC, f 10 MHz 25.0 pF