Fairchild 74LCX16373 service manual

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74LCX16373
Low Voltage 16-Bit Transparent Latch

with 5V Tolerant Inputs and Outputs

74LCX16373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs

February 1994
Revised May 2005

General Description

The LCX16373 con tains sixteen non-inver ting latc hes with
3-STATE outputs and is inten ded for bus orient ed applica­tions. The device is byte cont rolled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE
a high impedance state.

The LCX16373 is designed for lo w voltage (2.5V or 3 .3V)
V

CC

environment.
The LCX16373 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation whil e maintaining
CMOS low power dissipation.

) is LOW. When OE is HIG H, the o utp uts are in

applications with capability of interfacing to a 5V signal

Features

■ 5V tolerant inputs and outputs

■ 2.3V–3.6V V

■ 5.4 ns t

■ Power down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■

r

24 mA output drive (VCC 3.0V)

■ Uses patented noise/EMI reductio n circui tr y

■ Latch-up performance exce eds 500 mA

■ ESD performance:

Human body model ! 2000V
Machine model

■ Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up res istor: the m inimu m value or t he
resistor is determined by the current-sourcing capability of the driver.

specifications provided

CC

max (VCC 3.3V), 20 PA ICC max

PD

!

200V

Ordering Code:

Order Number Package Number Package Description

74LCX16373G
(Note 2)(Note 3)

74LCX16373MEA
(Note 3)

74LCX16373MTD
(Note 3)

Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix let te r “X” to the ordering code.

BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Logic Symbol

© 2005 Fairchild Semiconductor Corporation DS012002 www.fairchildsemi.com

Connection Diagrams

Pin Descriptions

Pin Assignment for SSOP and TSSOP

74LCX16373

Pin Assignment for FBGA

(Top Thru View)

Pin Names Description

OE
LE
I

0–I15

O

0–O15

n

n

Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs

NC No Connect

FBGA Pin Assignments

123456

A O
B O
C O
D O
E O
F O
G O
H O

J O

NC OE1LE1NC I

0

O1NC NC I

2

O3V

4
6

8
10
12O11VCCVCCI11
14O13

15

CCVCCI3

O5GND GND I
O7GND GND I
O9GND GND I

NC NC I

NC OE2LE2NC I

1

5
7
9

13I14

Truth Tables

Inputs Outputs

LE

1

OE

1

XH X Z
HL L L
HL H H
LL X O

Inputs Outputs

LE

2

OE

2

XH X Z
HL L L
HL H H
LL X O

H HIGH Voltage Level

LOW Voltage Level

L
X

Immaterial
High Impedance

Z

Previous O0 before HIGH-to- LOW transition of Latch Enable

O

0

I0–I

I8–I

7

15

O0–O

O8–O

0

I

2

I

4

I

6

I

8

I

10

I

12

15

7

0

15

0

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Functional Description

The LCX16373 contains sixteen D-type latches with
3-STATE standard outpu ts. The device is byte controlled
with each byte functioning iden tically, but independe nt of
the other. Control pi n s can b e s ho rte d to g et h er to ob tain full
16-bit operation. The foll owing description ap plies to each
byte. When the Latch Enab le (LE

enters the latches. In this condit ion the latches are

the I

n

transparent, i.e. a latch outpu t will change state e ach time

) input is HIGH, data on

n

Logic Diagrams

its I input changes. When LE
information that was p resent on the I inputs a setup time

preceding the HIGH-to-LOW transition of LE
3-STATE standard outputs are controlled by the Output

Enable (OE
puts are in the 2-state mode. When OE
dard outputs are in the high impedance mode but this does

not interfere with entering new data into the latches.

) input. When OEn is LOW, the standard out-

n

is LOW, the latches store

n

. The

n

is HIGH, the stan-

n

74LCX16373

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagatio n delays.

3 www.fairchildsemi.com

Absolute Maximum Ratings(Note 4)

Symbol Parameter Value Conditions Units

V

CC

V

I

V

74LCX16373

O

I

IK

I

OK

I

O

I

CC

I

GND

T

STG

Supply Voltage
DC Input Voltage
DC Output Voltage

DC Input Diode Current
DC Output Diode Current

DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature



0.5 to 7.0 V



0.5 to 7.0 V



0.5 to 7.0 Output in 3-STATE



0.5 to VCC  0.5 Output in HIGH or LOW State (Note 5)



50 VI  GND mA



50 VO  GND



50 VO ! V

r

50 mA

r

100 mA

r

100 mA



65 to 150

CC

Recommended Operating Conditions (Note 6)

Symbol Parameter Min Max Units

V

CC

V

I

V

O

I

OH/IOL

T

A

't/'

Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be op erated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operat ing Conditions” table will define the conditions fo r ac t ual device operation.

Note 5: I
Note 6: Unused inputs must be held HIGH or LOW. They may not fl oat .

Supply Voltage Operating 2.0 3.6

Data Retention 1.5 3.6
Input Voltage 05.5 V
Output Voltage HIGH or LOW State 0 V

CC

3-STATE 0 5.5

Output Current VCC 3.0V  3.6V

2.7V  3.0V

CC

V

2.3V  2.7V

CC

Free-Air Operating Temperature



40 85

r

24

r

12

r

8

V Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V 0 10 ns/V

Absolute Maximum Rating must be observed.

O

V

mA

q

C

V

V

mAV

q

C

DC Electrical Characteristics

Symbol Parameter Conditions

V

IH

V

IL

V

OH

V

OL

I

I

I

OZ

I

OFF

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HIGH Level Input Voltage 2.3  2.7 1.7

LOW Level Input Voltage 2.3  2.7 0.7

HIGH Level Output Voltage IOH 100 PA2.3

LOW Level Output Voltage IOL 100 PA2.3

Input Leakage Current 0 d VI d 5.5V 2.3  3.6
3-STATE Output Leakage 0 d VO d 5.5V

Power-Off Leakage Current VI or VO 5.5V 0 10

IOH 8 mA 2.3 1.8
IOH 12 mA 2.7 2.2
IOH 18 mA 3.0 2.4
IOH 24 mA 3.0 2.2

IOL 8 mA 2.3 0.6
IOL 12 mA 2.7 0.4
IOL 16 mA 3.0 0.4
IOL 24 mA 3.0 0.55

VI VIH or V

IL

V

TA 40qC to 85qC

CC

(V) Min Max

2.7  3.6 2.0

2.7  3.6 0.8



3.6 VCC  0.2



3.6 0.2

r

2.3  3.6

r

5.0

5.0

Units

V

V

V

V

P

A

P

A

P

A