Fairchild 74LCX16244 service manual

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74LCX16244
Low Voltage 16-Bit Buffer/Line Driver

with 5V Tolerant Inputs and Outputs

74LCX16244 Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs and Outputs

February 1994
Revised May 2005

General Description

The LCX16244 contains sixteen no n-inverting buffers with
3-STATE outputs designed to be empl oyed as a memory
and address driver, clock driv er, or bus oriented transmi t­ter/receiver. The device is nibble contr olled. Each nibble
has separate 3-STATE control inpu ts which can be shorted
together for full 16-bit operation.

The LCX16244 is designed for low voltage (2 .5 or 3.3V)
V

applications with capability of interfacing to a 5V signal

CC

environment.
The LCX16244 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation whil e maintaining
CMOS low power dissipation.

Features

■ 5V tolerant inputs and outputs

■ 2.3V to 3.6V V

■ 4.5 ns t

■ Power down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■

■ Uses patented noise/EMI reductio n circui tr y

■ Latch-up performance exce eds 500 mA

■ ESD performance:

■ Also packaged in plastic Fine-Pitch Ball Grid Array

Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up res istor: the m inimu m value or t he
resistor is determined by the current-sourcing capability of the driver.

PD

r

24 mA output drive (VCC 3.0V)

Human body model ! 2000V
Machine model

(FBGA)

specifications provided

CC

max, 10 PA I

!

200V

Ordering Code:

Order Number Package Number Package Description

74LCX16244G
(Note 2)(Note 3)

74LCX16244MEA
(Note 3)

74LCX16244MTD
(Note 3)

Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix let te r “X” to the ordering code.

BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

CCQ

max

Logic Symbol

GTO¥ is a trademark of Fairchild Semiconductor Corporation.

© 2005 Fairchild Semiconductor Corporation DS012000 www.fairchildsemi.com

Connection Diagrams

Pin Assignment for SSOP and TSSOP

74LCX16244

Pin Assignment for FBGA

(Top Thru View)

Pin Descriptions

Pin Names Description

OE
I

0–I15

O

0–O15

n

Output Enable Input (Active LOW)

Inputs
Outputs

NC No Connect

FBGA Pin Assignments

123456

A O
B O
C O
D O
E O
F O
G O
H O

J O

NC OE1OE2NC I

0

O1NC NC I

2

O3V

4
6

8
10
12O11VCCVCCI11
14O13

15

CCVCCI3

O5GND GND I
O7GND GND I
O9GND GND I

NC NC I

NC OE4OE3NC I

1

5
7
9

13I14

Truth Tables

Inputs Outputs

OE

1

I0–I

3

LL L
LH H
HX Z

Inputs Outputs

OE

2

I4–I

7

LL L
LH H
HX Z

Inputs Outputs

OE

3

I8–I

11

LL L
LH H
HX Z

Inputs Outputs

OE

4

I12–I

15

LL L
LH H
HX Z

H HIGH Voltage Level

LOW Voltage Level

L

Immaterial

X
Z

High Impedance

O0–O

O4–O

O8–O

O12–O

0

I

2

I

4

I

6

I

8

I

10

I

12

15

3

7

11

15

www.fairchildsemi.com 2

Functional Description

The LCX16244 contains sixteen no n-inverting buffers with
3-STATE standard outputs. The device is nibble (4 bits)
controlled with each ni b ble func ti onin g i d entic al ly, but inde­pendent of the other. The control pins can be shorted
together to obtain ful l 16-bit operation. T he 3-STATE out-

Logic Diagram

puts are controlled by an Output Enable (OE
each nibble. When OE
mode. When OE
impedance mode, but this does not interf ere with e ntering

new data into the inputs.

is LOW, the outputs are in 2-state

n

is HIGH, the outputs are in the high

n

) input for

n

74LCX16244

3 www.fairchildsemi.com

Absolute Maximum Ratings(Note 4)

Symbol Parameter Value Conditions Units

V
V
V

74LCX16244

I

IK

I

OK

I

O

I

CC

I

GND

T

STG

Supply Voltage

CC

DC Input Voltage

I

DC Output Voltage

O

DC Input Diode Current
DC Output Diode Current

DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature



0.5 to 7.0 V



0.5 to 7.0 V



0.5 to 7.0 Output in 3-STATE



0.5 to VCC  0.5 Output in HIGH or LOW State (Note 5)



50 VI  GND mA



50 VO  GND



50 VO ! V

r

50 mA

r

100 mA

r

100 mA



65 to 150

CC

Recommended Operating Conditions (Note 6)

Symbol Parameter Min Max Units

V

CC

V

I

V

O

I

OH/IOL

T

A

't/'

Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be opera t ed
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operat ing Conditions” table will define the conditions fo r ac t ual device operation.

Note 5: I
Note 6: Unused inputs must be held HIGH or LOW. They may not fl oat .

Supply Voltage Operating 2.0 3.6

Data Retention 1.5 3.6
Input Voltage 05.5V
Output Voltage HIGH or LOW State 0 V

CC

3-STATE 0 5.5

Output Current VCC 3.0V  3.6V

2.7V  3.0V

CC

V

2.3V  2.7V

CC

Free-Air Operating Temperature



40 85

r

24

r

12

r

8

V Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V 0 10 ns/V

Absolute Maximum Rating must be observed.

O

V

mA

q

C

V

V

mAV

q

C

DC Electrical Characteristics

Symbol Parameter Conditions

V

IH

V

IL

V

OH

V

OL

I

I

I

OZ

I

OFF

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HIGH Level Input Voltage 2.3  2.7 1.7

LOW Level Input Voltage 2.3  2.7 0.7

HIGH Level Output Voltage IOH 100 PA2.3

LOW Level Output Voltage IOL 100 PA2.3

Input Leakage Current 0 d VI d 5.5V 2.3  3.6
3-STATE Output Leakage 0 d VO d 5.5V 2.3  3.6

Power-Off Leakage Current VI or VO 5.5V 0 10

IOH 8 mA 2.3 1.8
IOH 12 mA 2.7 2.2
IOH 18 mA 3.0 2.4
IOH 24 mA 3.0 2.2

IOL 8 mA 2.3 0.6
IOL 12 mA 2.7 0.4
IOL 16 mA 3.0 0.4
IOL 24 mA 3.0 0.55

VI VIH or V

IL

V

TA 40qC to 85qC

CC

(V) Min Max

2.7  3.6 2.0

2.7  3.6 0.8



3.6 VCC  0.2



3.6 0.2

r
r

5.0

5.0

Units

V

V

V

V

P

P

P

A

A

A