Fairchild 74LCX162374 service manual
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74LCX162374
Low Voltage 16-Bit D-Type Flip-Flop
with 5V Tolerant Inputs and Outputs
and 26
Ω Series Resistors
74LCX162374 Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs and 26
February 2001
Revised August 2001
General Description
The LCX162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus oriented applications. The dev ice is byte controlled. A buffered clock (CP) and Output E nable (OE
each byte and can be shorted together for full 16-bit operation.
The LCX162374 is de si gn ed for l ow vo lt age ( 2.5 V or 3.3V)
V
applications with capability of interfacing to a 5V signal
CC
environment. The 26
reduce output overshoot and undershoot.
The LCX162374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining CMOS low power dissipation.
Ω series resistor in the output helps
) are common to
Features
■ 5V tolerant inputs and outputs
■ 2.3V–3.6V V
■ Equivalent 26
■ 7.0 ns t
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■
±12 mA output drive (V
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exce eds 500 mA
■ ESD performance:
Human body model
Machine model
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up res istor: the m inimu m value or t he
resistor is determin ed by the current-sourc ing capability of the driver.
specifications provided
CC
Ω series resistor on outputs
max (VCC = 3.3V), 20 µA ICC max
PD
> 200V
Ordering Code:
Order Number Package Number Package Description
74LCX162374GX
(Note 2)
74LCX162374MEA
(Note 3)
74LCX162374MTD
(Note 3)
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
BGA54A
(Preliminary)
MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
= 3.0V)
CC
> 2000V
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500442 www.fairchildsemi.com
Ω
Series Resistors
Connection Diagrams
Pin Descriptions
Pin Assignment for SSOP and TSSOP
74LCX162374
Pin Assignment for FBGA
Pin Names Description
OE
CP
I
0–I15
O
0–O15
n
n
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
Outputs
NC No Connect
FBGA Pin Assignments
123456
A O
B O
C O
D O
E O
F O
G O
H O
J O
NC OE1CP1NC I
0
O1NC NC I
2
O3V
4
6
8
10
12O11VCCVCCI11
14O13
15
CCVCCI3
O5GND GND I
O7GND GND I
O9GND GND I
NC NC I
NC OE2CP2NC I
1
5
7
9
13I14
Truth Tables
Inputs Outputs
CP
1
LL X O
XH X Z
OE
1
I0–I
7
O0–O
LH H
LL L
0
I
2
I
4
I
6
I
8
I
10
I
12
15
7
0
(Top Thru View)
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Inputs Outputs
CP
2
OE
2
I8–I
15
O8–O
LH H
LL L
LL X O
XH X Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= Previous O0 before HIGH-to-LOW of CP
O
0
15
0
Functional Description
The LCX162374 consists of sixteen edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The device i s byte contr olled wit h each byte func tioning identically, but independent of the other. The control
pins can be shorted to gether to obtain f ull 1 6-b it o per ati o n.
Each byte h a s a bu ffered clock and buf f ere d O ut p ut En ab le
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
the state of their individual D inputs that meet the setup and
hold time requirements on t he LOW-to-HIGH Clock (CP
transition. With the Output Enable (OE
tents of the flip-flops ar e available at the outputs. When
OE
is HIGH, the outputs go to the high impedan ce state.
n
Operation of the OE
flip-flops.
input does not affect the stat e of the
n
) LOW, the con-
n
74LCX162374
)
n
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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