Fairchild 74LCX162373 service manual

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74LCX162373
Low Voltage 16-Bit Transparent Latch

with 5V Tolerant Inputs and Outputs
and 26

Ω Series Resistor

February 2001
Revised August 2001

Resistor

74LCX162373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs and 26

General Description

The LCX162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears o n the bus when th e Output
Enable (OE
a high impedance state.

The LCX162373 is de si gn ed for l ow vo lt age ( 2.5 V or 3.3V)
V

CC

environment. The 26
reduce output overshoot and undershoot.

The LCX162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain­ing CMOS low power dissipation.

) is LOW. When OE is HIGH, the outputs are in

applications with capability of interfacing to a 5V signal

Ω series resistor in the output helps

Features

■ 5V tolerant inputs and outputs

■ 2.3V–3.6V V

■ Equivalent 26

■ 6.2 ns t

■ Power down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■

±12 mA output drive (V

■ Implements patented noise/EMI reduction circuitry

■ Latch-up performance exce eds 500 mA

■ ESD performance:

Human body model
Machine model

■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)

Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up res istor: the m inimu m value or t he

resistor is determin ed by the current-sourc ing capability of the driver.

specifications provided

CC

Ω series resistor outputs

max (VCC = 3.3V), 20 µA ICC max

PD

> 200V

Ordering Code:

Order Number Package Num ber Package Description

74LCX162373GX
(Note 2)

74LCX162373MEA
(Note 3)

74LCX162373MTD
(Note 3)

Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

BGA54A

(Preliminary)

MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]

= 3.0V)

CC

> 2000V

Logic Symbol

© 2001 Fairchild Semiconductor Corporation DS500443 www.fairchildsemi.com

Ω

Series

Connection Diagrams

Pin Descriptions

Pin Assignment for SSOP and TSSOP

74LCX162373

Pin Assignment for FBGA

(Top Thru View)

Pin Names Description

OE
LE
I

0–I15

O

0–O15

n

n

Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs

NC No Connect

FBGA Pin Assignments

123456

A O
B O
C O
D O
E O
F O
G O
H O

J O

NC OE1LE1NC I

0

O1NC NC I

2

O3V

4
6

8
10
12O11VCCVCCI11
14O13

15

CCVCCI3

O5GND GND I
O7GND GND I
O9GND GND I

NC NC I

NC OE2LE2NC I

1

5
7
9

13I14

Truth Tables

Inputs Outputs

LE

1

XH X Z
HL L L
HL H H
LL X O

LE

2

XH X Z
HL L L
HL H H
LL X O

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

= Previous O0 before HIGH-to-LOW transition of Lat ch Enable

O

0

OE

1

I0–I

7

O0–O

Inputs Outputs

OE

2

I8–I

15

O8–O

0

I

2

I

4

I

6

I

8

I

10

I

12

15

7

0

15

0

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Functional Description

The LCX162373 contains sixteen D-type latches with
3-STATE standard outputs. The device is byte controlled
with each byte functioning iden tically, but independent of
the other. Cont r ol pins can be s h or t ed t o ge t he r to o b t ain f u l l
16-bit operation. The foll owing description ap plies to each
byte. When the Latch Enable (LE

enters the latches. In this condit ion the latches are

the I

n

transparent, i.e. a latch outpu t will change state each time

) input is HIGH, data on

n

Logic Diagrams

its I input changes. When LE
information that was present on the I inputs a setup time

preceding the HIGH-to-LOW transition of LE
3-STATE standard outputs are controlled by the Output

Enable (OE
puts are in the 2-state mode. When OE
dard outputs are in the high impedance mode but this does

not interfere with entering new data into the latches.

) input. When OEn is LOW, the standard out-

n

is LOW, the latches store

n

. The

n

is HIGH, the stan-

n

74LCX162373

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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