Fairchild 74LCX14 service manual
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74LCX14
Low Voltage Hex Inverter
with 5V Tolerant Schmitt Trigger Inputs
74LCX14 Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs
March 1995
Revised February 2005
General Description
The LCX14 contains six inverter gates each with a Schmitt
trigger input. They are capable of transforming slowly
changing input signals in to sharply defined, jitte r-free output signals. In additio n, they have a greater no ise margin
than conventional inverters.
The LCX14 has hysteresis b etween th e posi tive-go ing and
negative-going input thresholds (typically 1.0V) which is
determined internal ly by transistor rati os and is essentially
insensitive to temperature and supply voltage variations.
The inputs tolerate voltages up to 7V allowing the interface
of 5V, 3V and 2.5V systems.
The 74LCX14 is fabrica ted with advanced C MOS technology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
■ 5V tolerant inputs
■ 2.3V–3.6V V
■ 6.5 ns t
■ Power down high impedance inputs and outputs
■
r
24 mA output drive (V
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds JEDEC 78 conditions
■ ESD performance:
Machine model
■ Leadless Pb-Free DQFN package
specifications provided
CC
max (V
PD
Human model ! 2000V
3.3V), 10 PA ICC max
CC
CC
!
200V
3.0V)
Ordering Code:
Order Number
74LCX14M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX14MX_NL
(Note 2)
74LCX14SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX14BQX
(Note 1)
74LCX14MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LCX14MTCX_NL
(Note 2)
Devices also availab l e in Tape and Reel. Specify by appending the suffix let t er “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: DQFN package available in Tape and Reel only.
Note 2: “_NL” indicates Pb-Free pac k age (per JEDEC J-S T D -020B). Device available in Tape and Reel only.
Package
Number
M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MLP014A Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Package Description
© 2005 Fairchild Semiconductor Corporation DS012412 www.fairchildsemi.com
Logic Symbol
Connection Diagrams
74LCX14
Pin Descriptions
Pin Names Description
O
Truth Table
Input Output
AO
L H
H L
IEEE/IEC
I
n
n
Inputs
Outputs
Pin Assignments for SOIC, SOP, and TSSOP
Pad Assignments for DQFN
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(Top View)
Absolute Maximum Ratings(Note 3)
Symbol Parameter Value Conditions Units
V
V
V
I
IK
I
OK
I
O
I
CC
I
GND
T
CC
I
O
STG
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
0.5 to 7.0 V
0.5 to 7.0 V
0.5 to VCC 0.5 Output in HIGH or LOW State (Note 4) V
50 VI GND mA
50 VO GND
50 VO ! V
r
50 mA
r
100 mA
r
100 mA
65 to 150
CC
mA
q
Recommended Operating Conditions (Note 5)
Symbol Parameter Min Max Units
V
V
V
I
OH/IOL
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The para metric va lues defined in the Elec trical Cha racteristic s tables are n ot guarantee d at the A bsolute Ma ximum R atings . The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 4: I
Note 5: Unused inputs must be he ld H I GH or LOW. They may not float.
Supply Voltage Operating 2.0 3.6
CC
Data Retention 1.5 3.6
Input Voltage 05.5V
I
Output Voltage HIGH or LOW State 0 V
O
Output Current VCC 3.0V 3.6V
2.7V 3.0V
CC
2.3V 2.7V
V
CC
Absolute Maximum Rating must be observed.
O
r
r
r
CC
24
12
V
V
mAV
8
74LCX14
C
DC Electrical Characteristics
Symbol Parameter Conditions
V
V
V
V
V
I
I
I
'
t
t
H
OH
OL
I
OFF
CC
I
Positive Input Threshold 2.5 0.9 1.7
Negative Input Threshold 2.5 0.4 1.1
Hysteresis 2.5 0.3 1.0
HIGH Level Output Voltage IOH 100PA2.3
LOW Level Output Voltage IOL 100PA2.3
Input Leakage Current 0 d VI d 5.5V 2.3 3.6
Power-Off Leakage Current VI or VO 5.5V 0 10
Quiescent Supply Current VI VCC or GND 2.3 3.6 10
Increase in ICC per Input VIH VCC 0.6V 2.3 3.6 500
CC
IOH = -8 mA 2.3 1.8
IOH 12 mA 2.7 2.2
IOH 18 mA 3.0 2.4
IOH 24 mA 3.0 2.2
IOL = 8mA 2.3 0.6
IOL 12 mA 2.7 0.4
IOL 16 mA 3.0 0.4
IOL 24 mA 3.0 0.55
3.6V d VI d 5.5V 2.3 3.6
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V
TA 40qC to 85qC
CC
(V) Min Max
3.0 1.2 2.2
3.0 0.6 1.5
3.0 0.4 1.2
3.6 VCC - 0.2
3.6 0.2
r
Units
V
V
V
V
V
5.0
r
10
P
A
P
A
P
A
P
A
AC Electrical Characteristics
40qC to 85qC, RL 500
T
A
74LCX14
Symbol Parameter
V
3.3V r 0.3V VCC 2.7V VCC 2.5V r 0.2V
CC
50 pF CL 50 pF CL 30 pF
C
L
Min Max Min Max Min Max
t
PHL
t
PLH
t
OSHL
t
OSLH
Note 6: Skew is defined as the absolute value of the difference between t he actual propagat ion delay for any t w o separate outputs of t he same device. The
specification applies to any outputs swi tching in the same direc t ion, either HIGH-to- LOW (t
Propagation Delay Time 1.5 6.5 1.5 7.5 1.5 7.8
1.56.51.57.51.57.8
Output to Output Skew 1.0
(Note 6) 1.0
) or LOW-to-HIGH (t
OSHL
OSLH
:
).
Dynamic Switching Characteristics
Symbol Parameter Conditions
V
OLP
Quiet Output Dynamic Peak V
OL
CL 50 pF, VIH 3.3V, VIL 0V 3.3 0.8
CL 30 pF, VIH 2.5V, VIL 0V 2.5 0.6
V
OLV
Quiet Output Dynamic Valley V
OL
CL 50 pF, VIH 3.3V, VIL 0V 3.3
CL 30 pF, VIH 2.5V, VIL 0V 2.5
V
(V) Typical
CCTA
25qC
0.8
0.6
Capacitance
Symbol Parameter Conditions Typical Units
C
IN
C
OUT
C
PD
Input Capacitance VCC Open, VI 0V or V
Output Capacitance VCC 3.3V, VI 0V or V
CC
CC
7pF
8pF
Power Dissipation Capacitance VCC 3.3V, VI 0V or VCC, f 10 MHz 25 pF
Units
ns
ns
Units
V
V
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