Fairchild 74LCX125 service manual
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74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs
February 2008
74LCX125
Low Voltage Quad Buffer with 5V Tolerant
Inputs and Outputs
Features
5V tolerant inputs and outputs
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2.3V–3.6V V
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6.0ns t
PD
Power down high impedance inputs and outputs
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Supports live insertion/withdrawal
±24mA output drive (V
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Implements proprietary noise/EMI reduction circuitry
Latch-up performance exceeds JEDEC 78 conditions
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ESD performance:
– Human body model > 2000V
– Machine model > 100V
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Leadless DQFN package
Note:
1. To ensure the high-impedance state during power up
or down, OE
resistor: the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
specifications provided
CC
max. (V
should be tied to V
3.3V), 10µA I
CC
CC
3.0V)
max.
CC
(1)
through a pull-up
CC
General Description
The LCX125 contains four independent non-inverting
buffers with 3-STATE outputs. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V
systems.
The 74LCX125 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining CMOS low power dissipation.
Ordering Information
Package
Order Number
74LCX125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX125BQX
74LCX125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Note:
2. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Number Package Description
(2)
MLP14A 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
Wide
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX125 Rev. 1.7.0
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74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs
Connection Diagrams
Pin Assignments for SOIC, SOP, and TSSOP
(Top View)
Pad Assignments for DQFN
(Top Through View)
Logic Symbol
Truth Table
Inputs Output
OE
n
LLL
LHH
HXZ
HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
IEEE/IEC
A
n
O
n
Pin Description
Pin Names Description
A
n
OE
n
O
n
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX125 Rev. 1.7.0 2
Inputs
Output Enable Inputs
Outputs
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<
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∆
∆
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Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Rating
V
CC
V
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Note:
3. I
Absolute Maximum Rating must be observed.
O
Supply Voltage –0.5V to +7.0V
DC Input Voltage –0.5V to +7.0V
I
DC Output Voltage,
Output in 3-STATE –0.5V to +7.0V
Output in HIGH or LOW State
DC Input Diode Current, V
GND –50mA
I
(3)
–0.5V to V
DC Output Diode Current
V
V
GND –50mA
O
V
O
CC
DC Output Source/Sink Current ±50mA
DC Supply Current per Supply Pin ±100mA
DC Ground Current per Ground Pin ±100mA
Storage Temperature –65°C to +150°C
CC
+ 0.5V
+50mA
74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs
Recommended Operating Conditions
(4)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Min. Max. Units
V
CC
V
V
O
I
/
OH
T
A
t
/
Note:
4. Unused inputs must be held HIGH or LOW. They may not float.
Supply Voltage
Operating 2.0 3.6 V
Data Retention 1.5 3.6
Input Voltage 0 5.5 V
I
Output Voltage
HIGH or LOW State 0 V
3-STATE 0 5.5
I
Output Current
OL
V
V
V
3.0V–3.6V ±24 mA
CC
2.7V–3.0V ±12
CC
2.3V–2.7V ±8
CC
Free-Air Operating Temperature –40 85 °C
V Input Edge Rate, V
0.8V–2.0V, V
IN
3.0V 0 10 ns
CC
CC
V
/
V
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX125 Rev. 1.7.0 3
DC Electrical Characteristics
Symbol Parameter V
V
V
V
V
I
I
OFF
I
∆I
Note:
5. Outputs disabled or 3-STATE only.
HIGH Level Input Voltage 2.3–2.7 1.7 V
IH
LOW Level Input Voltage 2.3–2.7 0.7 V
IL
HIGH Level Output Voltage 2.3–3.6 I
OH
LOW Level Output Voltage 2.3–3.6 I
OL
I
Input Leakage Current 2.3–3.6 0 ≤ V
I
3-STATE Output Leakage 2.3–3.6 0 ≤ VO ≤ 5.5V,
OZ
Power-Off Leakage Current 0 VI or VO = 5.5V 10 µA
Quiescent Supply Current 2.3–3.6 VI = VCC or GND 10 µA
CC
Increase in ICC per Input 2.3–3.6 VIH = VCC – 0.6V 500 µA
CC
T
–40°C to +85°C
A
(V) Conditions
CC
2.7–3.6 2.0
2.7–3.6 0.8
2.3 I
2.7 I
3.0 I
2.3 I
2.7 I
3.0 I
–100µA V
OH
–8mA 1.8
OH
–12mA 2.2
OH
–18mA 2.4
OH
I
–24mA 2.2
OH
100µA 0.2 V
OL
8mA 0.6
OL
12mA 0.4
OL
16mA 0.4
OL
I
24mA 0.55
OL
≤ 5.5V ±5.0 µA
I
– 0.2 V
CC
±5.0 µA
V
= VIH or V
I
3.6V ≤ V
IL
, VO ≤ 5.5V
I
(5)
±10
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74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs
UnitsMin. Max.
AC Electrical Characteristics
TA = –40°C to +85°C, RL = 500Ω
VCC = 3.3V ± 0.3V,
CL = 50 pF
Symbol Parameter
t
, t
PHL
, t
t
PZL
, t
t
PLZ
, t
t
OSHL
Note:
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (t
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX125 Rev. 1.7.0 4
Propagation Delay 1.5 6.0 1.5 6.5 1.5 7.2 ns
PLH
Output Enable Time 1.5 7.0 1.5 8.0 1.5 9.1 ns
PZH
Output Disable Time 1.5 6.0 1.5 7.0 1.5 7.2 ns
PHZ
Output to Output Skew
OSLH
OSHL
(6)
) or LOW-to-HIGH (t
Min. Max. Min. Max. Min. Max.
1.0 ns
).
OSLH
VCC = 2.7V,
CL = 50 pF
VCC = 2.5V ± 0.2V,
CL = 30 pF
Units
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