Fairchild 74F138 service manual

74F138
1-of-8 Decoder/Demultiplexer

74F138 1-of-8 Decoder/Demultiplexer

April 1988
Revised September 2000

General Description

The F138 is a high-speed 1-of-8 decoder/demultiplexer.
This device is ideally suited for high-speed bipolar memory
chip select address decoding. The multiple input enables
allow parallel expansion to a 1-of-24 decoder using just
three F138 devices or a 1-of-32 d ecoder using four F138
devices and one inverter.

Features

■ Demultiplexing capability

■ Multiple input enable for easy expansion

■ Active LOW mutually exclusive outputs

Ordering Code:

Order Number Package Number Package Description

74F138SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F138PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also availab le in Tape and Reel. Specify by appending the suffix letter “X” to the o rdering code.

Logic Symbols

IEEE/IEC

Connection Diagram

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Unit Loading/Fan Out

74F138

Pin Names Description

A0–A
E

, E

1

E

3

O

0–O7

2
2

Address Inputs 1.0/1.0 20 µA/−0.6 mA
Enable Inputs (Active LOW) 1.0/1.0 20 µA/−0.6 mA
Enable Input (Active HIGH) 1.0/1.0 20 µA/−0.6 mA
Outputs (Active LOW) 50/33.3 −

Truth Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

Functional Description

The F138 high-speed 1-of-8 decoder/demultiplexer
accepts three binary weighted inputs (A

when enabled, provides eight mutually exclusive active
LOW outputs (O

inputs, two active LOW (E
All outputs will be HIGH unless E

). The F138 features three Enable

0–O7

) and one active HIGH (E3).

1, E2

1

is HIGH. This multiple enable function allows easy parallel

0, A1, A2

and E2 are LOW and E

) and,

U.L. Input I

IH/IIL

HIGH/LOW Output IOH/I

expansion of the devi ce to a 1-of-32 (5 lines to 32 lines)
decoder with just four F13 8 devices and one inverter (See
Figure 1). The F138 can be used as an 8-out put demulti­plexer by using one of the active LOW Enable inputs as the
data input and the other Enable inputs as strobes. The
Enable inputs which are not used must be permanently tied

3

to their appropriate active HIGH or active LOW state.

OL

FIGURE 1. Expansion to 1-of-32 Decoding

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Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

74F138

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