Fairchild 74F113 service manual
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74F113
Dual JK Negative Edge-Triggered Flip-Flop
74F113 Dual JK Negative Edge-Triggered Flip-Flop
April 1988
Revised July 1999
General Description
The 74F113 offers individual J, K, Set and Cl ock inputs.
When the clock goes HIGH the inputs are enabled and
data may be entered. The logic level of the J and K inputs
may be changed when the clock pulse is HIGH and the flipflop will perf orm according to the Truth Table as long as
minimum setup and h old tim es are obs erved . Inp ut dat a is
transferred t o the outputs on the falling edge of the clock
pulse.
Asynchronous input:
LOW input to S
Set is independent of clock
sets Q to HIGH level
D
Ordering Code:
Order Number Package Number Package Description
74F113SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F113SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F113PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel . Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009473 www.fairchildsemi.com
Unit Loading/Fan Out
74F113
Pin Names Description
HIGH/LOW
J1, J2, K1, K2Data Inputs 1.0/1.0 20 µA/−0.6 mA
CP
, CP
1
S
, S
D1
D2
Q
, Q2, Q1, Q2Outputs 50/33.3 −1 mA/20 mA
1
Clock Pulse Inputs (Active Falling Edge) 1.0/4.0 20 µA/−2.4 mA
2
Direct Set Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA
Tr uth Table
Inputs Outputs
S
CP JK Q Q
D
LXXXHL
H
H
H
H
H (h) = HIGH Voltage Level
L (l) = LOW Voltage level
]
= HIGH-to-LOW Clock Transition
X = Immaterial
Q
) = Before HIGH-to-LOW Transition of Clock
0 (Q0
Lower case letters indicate the state of the referenced input or output prior to the HIGH-to-LOW clock t r ansition.
hhQ0Q
lhL H
hl H L
llQ0Q
Logic Diagram
(One Half Shown)
U.L.
Input I
IH/IIL
Output I
OH/IOL
0
0
Please not e that this diagram is provided only for the understanding of logic operations and should not be use d to estimate propagation delays.
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