Fairchild 74F109 service manual
74F109
74F109 Dual JK Positive Edge-Triggered Flip-Flop
April 1988
Revised September 2000
Dual JK
General Description
The F109 consists of two high-spe ed, com plete ly inde pendent transition clocked JK
is independent of rise and fall ti m es of th e cloc k w avefor m.
The JK
to F74 data sheet) by connecting the J and K
Positive Edge-Triggered Flip-Flop
Asynchronous Inputs:
LOW input to S
flip-flops. The clocking operat i on
design allows operati on as a D-ty pe flip-flop ( refer
inputs.
LOW input to C
Clear and Set are independent of cloc k
Simultaneous LOW on C
both Q and Q
sets Q to HIGH level
D
sets Q to LOW level
D
and SD makes
D
HIGH
Ordering Code:
Order Number Package Number Package Description
74F109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F109SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F109PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also availab l e in Tape and Reel. Specify by appending su ffix let te r “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
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Truth Table
74F109
Inputs Outputs
S
D
C
D
CP J K QQ
LHXXXHL
HLXXXLH
LLXXXHH
HH
HH
HH
HH
IILH
hI Toggle
IhQQ
hhHL
HHLXXQQ
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
= LOW-to-HIGH Transition
X = Immaterial
Q0 (Q0) = Before LOW-to-HIGH Transition of Clock
Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.
Unit Loading/Fan Out
Pin Names Description
U.L. Input I
HIGH/LOW Output IOH/I
IH/IIL
OL
J1, J2, K1, K2Data Inputs 1.0/1.0 20 µA/−0.6 mA
CP
, CP
1
C
, C
D1
S
, S
D1
Q
, Q2, Q1, Q2Outputs 50/33.3 −1 mA/20 mA
1
Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA
2
Direct Clear Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA
D2
Direct Set Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA
D2
Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings(Note 1) Recommended Operating
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
Pin Potential to
V
CC
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
−55°C to +125°C
−55°C to +175°C
−0.5V to +7.0V
−0.5V to +7.0V
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
Standard Output
cc
= 0V)
−0.5V to V
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
Conditions
Free Air Ambient Temperature 0
Supply Voltage
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired . Functional operation
CC
under these conditions is not implied.
Note 2: Either voltage lim it or c urrent limit is sufficient to protect inputs.
(mA)
DC Electrical Characteristics
74F109
°C to +70°C
+4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
V
V
V
V
I
IH
I
BVI
I
CEX
V
I
OD
I
IL
I
OS
I
CC
IH
IL
CD
OH
OL
ID
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
Input LOW Voltage 0.8 V Recognized as a LOW Signal
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
Output HIGH Voltage 10% V
Output LOW Voltage 10% V
Input HIGH Current 5.0 µAMaxVIN = 2.7V
Input HIGH Current Breakdown Test 7.0 µAMaxVIN = 7.0V
Output HIGH Leakage Current 50 µAMaxV
Input Leakage Test
Output Leakage
Circuit Current All Other Pins Grounded
Input LOW Current −0.6 mA Max VIN = 0.5V (Jn, Kn)
Output Short-Circuit Current −60 −150 mA Max V
Power Supply Current 11.7 17.0 mA Max CP = 0V
5% V
CC
CC
CC
2.5
2.7 IOH = −1 mA
0.5 V Min IOL = 20 mA
4.75 V 0.0
3.75 µA0.0
−1.8 mA Max VIN = 0.5V (CDn, SDn)
V
CC
VMin
IOH = −1 mA
IID = 1.9 µA
All Other Pins Grounded
V
= V
OUT
= 150 mV
IOD
= 0V
OUT
Conditions
CC
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