Fairchild 74ACTQ74 service manual

74ACTQ74
Quiet Series Dual D-Type

Positive Edge-Triggered Flip-Flop

74ACTQ74 Quiet Series Dual D-Type

March 1993
Revised November 1999

General Description

The 74ACTQ74 is a dual D-type flip-flop with Asynchro­nous Clear and Set inputs and complem entary (Q, Q
puts. Information at th e input is transferred to the outputs
on the positive edge of the clock pulse. Clock triggeri ng
occurs at a voltage level of the clock pulse and is not
directly related t o the transition ti me of the positive- going
pulse. After the Clock Pulse input threshold voltage has
been passed, the Data input is lock ed out and infor mation
present will not be transferred to the out puts until the next
rising edge of the Clock Pulse input.

The ACTQ74 utilizes Fairchild Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series features
GTO output control and unde rshoot corre ctor in add ition
to a split ground bus for superior performance.

) out-

Asynchronous Inputs:

LOW input to S
LOW input to C
Clear and Set are independent of clock

Simultaneous LOW on C

both Q and Q

(Set) sets Q to HIGH level

D

(Clear) sets Q to LOW level

D

and SD makes

D

HIGH

Features

■ ICC reduced by 50%

■ Guaranteed simultaneous switching noise level and

dynamic threshold performan ce

■ Guaranteed pin-to-pin skew AC performance

■ Improved latch-up immunity

■ 4 kV minimum ESD immunity

■ TTL-compatible inputs

Ordering Code:

Order Number Package Number Package Description

74ACTQ74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74ACTQ74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form.

Connection Diagram Pin Descriptions

Pin Names Description

D

, D

1

2

CP

, CP

1

C

, C

D1

S

, S

D1

Q

, Q1, Q2, Q

1

2

D2

D2

2

Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs

FACT, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.

© 1999 Fairchild Semiconductor Corporation DS010920 www.fairchildsemi.com

Truth Table

(Each Half)

Inputs Outputs

74ACTQ74

S

C

D

LHXXHL
HLXXLH
LLXXHH
HH
HH
HHLXQ

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial



= LOW-to-HIGH Clo c k Transi ti on

) = Previous Q(Q) before LOW-to-HIGH Transition of Clock

Q

0(Q0

CP D Q Q

D




HHL
LLH

Logic Symbols

Q

0

0

IEEE/IEC

Block Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1) Recommended Operating

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
V

= −0.5V −20 mA

I

= VCC + 0.5V +20 mA

V

I

DC Input Voltage (V
DC Output Diode Current (I

= −0.5V −20 mA

V

O

V

= VCC + 0.5V +20 mA

O

DC Output Voltage (V

)

IK

) −0.5V to VCC + 0.5V

I

)

OK

) −0.5V to VCC + 0.5V

O

DC Output Source

or Sink Current (I

DC V

or Ground Current

CC

per Output Pin (I
Storage Temperature (T

) ± 50 mA

O

or I

CC

) ± 50 mA

GND

) −65°C to +150°C

STG

DC Latch-Up Source or Sink Current ± 300 mA
Junction Temperature (T

) PDIP 140°C

J

Conditions

Supply Voltage (V
Input Voltage (V
Output Voltage (VO) 0V to V
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate ∆V/∆t
V

from 0.8V to 2.0V

IN

@ 4.5V, 5.5V 125 mV/ns

V

CC

Note 1: Absolute maximu m rating s are thos e values be yond wh ich dam­age to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its
power supply, temperature, an d output/input loading variables. Fair child
does not re c om m end operation of FACT circuit s outside databook s pecifi­cations.

) 4.5V to 5.5V

CC

) 0V to V

I

DC Electrical Characteristics

V

Symbol Parameter

V

Minimum HIGH Level 4.5 1.5 2.0 2.0

IH

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

V

Maximum LOW Level 4.5 1.5 0.8 0.8

IL

Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V

V

Minimum HIGH Level 4.5 4.49 4.4 4.4

OH

Output Voltage 5.5 5.49 5.4 5.4

V

Maximum LOW Level 4.5 0.001 0.1 0.1

OL

Output Voltage 5.5 0.001 0.1 0.1

Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND

I

IN

I

Maximum 3-STATE

OZ

Leakage Current VO = VCC, GND

I

Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V

CCT

I

Minimum Dynamic 5.5 75 mA V

OLD

I

Output Current (Note 2) 5.5 −75 mA V

OHD

I

Maximum Quiescent Supply Current 5.5 2.0 20.0 µAVIN = VCC or GND

CC

V

Quiet Output Maximum

OLP

Dynamic V

V

OLV

V

IHD

V

ILD

Note 2: All outputs loaded; thres holds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: PDIP package.
Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 6: Max number of data input s (n ) s w it c hing. (n − 1) inputs switching 0V to 3V. Input-under-test swit ch ing:

OL

Quiet Output Minimum
Dynamic V

OL

Minimum HIGH Level Dynamic Input Voltage 5.0 1.9 2.2 V (Note 4)(Note 6)
Maximum LOW Level Dynamic Input Voltage 5.0 1.2 0.8 V (Note 4)(Note 6)

3V to threshold (V

), 0V to threshold (V

ILD

IHD

CC

(V) Typ Guaranteed Limits

4.5 3.86 3.76

5.5 4.86 4.76

4.5 0.36 0.44

5.5 0.36 0.44

5.5 ± 0.5 ± 5.0 µA

5.0 1.1 1.5 V

5.0 −0.6 −1.2 V

), f = 1 MHz.

TA = +25°C TA = −40°C to +85°C

Units Conditions

V

V

VI

V

VI

V

CC
CC

V

= 0.1V

OUT

V

= 0.1V

OUT

= −50 µA

OUT

VIN = V

or V

IL

IOH = −24 mA
IOH = −24 mA (Note 2)

OUT

VIN = VIL or V
IOL = 24 mA
I

OL

VI = VIL, V

OLD
OHD

Figure 1, Figure 2
(Note 4)(Note 5)
Figure 1, Figure 2
(Note 4)(Note 5)

IH

= 50 µA

IH

= 24 mA (Note 2)

IH

= 1.65V Max
= 3.85V Min

74ACTQ74

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