Fairchild 74ACTQ153 service manual

74ACTQ153
Quiet Series Dual 4-Input Multiplexer

74ACTQ153 Quiet Series Dual 4-Input Multiplexer

July 1990
Revised March 2001

General Description

The ACTQ153 is a high-speed dual 4-input multiplexer with
common select inputs and individual enable inputs for each
section. It can select two lines of data fro m four sources.
The two buffered outputs present data in the true (non­inverted) form. In addition to multiplexer operation, the
ACTQ153 can act as a function gene rator and generate
any two functions of three variables.

Features

■ Outputs source/sink 24 mA

■ ACTQ153 has TTL-compatible inputs

■ Guaranteed simultaneous switching noise level and

dynamic threshold performan ce

■ Improved latch-up immunity

Ordering Code:

Order Number Package Number Package Description

74ACTQ153SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74ACTQ153PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the or dering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

Pin Names Description

- 1

I

0a

3a

I

- 1

0b

3b

S

, S

0

1

E

a

E

b

Z

a

Z

b

FACT, FACT Quiet Series, and GTO are trademarks of F airchild Semiconduc t or Corporation.

© 2001 Fairchild Semiconductor Corporation DS010244 www.fairchildsemi.com

Side A Data Inputs
Side B Data Inputs

Common Select Inputs

Side A Enable Input
Side B Enable Input

Side A Output
Side B Output

Functional Description

The ACTQ153 is a dual 4-in put multiplexer. It can select
two bits of data from up to four sources under the control of
the common Select inputs (S

plexer circ ui ts ha v e in di vi d ua l ac t iv e- L OW En ab les ( E

74ACTQ153

which can be used to strobe the outputs independently.
When the Enables ( E

outputs ( A

, Zb) are forced LOW. The ACTQ153 is the logic

z

, S1). The two 4-input multi-

0

, Eb) are HIGH, the corre sponding

a

implementation of a 2-pole, 4-position switch, where the
position of the switch is deter min ed by the log i c levels sup ­plied to the Select input s. The logic equatio ns for the out­puts are shown below.

Z

= Ea • (I0a • S1 • S0 + I1a • S1 • S0 +

a

I2a • S1 •S0 + I3a • S1 • S0)

= Eb • (I0b • S1 • S0 • I1b • S1 • S0 +

Z

b

• S1 • S0 +I3b • S1 • S0)

I

2b

Logic Diagram

a

, Eb)

Truth Table

Select
Inputs

S

0S1

XXHXXXX L
LLLLXXX L
LLLHXXX H
HLLXLXX L

HLLXHXX H
LHLXXLX L
LHLXXHX H
HHLXXXL L
HHLXXXH H

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

Inputs (a or b) Outputs

I0I1I2I

E

3

Z

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1) Recommended Operating

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

V

= −0.5V −20 mA

I

= VCC + 0.5V +20 mA

V

I

DC Input Voltage (V
DC Output Diode Current (I

= −0.5V −20 mA

V

O

V

= VCC + 0.5V +20 mA

O

DC Output Voltage (V

)

IK

) −0.5V to VCC + 0.5V

I

)

OK

) −0.5V to VCC + 0.5V

O

DC Output Source

or Sink Current (I

DC V

or Ground Current

CC

per Output Pin (I
Storage Temperature (T
DC Latch-Up Source or Sink Current
Junction Temperature (T

) ±50 mA

O

or I

CC

) ±50 mA

GND

) −65°C to +150°C

STG

±300 mA

)

J

PDIP 140

Conditions

Supply Voltage (V
Input Voltage (V
Output Voltage (VO)0V to V
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate

V

from 0.8V to 2.0V

IN

@ 4.5V, 5.5V 125 mV/ns

V

CC

Note 1: Absolute max imum ratings are those values beyon d w hich damage
to the device may occu r. The databook spe cificatio ns shou ld be met, w ith­out exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specific at ions.

°C

) 4.5V to 5.5V

CC

)0V to V

I

∆V/∆t

DC Electrical Characteristics

V

Symbol Parameter

V

V

V

V

I
I
I
I
I
V

V
V
V

Minimum HIGH Level 4.5 1.5 2.0 2.0

IH

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V
Maximum LOW Level 4.5 1.5 0.8 0.8

IL

Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V
Minimum HIGH Level 4.5 4.49 4.4 4.4

OH

Output Voltage 5.5 5.49 5.4 5.4

Maximum LOW Level 4.5 0.001 0.1 0.1

OL

Output Voltage 5.5 0.001 0.1 0.1

Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µAVI = VCC, GND

IN

Maximum ICC/Input 5.5 0.6 1.5 µAVI = VCC − 2.1V

CCT

Minimum Dynamic 5.5 75 mA V

OLD

Output Current (Note 3) 5.5 −75 mA V

OHD

Maximum Quiescent Supply Current 5.5 8.0 80.0 µAVIN = VCC or GND

CC

Maximum HIGH Level

OLP

Output Noise (Note 4)(Note 5)
Maximum LOW Level Output Noise 5.0 −0.6 −1.2 V Figures 1, 2

OLV

Minimum HIGH Level Dynamic Input Voltage 5.0 1.9 2.2 V (Note 4)(Note 6)

IHD

Maximum LOW Level Dynamic Input Voltage 5.0 1.2 0.8 V (Note 4)(Note 6)

ILD

Note 2: All outputs loaded; thres holds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: Worst case package.
Note 5: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One Data Input @ V
Note 6: Max number of Data Inputs (n) switching. (n−1) inputs switching 0V to 5V. Input-under-tes t switching:

5V to threshold (V

), 0V to threshold (V

ILD

), f = 1 MHz.

IHD

CC

(V) Typ Guaranteed Limits

4.5 3.86 3.76 IOH = −24 mA

5.5 4.86 4.76 I

4.5 0.36 0.44 IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

5.0 1.1 1.5 V

TA = +25°CTA = −40°C to +85°C

= GND.

IN

Units Conditions

V

V

VI

V

VI

V

V

= 0.1V

OUT

V

= 0.1V

OUT

= −50 µA

OUT

VIN = VIL or VIH

= −24 mA (Note 2)

OH

= 50 µA

OUT

VIN = VIL or V

= 1.65V Max

OLD

= 3.85V Min

OHD

Figures 1, 2

74ACTQ153

CC
CC

IH

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