Fairchild 74ACT16240 service manual

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74ACT16240
16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs

74ACT16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs

August 1999
Revised October 1999

General Description

The ACT16240 contain s sixteen inverting buffers with 3­STATE outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver. The device is nibble controlled. Each nibble has
separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.

Features

■ Separate control logic for each byte

■ 16-bit version of the ACT240

■ Outputs source/sink 24 mA

■ TTL-compatible inputs

Ordering Code:

Order Number Package Number Package Description

74ACT16240SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACT16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code .

Logic Symbol

Connection Diagram

Pin Descriptions

Pin Names Description

OE

n

I

0–I15

O

0–O15

FACT is a trade m ark of F airchild Semicondu ctor Corporation.

© 1999 Fairchild Semiconductor Corporation DS500293 www.fairchildsemi.com

Output Enable Inputs (Active LOW)
Inputs
Outputs

Truth Tables

74ACT16240

Inputs Outputs

OE

1

I0–I

3

O0–O

LL H
LH L
HX Z

Inputs Outputs

OE

3

I8–I

11

O8–O

LL H
LH L
HX Z

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

Functional Description

The ACT16240 contains sixteen inverting buffers with 3­STATE standar d outp uts. Th e device is nibb le (4 bits) con­trolled with each nibble fun c tion ing i de ntica lly, but indepen­dently of the other. The control pins may be shorted
together to obtain full 16-bit operation. The 3-STATE ou t­puts are controlled by an Output Enable (OE

each nibble. When O E
mode. When OE

is LOW, the outputs are in 2-state

n

is HIGH, the outputs are in the high

n

impedance mode, but this doe s not interfere with enterin g
new data into the inputs.

n

3

11

) input for

Inputs Outputs

OE

2

I4–I

7

O4–O

LL H
LH L
HX Z

Inputs Outputs

OE

4

I12–I

15

O12–O

LL H
LH L

HX Z

Logic Diagram

7

15

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Absolute Maximum Ratings(Note 1) Recommended Operating

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

V

I

DC Output Diode Current (I

V

= −0.5V −20 mA

O

= VCC + 0.5V +20 mA

V

O

DC Output Voltage (V
DC Output Source/Sink Current (I

or Ground Current

DC V

CC

)

IK

)

OK

) −0.5V to VCC + 0.5V

O

) ± 50 mA

O

per Output Pin ± 50 mA
Junction Temperature +140°C
Storage Temperature −65°C to +150°C

Conditions

Supply Voltage (V
Input Voltage (V
Output Voltage (VO)0V to V
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t) 125 mV/ns

from 0.8V to 2.0V

V

IN

V

@ 4.5V, 5.5V

CC

Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with­out exception to ensure that the system design is reliable over its power
supply, temperature, and ou tput/inp ut load ing vari ables. Fairchild does n ot
recommend operat ion of FACT circuits outside da t abook specifications .

) 4.5V to 5.5V

CC

)0V to V

I

DC Electrical Characteristics

V

Symbol Parameter

V

Minimum HIGH 4.5 1.5 2.0 2.0

IH

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

V

Maximum LOW 4.5 1.5 0.8 0.8

IL

Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V

V

Minimum HIGH 4.5 4.49 4.4 4.4

OH

Output Voltage 5.5 5.49 5.4 5.4

V

Maximum LOW 4.5 0.001 0.1 0.1

OL

Output Voltage 5.5 0.001 0.1 0.1

I

Maximum 3-STATE

OZ

Leakage Current VO = VCC, GND

I

Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND

IN

I

Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V

CCT

I

Max Quiescent Supply Current 5.5 8.0 80.0 µAVIN = VCC or GND

CC

I

Minimum Dynamic

OLD

I

Output Current (Note3) −75 mA V

OHD

Note 2: All outputs loaded; thresholds assoc iated with output und er t es t .
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.

CC

(V) Typ Guaranteed Limits

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 IOH = −24 mA (Note 2)

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

5.5 ±0.5 ±5.0 µA

5.5

TA = +25°C

TA = −40°C to +85°C

75 mA V

Units Conditions

V

V

VI

VI

V

= 0.1V

OUT

V

= 0.1V

OUT

= −50 µA

OUT

VIN = VIL or V

= 50 µA

OUT

VIN = VIL or V

VI = VIL, V

IH

= 1.65V Max

OLD

= 3.85V Min

OHD

74ACT16240

CC
CC

IH

IH

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