The 6N137, EL2601 and EL2611 are consists of an infrared
emitting diode optically coupled to a high speed integrated
photo detector logic gate with a strobable output.
It is packaged in a 8-pin DIP package and available in
wide-lead spacing and SMD options.
Applications
• Ground loop elimination
• LSTTL to TTL, LSTTL or 5 volt CMOS
• Line receiver, data transmission
• Data multiplexing
• Switching power supplies
• Pulse transformer replacement
• Computer peripheral interface
Truth Table (Positive Logic)
Input Enable Output
H H L
L H H
H L H
A 0.1µF bypass capacitor must be
connected between pins 8 and 5 *3
*3 The VCC supply must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid
tantalum capacitor with good high frequency characteristic and should be connected as close as possible to
the package VCC and GND pins
*4. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
*5. tPLH– Propagation delay is measured from the 3.75mA level on the HIGH to LOW transition of the input
current pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
*6. tPHL– Propagation delay is measured from the 3.75mA level on the LOW to HIGH transition of the input
current pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
*7. tr– Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output
pulse.
*8. tf– Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output
pulse.
*9. tELH– Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of
the input voltage pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
*10. tEHL– Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of
the input voltage pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
*11 CMH– The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in
the HIGH state (i.e., VOUT > 2.0V).
*12 CML– The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in
the LOW output state (i.e., VOUT < 0.8V).
Order Information
Part Number
6N137Y(Z)-V
Or
EL26XXY(Z)-V
Note
X = (01 or 11) for EL26 part no.
Y = Lead form option (S, S1, M or none)
Z = Tape and reel option (TA, TB or none).
V = VDE (optional)
Option Description Packing quantity
None Standard DIP-8 45 units per tube
M Wide lead bend (0.4 inch spacing) 45 units per tube
S (TA) Surface mount lead form + TA tape & reel option 1000 units per reel
S (TB) Surface mount lead form + TB tape & reel option 1000 units per reel
S1 (TA) Surface mount lead form (low profile) + TA tape & reel option 1000 units per reel
S1 (TB) Surface mount lead form (low profile) + TB tape & reel option 1000 units per reel