ETRON EM6A9320BI-5, EM6A9320BI-4, EM6A9320BI-3.5, EM6A9320BI-3.3, EM6A9320BI-3.0 Datasheet

Etr onT ech

EM6A9320

4M x 32 DDR SDRAM

Etron Confidential Preliminary (Rev 0.3 7/2002)

Features

Fast clock rate: 350/333/300/285/250/200 MHz

•

Differential Clock CK & CK# input

•

4 Bi-directional DQS. Data transactions on both

•

edges of DQS (1DQS / Byte)

DLL aligns DQ and DQS transitions

•

Edge aligned data & DQS output

•

Center aligned data & DQS input

•

4 internal banks, 1M x 32-bit for each bank

•

Programmable mode and extended mode registers

•

- CAS# Latency: 3, 4, 5

- Burst length: 2, 4, 8

- Burst Type: Sequential & Interleave
Full page burst length for sequential type only

•

Start address of full page burst should be even

•

All inputs except DQ’s & DM are at the positive

•

edge of the system clock

No Write-Interrupted by Read function

•

4 individual DM control for write masking only

•

Auto Refresh and Self Refresh

•

4096 refresh cycles / 32ms

•

Power supplies up to 350/333/300/285MHz:

•

V

V

Power supplies up to 250/200MHz:

•

V

V

Interface : SSTL_2 I/O compatible

•

6WDQGDUG EDOO )%*$ SDFNDJH

•

= 2.8V ± 5%

DD

= 2.8V ± 5%

DDQ

= 2.5V ± 5%

DD

= 2.5V ± 5%

DDQ

Overview

The EM6A9320 DDR SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 128
Mbits. It is internally configured as a quad 1M x 32
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal, CK).

Data outputs occur at both rising edges of CK and CK#.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence.

Accesses begin with the registration of a BankActivate
command, which is then followed by a Read or Write
command.

The EM6A9320 provides programm able Read or Write
burst lengths of 2, 4, 8. An auto precharge function m ay
be enabled to provide a self-timed row prechar ge that is
initiated at the end of the burst sequence.

The refresh functions, either Auto or Self Refresh are
easy to use.

In addition, EM6A9320 features programmable DLL
option. By having a programmable mode register and
extended mode register, the system can choose the
most suitable modes to maximize its performance.

These devices are well suited f or applications requiring
high memory bandwidth, result in a device particularly
well suited to high performance main memory and
graphics applications.

Ordering Information

Part Number

EM6A9320BI-2.8 350MHz FBGA
EM6A9320BI-3.0 333MHz FBGA
EM6A9320BI-3.3 300MHz FBGA
EM6A9320BI-3.5 285MHz
EM6A9320BI-4 250MHz FBGA
EM6A9320BI-5 200MHz

Frequency Power Supply Package

V

2.8V

DD

2.8V

V

DDQ

2.5V

V

DD

V

2.5V

DDQ

FBGA

FBGA

Etron Technology, Inc.

No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: [phone] FAX: [phone]

Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.

Etr onT ech

A

4Mx32 DDR SDRAM

EM6A9320

Pin Assignment (FBGA 144Ball Top View)

DQS0

A

B

DQ4

DM0

VDDQ

VSSQ

NC

DQ3

VDDQ

DQ2 DQ0

DQ1

VDDQ

DQ31 DQ29

VDDQ DQ30

DQ28 VSSQ

VDDQ

NC

12 11 10 9 8 7 6 5 4 3 2 1

DM3

VDDQ DQ27

DQS3

C

DQ6 DQ5

VSSQ VSSQ

VSSQ

VDD

VDD

VSSQ

VSSQ VSSQ

DQ26 DQ25

D

DQ7

VDDQ

VDD VSS

VSSQ

VSS

VSS

VSSQ

VSS VDD

VDDQ DQ24

E

DQ17 DQ16

VDDQ VSSQ

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSSQ VDDQ

DQ15 DQ14

F

DQ19 DQ18

VDDQ VSSQ

G

DQS2

DM2

NC

VSSQ

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSSQ VDDQ

VSSQ

NC

DQ13 DQ12

DM1

DQS1

H

DQ21 DQ20

VDDQ VSSQ

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSSQ VDDQ

DQ11 DQ10

J

DQ22 DQ23

VDDQ VSSQ

VSS VSS

VSS VSS

VSSQ VDDQ

DQ9 DQ8

K

CAS#

WE#

VDD VSS

A10 VDD

VDD NC

VSS VDD

NC NC

L

RAS#

NC

NC BA1

A2 A11

A9 A5

NC CK

CK# NC

M

CS# NC

BA0 A0

A1 A3

A4 A6

A7

AP

8/

CKE

VREF

Pin Assignment by Name (FBGA 144Ball)

Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location

A0 M4 DQ6 C1 DQ24 D12 CK L10 VDDQ B6 VSS E5 VSS J7 VSSQ G4
A1 M5 DQ7 D1 DQ25 C12 CK# L11 VDDQ B7 VSS E6 VSS J8 VSSQ G9
A2 L5 DQ8 J12 DQ26 C11 CKE M11 VDDQ B9 VSS E7 VSS K4 VSSQ H4
A3 M6 DQ9 J11 DQ27 B12 CS# M1 VDDQ B11 VSS E8 VSS K9 VSSQ H9
A4 M7 DQ10 H12 DQ28 A9 RAS# L1 VDDQ D2 VSS F5 VSSQ A3 VSSQ J4
A5 L8 DQ11 H11 DQ29 A8 CAS# K1 VDDQ D11 VSS F6 VSSQ A10 VSSQ J9
A6 M8 DQ12 F12 DQ30 B8 WE# K2 VDDQ E3 VSS F7 VSSQ C3 NC B3
A7 M9 DQ13 F11 DQ31 A7 VREF M12 VDDQ E10 VSS F8 VSSQ C4 NC B10

A8/AP M10 DQ14 E12 DQS0 A1 VDD C6 VDDQ F3 VSS G5 VSSQ C5 NC G3

A9 L7 DQ15 E11 DQS1 G12 VDD C7 VDDQ F10 VSS G6 VSSQ C8 NC G10
A10 K5 DQ16 E2 DQS2 G1 VDD D3 VDDQ H3 VSS G7 VSSQ C9 NC K8
A11 L6 DQ17 E1 DQS3 A12 VDD D10 VDDQ H10 VSS G8 VSSQ C10 NC K11

DQ0 A6 DQ18 F2 DM0 A2 VDD K3 VDDQ J3 VSS H5 VSSQ D5 NC K12
DQ1 B5 DQ19 F1 DM1 G11 VDD K6 VDDQ J10 VSS H6 VSSQ D8 NC L2
DQ2 A5 DQ20 H2 DM2 G2 VDD K7 VSS D4 VSS H7 VSSQ E4 NC L3
DQ3 A4 DQ21 H1 DM3 A11 VDD K10 VSS D6 VSS H8 VSSQ E9 NC L9
DQ4 B1 DQ22 J1 BA0 M3 VDDQ B2 VSS D7 VSS J5 VSSQ F4 NC L12
DQ5 C2 DQ23 J2 BA1 L4 VDDQ B4 VSS D9 VSS J6 VSSQ F9 NC M2

Etron Confidential

2 Rev 0.3 July. 2002

Etr onT ech

Block Diagram

4Mx32 DDR SDRAM

Column Decoder

4096 X 256 X 32

CELL ARRAY

Decoder
Row

Sense Amplifier

EM6A9320

(BANK #0)

CK
CK#

CKE

CS#
RAS#
CAS#

WE#

A8/AP

A0

A10
A11

BA0
BA1

DLL

CLOCK

BUFFER

COMMAND

DECODER

COLUMN

COUNTER

ADDRESS

BUFFER

SFGSFTI

DPVOUFS

CONTROL

SIGNAL

GENERATOR

MODE

REGISTER

Sense Amplifier

4096 X 256 X 32

CELL ARRAY

(BANK #1)

Row Decoder

Column Decoder

Column Decoder

4096 X 256 X 32

CELL ARRAY

(BANK #2)

Row Decoder

Sense Amplifier

DATA

DQ0

h

DQ31

STROBE

BUFFER

DQS0~3

Etron Confidential

Sense Amplifier

DQ

BUFFER

DM0~3

3 Rev 0.3 July. 2002

4096 X 256 X 32

CELL ARRAY

Decoder

(BANK #3)

Row

Column Decoder

Etr onT ech

4Mx32 DDR SDRAM

EM6A9320

Pin Descriptions

Symbol Type Description

CK, CK# Input

CKE Input

BA0, BA1 Input

A0-A11 Input

CS# Input

RAS# Input

CAS# Input

WE# Input

DQS0-DQS3 Input /

Output

DM0 - DM3 Input

DQ0 - DQ31 Input /

Output

V

DD

Supply

Table 1. Pin Details of EM6A9320

Differential Clock:

commands are sam pled on the positive edge of CK. Both CK and CK# increment the
internal burst counter and controls the output registers.

Clock Enable:

goes low synchronously with clock, the internal clock is suspended f r om the next clock
cycle and the state of output and burst address is fr ozen as long as the CKE rem ains
low. When all bank s are in the idle state, deactivating the clock controls the entry to
the Power Down and Self Refresh modes.

Bank Select:

BankPrecharge com mand is being applied. They also define which Mode Register or
Extended Mode Register is loaded during a Mode Register Set command.

Address Inputs:

address A0-A11) and Read/W rite comm and (column address A0-A7 with A8 defining
Auto Precharge) to select one location out of the 256K available in the respective
bank. During a Precharge command, A8 is sampled to deter mine if all banks ar e to be
precharged (A8 = HIGH). The addr ess inputs also pr ovide the op-code during a Mode
Register Set or Extended Mode Register Set command.

Chip Select:

command decoder. All commands are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks . It is considered
part of the command code.

Row Address Strobe:

conjunction with the CAS# and WE# signals and is latched at the positive edges of
CK. When RAS# and CS# are as serted "LOW" and CAS# is asserted "HIGH" either
the BankActivate command or the Precharge command is selected by the WE# signal.
When the W E# is asserted "HIGH," the BankActivate c ommand is selected and the
bank designated by BS is turned on to the active state. When the W E# is asserted
"LOW," the Precharge command is selected and the bank designated by BS is
switched to the idle state after the precharge operation.

Column Address Strobe:

conjunction with the RAS# and WE# signals and is latched at the positive edges of
CK. When RAS# is held "HIGH" and CS# is asserted "LOW" the colum n access is
started by asserting CAS# "LOW" Then, the Read or Write comm and is selected by
asserting WE# "HIGH " or “LOW".

Write Enable:

the RAS# and CAS# signals and is latched at the positive edges of CK. The WE#
input is used to select the BankActivate or Prechar ge command and Read or Write
command.

Bidirectional Data Strobe:

bytes: DQS0 to DQ0-DQ7, DQS1 to DQ8-DQ15, DQS2 to DQ16-DQ23, DQS3 to
DQ24-DQ31.

Data Input Mask:

sampled HIGH during a write cycle. DM3 masks DQ31-DQ24, DM2 masks DQ23­DQ16, DM1 masks DQ15-DQ8, and DM0 masks DQ7-DQ0.

Data I/O:

edges of CK and CK#. The I/Os are byte-maskable during Writes.

3RZHU 6XSSO\

The DQ0-DQ31 input and output data are synchronized with the positive

CK, CK# are driven by the system clock. All SDRAM input

CKE activates (HIGH) and deactivates (LOW ) the CK signal. If CKE

BA0 and BA1 defines to which bank the Bank Activate, Read, W rite, or

A0-A11 are sampled during the Bank Activate command (row

CS# enables (sampled LOW) and disables (sampled HIGH) the

The RAS# signal defines the operation commands in

The CAS# signal defines the operation commands in

The W E# signal defines the operation commands in c onjunction with

The DQSx signals are mapped to the following data

DM0-DM3 are byte specific. Input data is masked when DM is

3RZHU IRU WKH LQSXW EXIIHUV DQG FRUH ORJLF



Etron Confidential

4 Rev 0.3 July. 2002

Etr onT ech

V

SS

V

DDQ

V

SSQ

V

REF

NC -

Note: The timing reference point for the differential clocking is the cross point of the CK and CK#. For any
applications using the single ended clocking, apply V

Supply
Supply

Supply
Supply

Ground:
DQ Power:
DQ Ground:
Reference Voltage for Inputs:
No Connect:

Ground

Provide isolated power to DQs for improved noise immunity.

Provide isolated ground to DQs for improved noise immunity.

These pins should be left unconnected.

4Mx32 DDR SDRAM

IRU WKH LQSXW EXIIHUV DQG FRUH ORJLF

+0.5 x V

to CK# pin.

REF

DDQ



EM6A9320

Operation Mode

Fully synchronous operations are performed to latch the c ommands at the positive edges of CK . Table 2 shows
the truth table for the operation commands.

Table 2. Truth Table (Note (1), (2) )

Command State

BankActivate Idle
BankPrecharge Any H X X V V L X L L H L
PrechargeAll Any H X X X X H X L L H L
Write Active

Write and AutoPrecharge

Read Active
Read and Autoprecharge Active
Mode Register Set Idle H X X L L L L L L

Extended Mode Register Set

No-Operation Any H X X X X X X L H H H
Device Deselect Any H X X X X X X H X X X
Burst Stop Active
AutoRefresh Idle H H X X X X X L L L H
SelfRefresh Entry Idle H L X X X X X L L L H

SelfRefresh Exit

Power Down Mode Entry Idle/Active

Power Down Mode Exit
Data Write/

Data Mask/

Note:

Output Enable
Output Disable

1. V = Valid data, X = Don't Care, L = Low level, H = High level

2. CKE

3. These are states of bank designated by BA0, BA1signals.

4. Read burst stop with BST command for all burst types.

5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.

signal is input level when commands are provided.

n

CKE

signal is input level one clock cycle before the commands are provided.

n-1

Active

Idle H X X L H

Idle

(Self Refresh)

Any

(Power Down)

Active H X L X X X X X X X X
Active H X H X X X X X X X X

CKEn-1 CKEn DM BA1 BA0 A8 A11-A9, A7-0 CS# RAS# CAS# WE#

(3)

H X X V V Row Address L L H H

(3)

H X V V V L L H L L

(3)

H X V V V H L H L L

(3)

H X X V V L L H L H

(3)

H X X V V H

(4)

H X X X X X X L H H L

L H X X X X X

(5)

H L X X X X X

L H X X X X X

Column

Address

A0~A7

OP code

L H L H

L L L L

H X X X

L H H H

H X X X

L H H H

H X X X

L H H H

Etron Confidential

5 Rev 0.3 July. 2002