ETRON EM639165TS-75, EM639165TS-8L, EM639165TS-8, EM639165TS-75L Datasheet
EtronTech
EM639165
8Mega x 16bits SDRAM
Preliminary (Rev 1.0, 2/2001)
Features
•
Single 3.3 ± 0.3V power supply
•
Fast clock rate
-
PC133: 133 MHz (CL3)
-
PC100: 100 MHz (CL2)
•
Fully synchronous operation referenced to clock
rising edge
•
4-bank operation controlled by BA0, BA1 (Bank
Address)
•
Programmable Mode registers
- /CAS Latency: 2 or 3
- Burst Length: 1, 2, 4, 8 or full page
- Burst Type: interleaved or linear burst
•
Byte Control – DQML and DQMU
•
Random column access
•
Auto precharge / All banks precharge controlled
by A10
•
Auto and self-refresh
•
Self-refresh mode: standard and low power
•
4096 refresh cycles/64ms
•
Interface: LVTTL
•
54-pin 400 mil plastic TSOP II package
Pin Assignment (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
DQML
/WE
/CAS
/RAS
/CS
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Ordering Information
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
Key Specifications
EM639165
Clock Cycle time (min., CL=2)
t
CK2
Clock Cycle time (min., CL=3)
t
CK3
Access time (max., CL=2)
t
AC2
Access time (max., CL=3)
t
AC3
Row Active time (max.)
t
RAS
Row Cycle time(min.)
t
RC
-
75/8
10/10 ns
7.5/8 ns
6/6 ns
5.4/6 ns
45/48 ns
67.5/70 ns
Overview
EM639165 is a high-speed Synchronous Dynamic
Random Access Memory (SDRAM), organized as 4
banks x 2,097,152 words x 16 bits. All inputs and
outputs are referenced to the rising edge of CLK.
It achieves very high-speed data rates up to
133MHz, and is suitable for main memories or graphic
memories in computer systems. For handheld device
application, we also provide a low power option, with
self-refresh current under 800 µA.
Part Number Speed
Grade
Self refresh
current (Max.)
EM639165TS-75 PC133/CL3 2 mA
EM639165TS-75L PC133/CL3
800 µA
EM639165TS-8 PC100/CL2 2 mA
EM639165TS-8L PC100/CL2
800 µA
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
BLOCK DIAGRAM
EM639165
DQ0-15
I/O Buffer
Memory Array
4096 x512x16
Cell Array
Bank #0
Mode
Register
Address Buffer
A0-11
BA0,1
Memory Array
4096 x512x16
Cell Array
Bank #1
Control Circuitry
Clock Buffer
CLK CKE
Memory Array
4096 x512x16
Cell Array
Bank #2
Control Signal Buffer
/CS /RAS
/CAS
Memory Array
4096 x512x16
Cell Array
Bank #3
/WE
DQM
Preliminary Rev 1.0 Feb. 2001
2
PIN FUNCTION
EM639165
CLK Input
CKE Input
/CS Input
/RAS, /CAS, /WE Input
A0-11 Input
BA0,1 Input
Master Clock:
All other inputs are referenced to the rising edge of CLK
Clock Enable:
CKE controls internal clock.When CKE is low, internal clock for
the following cycle is ceased. CKE is also used to select
auto / self-refresh.
After self-refresh mode is started, CKE becomes asynchronous input.
Self-refresh is maintained as long as CKE is low.
Chip Select:
When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11.
The Column Address is specified byA0-8.
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE , READ , WRITE commands.
DQ0-15
DQMU/L
VDD,VSS
Input / Output
Input
Power Supply
VDDQ,VSSQ Power Supply
Data In and Data out are referenced to the rising edge of CLK.
Din Mask / Output Disable:
When DQM(U/L) is high in burst write, Din for the current cycle is
masked. When DQM(U/L) is high in burst read,
Dout is disabled at the next but one cycle.
Power Supply for the memory array and peripheral circuitry.
VDDQ and VSSQ are supplied to the Output Buffers only.
Preliminary Rev 1.0 Feb. 2001
3
BASIC FUNCTIONS
The EM639165 provides basic functions, bank (row)
activate, burst read / write, bank (row) precharge, and auto
/ self refresh.
Each command is defined by control signals of /RAS, /CAS
and /WE at CLK rising edge. In addition to 3 signals, /CS
CLK
/CS Chip Select : L=select, H=deselect
/RAS Command
/CAS
/WE Command
CKE Refresh Option @ refresh command
A10 Precharge Option @ precharge or read/write command
Command
EM639165
,CKE and A10 are used as chip select, refresh opt ion, and
precharge option, respectively .
To know the detailed definition of commands, please see
the command truth table.
define basic command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output
data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge, READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, all banks
are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally . After this command, the banks are precharged automatically.
Preliminary Rev 1.0 Feb. 2001
4
COMMAND TRUTH T ABLE
COMMAND
MNEMONIC
CKE
n-1
CKE
n
EM639165
/CS /RAS /CAS /WE BA0,1 A1 1 A10 A0-9
Deselect
No Operation
Row Address Entry &
Bank Active
Single Bank Precharge
Precharge All Banks
Column Address Entry
Column Address Entry &
Write with Auto-Precharge
Column Address Entry
Column Address Entry &
Read with Auto-Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
&Write
& Read
DESEL HXHXXXX XXX
NOP HXLHHHXXXX
ACT
PRE
PREA
WRITE
WRITE A
READ
READA
REFA
REFS
REFSX
HXLL HHVVVV
HXLLHLVXLX
HXLLHL XHX
HXLHLLVVLV
HXLHLL VVHV
HXLHLHVVLV
HXLHLHVVHV
HHL L LHX XXX
HLL L LHX XXX
L HHXXXX XXX
L HLHHHX XXX
X
Burst Terminate
Mode Register Set
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE: 1. A7-A9 =0, A0-A6 =Mode Address
Preliminary Rev 1.0 Feb. 2001
TBST HX L HHL XX XX
MRS
H X L L L L L L L V*1
5
FUNCTION TRUTH T ABLE
Current State /CS /RAS /CAS /WE Address Command Action
EM639165
IDLE
ROW
ACTIVE
HXXXX DESEL NOP
L H H H X NOP NOP
L H H L TBST ILLEGAL*2
L H L X BA, CA, A10
L L H H BA, RA ACT Bank Active, Latch RA
L L H L BA, A10
L L L H X REFA Auto-Refresh*5
LLLL
HXXXX DESEL NOP
L H H H X NOP NOP
L H H L TBST NOP
BA
Op-Code,
Mode-Add
BA
READ /
WRITE
PRE /
PREA
MRS Mode Register Set*5
ILLEGAL*2
NOP*4
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
Op-Code,
Mode-Add
READ /
READA
WRITE /
WRITEA
PRE /
PREA
MRS ILLEGAL
Begin Read, Latch CA, Determine
Auto-Precharge
Begin Write, Latch CA, Determine
Auto-Precharge
Precharge / Precharge All
Preliminary Rev 1.0 Feb. 2001
6
FUNCTION TRUTH T ABLE (continued)
EM639165
Current State /CS /RAS /CAS /WE Address
READ
WRITE
H X X X X DESEL
LHHHX NOP
L H H L TBST
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
H X X X X DESEL
L H H H X NO P NOP (Continue Burst to END)
BA
Op-Code,
Mode-Add
Command
READ
/READA
WRITE /
WRITEA
PRE /
PREA
MRS ILLEGAL
Action
NOP (Continue Burst to END)
NOP (Continue Burst to END)
Terminate Burst
Terminate Burst, Latch CA,Begin
Read, Determine Auto-Precharge*3
Terminate Burst, Latch CA,Begin
Write, Determine Auto-Precharge*3
Bank Active / ILLEGAL*2
Terminate Burst, Precharge
NOP (Continue Burst to END)
L H H L TBST
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L MRS ILLEGAL
BA
READ /
READA
WRITE /
WRITEA
PRE /
PREA
Op-Code,
Mode-Add
Terminate Burst, Latch CA,Begin
Terminate Burst, Latch CA,Begin
Read, Determine Auto-Precharge*3
Terminate Burst, Latch CA,Begin
Write, Determine Auto-Precharge*3
Terminate Burst, Precharge
Preliminary Rev 1.0 Feb. 2001
7
FUNCTION TRUTH T ABLE (continued)
Current State /CS /R AS /C AS /WE Address Command Action
EM639165
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
H X X X X DESEL
LHHHX NOP
L H H L TBST ILLEGAL
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
H X X X X DESEL
L H H H X NOP NOP (Continue Burst to END)
BA
Op-Code,
Mode-Add
READ /
READA
WRITE /
WRITE A
PRE /
PREA
MRS ILLEGAL
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
ILLEGAL
Bank Active / ILLEGAL*2
ILLEGAL*2
NOP (Continue Burst to END)
L H H L TBST ILLEGAL
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
BA
Op-Code,
Mode-Add
READ /
READA
WRITE /
WRITEA
PRE /
PREA
MRS
ILLEGAL
ILLEGAL
Bank Active / ILLEGAL*2
ILLEGAL*2
ILLEGAL
Preliminary Rev 1.0 Feb. 2001
8
FUNCTION TRUTH T ABLE (continued)
Current State /CS /RAS /C AS /WE Address Command Action
EM639165
PRE -
CHARGING
ROW
ACTIVATING
H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L TBST ILLEGAL*2
L H L X BA, CA, A10
L L H H BA, RA ACT ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
H X X X X DESEL NOP (Row Active after tRCD)
L H H H X NOP NOP (Row Active after tRCD)
L H H L TBST ILLEGAL*2
BA
Op-Code,
Mode-Add
BA
READ /
WRITE
PRE /
PREA
MRS ILLEGAL
ILLEGAL*2
NOP*4 (Idle after tRP)
L H L X BA, CA, A10
L L H H BA, RA ACT
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
Op-Code,
Mode-Add
READ /
WRITE
PRE /
PREA
MRS ILLEGAL
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
Preliminary Rev 1.0 Feb. 2001
9
FUNCTION TRUTH T ABLE (continued)
Current State /CS /RAS /C AS /WE Address Command Action
EM639165
WRITE
RECOVERING
REFRESHING
HXXX
LHHH
LHHL
LHLX
LLHH
LLHL
L L L H X REFA ILLEGAL
LLLL
H X X X X DESEL NOP (Idle after tRC)
L H H H X NOP NOP (Idle after tRC)
L H H L TBST ILLEGAL
X
X NOP NOP
BA
BA, CA, A10
BA, RA ACT
BA, A10
Op-Code,
Mode-Add
BA
DESEL
TBST
READ /
WRITE
PRE /
PREA
MRS
NOP
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL
L H L X BA, CA, A10
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
Op-Code,
Mode-Add
READ /
WRITE
PRE /
PREA
MRS ILLEGAL
ILLEGAL
ILLEGAL
Preliminary Rev 1.0 Feb. 2001
10
FUNCTION TRUTH T ABLE (continued)
Current State /CS /RAS /CAS /WE Address Command Action
EM639165
MODE
REGISTER
SETTING
H X X X X DESEL NOP (Idle after tRSC)
L H H H X NOP NOP (Idle after tRSC)
L H H L TBST ILLEGAL
L H L X BA, CA, A10
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
BA
Op-Code,
Mode-Add
READ /
WRITE
PRE /
PREA
MRS ILLEGAL
ILLEGAL
ILLEGAL
Preliminary Rev 1.0 Feb. 2001
11
FUNCTION TRUTH T ABLE for CKE
EM639165
Current State
SELF-
REFRESH*1
POWER
DOWN
ALL BANKS
IDLE*2
CKE
CKE
n-1
H X X X X X X INVALID
L H H X X X X Exit Self-Refresh (Idle after tRC)
LHLHHHX
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP (Maintain Self-Refresh)
HXXXXXX
L H X X X X X Exit Power Down to Idle
L L X X X X X NOP (Maintain Power Down)
H H X X X X X Refer to Function Truth Table
H L L L L H X Enter Self-Refresh
H L H X X X X Enter Power Down
H L L H H H X Enter Power Down
/CS /RAS /CAS /WE Add Action
n
Exit Self-Refresh (Idle after tRC)
INVALID
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L X X X ILLEGAL
L X X X X X X Refer to Current State =Power Down
ANY STATE
other than
listed above
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum
setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
H H X X X X X Refer to Function Truth Table
H L X X X X X Begin CLK Susspend at Next Cycle*3
LHXXXXX
L L X X X X X Maintain CLK Suspend
Exit CLK Susspend at Next Cycle*3
Preliminary Rev 1.0 Feb. 2001
12
EM639165
POWER ON SEQUENCE
Before starting normal operation, the following power on
sequence is necessary to prevent a SDRAM from damaged
or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE
high, DQM high and NOP condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or
more auto-refresh commands.
5. Issue a mode register set command to initialize the mode
register.
After these sequence, the SDRAM is idle state and ready
for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode
register stores these data until the next MRS command,
which may be issued when all banks are in idle state. After
tRSC from a MRS command, the SDRAM is ready for new
command.
CLK
/CS
/RAS
/CAS
/WE
BA0,1 A11-A0
V
LATENCY
MODE
A11 A1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0 0 0 0 LTMODE BT BL00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
/CAS LATENCY
R: Reserved for Future Use
FP: Full Page
BL
0 0 0
0 0 1
R
R
2
3
R
R
R
R
BURST
LENGTH
BURST
TYPE
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
BT= 0 BT= 1
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
1
2
4
8
R
R
R
R
Preliminary Rev 1.0 Feb. 2001
13
CLK
EM639165
Command
Address
DQ
Initial Address
A2 A1 A0
00 0
00 1
01 0
01 1
10 0
CL= 3
BL= 4
BL
8
Read
Y
Q0 Q1 Q2 Q3
/CAS Latency Burst Length Burst Length
Burst Type
Column Addressing
Sequential Interleaved
0123456701234567
1234567010325476
2345670123016745
3456701232107654
4567012345670123
Write
Y
D0 D1 D2 D3
10 1
11 0
11 1
-00
-01
-10
-11
--0
--1
5670123454761032
6701234567452301
7012
0123
1230
4
2301
30
01
2
10
3456 3210
12
7654
0123
1032
2301
32
01
10
10
Preliminary Rev 1.0 Feb. 2001
14
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by
the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A0-11. The minimum activation interval
between one bank and the other bank is tRRD. Maximum 2 ACT
commands are allowed within tRC , although the number of banks
which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When
multiple banks are active, the precharge all command (PREA, PRE
+ A10=H) is available to deactivate them at the same time.
After tRP from the precharge, an ACT command to the same bank
can be issued.
READ
After tRCD from the bank activation, a READ command can be
issued. 1st output data is available after the /CAS Latency from the
READ, followed by (BL -1) consecutive data when the Burst Length
is BL. The start address is specified by A0-A9,A11(x4), A0-9(X8),
A0-8(X16) , and the address sequence of burst data is defined by
the Burst Type. A READ command may be applied to any active
bank, so the row precharge time (tRP) can be hidden behind
continuous output data by interleaving the multiple banks. When
A10 is high at a READ command, the auto-precharge (READA) is
performed. Any command (READ, WRITE, PRE, TBST, ACT) to
the same bank is inhibited till the internal precharge is complete.
The internal precharge starts at BL after READA. (Need to keep
tRAS min.) The next ACT command can be issued after (BL +
tRP) from the previous READA.
Bank Activation and Precharge All (BL=4, CL=3)
EM639165
CLK
Command
A0-9
A10
A11
BA0,1
DQ
2 ACT command / tRCmin
ACT
tRRD
Xa
tRCD
Xa
Xa Xb Xb
00
ACT
Xb
Xb
01
READ
Y
0
00
tRCmin
tRAS
PRE
tRP
1
Qa0 Qa1 Qa2 Qa3
Precharge all
ACT
Xb
Xb
01
Preliminary Rev 1.0 Feb. 2001
15
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