ETRON EM636327Q-8, EM636327Q-6, EM636327Q-55, EM636327Q-10, EM636327JT-8 Datasheet

EtronTech

EM636327

512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)

Preliminary (12/98)

Features

•

Fast access time from clock: 5/5/5.5/6.5/7.5 ns

•

Fast clock rate: 183/166/143/125/100 MHz

•

Fully synchronous operation

•

Internal pipelined architecture

•

Dual internal banks(256K x 32-bit x 2-bank)

•

Programmable Mode and Special Mode registers

- CAS# Latency: 1, 2, or 3

- Burst Length: 1, 2, 4, 8, or full page

- Burst Type: interleaved or linear burst

- Burst-Read-Single-Write

- Load Color or Mask register

•

Burst stop function

•

Individual byte controlled by DQM0-3

•

Block write and write-per-bit capability

•

Auto Refresh and Self Refresh

•

2048 refresh cycles/32ms

•

Single +3.3V±0.3V power supply

•

Interface: LVTTL

•

JEDEC 100-pin Plastic package

-QFP (body thickness=2.8mm)

-TQFP1.4 (body thickness=1.4mm)

-TQFP1.0 (body thickness=1.0mm)

Overview

The EM636327 SGRAM is a high-speed
CMOS synchronous graphics DRAM containing 16
Mbits. It is internally configured as a dual 256K x
32 DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock
signal, CLK). Each of the 256K x 32 bit banks is
organized as 1024 rows by 256 columns by 32 bits.
Read and write accesses to the SGRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in
a programmed sequence. Accesses begin with the
registration of a BankActivate command which is
then followed by a Read or Write command.

The EM636327 provides for programmable
Read or Write burst lengths of 1, 2, 4, 8, or full

Key Specifications

EM636327 - 55/6/7/8/10

Clock Cycle time(min.) 5.5/6/7/8/10 ns

t

CK3

Row Active time(max.) 32/36/42/48/60 ns

t

RAS

Access time from Read command 7/8/13/18/23 ns

t

AC1

Access time from CLK(max.) 5/5/5.5/6.5/7.5 ns

t

AC3

Row Cycle time(min.) 48/54/63/72/90 ns

t

RC

Ordering Information

Part Number Frequency Package

EM636327Q-10 100MHz QFP
EM636327R-10 100MHz QFP (Reverse)
EM636327TQ-10 100MHz TQFP1.4
EM636327JT-10 100MHz TQFP1.0
EM636327Q-8 125MHz QFP
EM636327R-8 125MHz QFP (Reverse)
EM636327TQ-8 125MHz TQFP1.4
EM636327JT-8 125MHz TQFP1.0
EM636327Q-7 143MHz QFP
EM636327TQ-7 143MHz TQFP1.4
EM636327Q-6 166MHz QFP
EM636327TQ-6 166MHz TQFP1.4
EM636327Q-55 183MHz QFP
EM636327TQ-55 183MHz TQFP1.4

page, with a burst termination option. An auto
precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end
of the burst sequence. The refresh functions,
either Auto or Self Refresh are easy to use. In
addition, EM636327 features the write-per-bit and
the masked block write functions.

By having a programmable mode register and
special mode register, the system can choose the
most suitable modes to maximize its performance.
These devices are well suited for applications
requiring high memory bandwidth, and when
combined with special graphics functions result in
a device particularly well suited to high
performance graphics applications.

Etron Technology, Inc.

1F, No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C
TEL: [phone] FAX: [phone]

Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.

EtronTech

Block Diagram

EM636327Q-xx

EM636327

CLK

CKE

CS#
RAS#

CAS#
WE#

DSF

A9

A0

A8
BS

CLOCK

BUFFER

COMMAND

DECODER

COLUMN

COUNTER

ADDRESS

BUFFER

REFRESH

COUNTER

CONTROL

SIGNAL

GENERATOR

MODE

REGISTER

SPECIA L

MODE

REGIS TER

Row Decoder

COLOR

REGISTE R

MAS K

REGISTE R

Row Decoder

Column Decoder

1024 X 256 X 32

CELL ARRAY

(BANK #0)

Sense Amplifier

Sense Amplifier

1024 X 256 X 32

CELL ARRAY

(BANK #1)

Column Decoder

DQS

BUFFER

DQM0~3

DQ0

¢x

DQ31

DQ3

V

DDQ

DQ4
DQ5

VSSQ

DQ6
DQ7

VDDQ
DQ16
DQ17

VSSQ
DQ18
DQ19

V

DDQ

V

DD

V
DQ20
DQ21

V

SSQ

DQ22
DQ23

VDDQ
DQM0
DQM2

WE#
CAS#
RAS#

CS#

BS
A8

Pin Assignment (Top View)

Forward Type Reverse Type

VSSQ

DQ0

DQ1

DQ2

VDD

NC

100

1
2
3
4
5
6
7
8
9
10
1 1
12
13
14
15
16

SS

17
18
19
20
21
22
23
24
25
26
27
28
29

31

30

A0

NCNCNCNCNCNCNCNCNC

NCNCNCNCNCNCNCNCNCNCVDDA3A2A1

DQ29

DQ30

DQ31

VSSQ

VSS

81828384858687888990919293949596979899

80

DQ28

79

V

DDQ

78

DQ27

77

DQ26

76

V

SSQ

75

DQ25

74

DQ24

73

VDDQ

72

DQ15

71

DQ14

70

VSSQ

69

DQ13

68

DQ12

67

VDDQ

66

VSS

65

V

DD

64

DQ11

63

DQ10

62

V

SSQ

61

DQ9

60

DQ8

59

V

DDQ

58

NC

57

DQM3

56

DQM1

55

CLK

54

CKE

53

DSF

52

NC

50494847464544434241403938373635343332

51

A9

A7A6A5A4VSS

DQ28

VDDQ
DQ27
DQ26

VSSQ
DQ25
DQ24

VDDQ
DQ15
DQ14

VSSQ
DQ13
DQ12

V

DDQ

V

V

DD

DQ11
DQ10

V

SSQ

DQ9
DQ8

VDDQ

NC
DQM3
DQM1

CLK

CKE

DSF

NC

A9

SS

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DQ31

DQ30

DQ29

VSSQ

VSS

NC

81

EM636327R-xx

50

A4A5A6

A7

VSSQ

DQ2

DQ1

DQ0

VDD

NCNCNCNCNCNCNCNCNC

100999897969594939291908988878685848382

1

DQ3

2

V

DDQ

3

DQ4

4

DQ5

5

VSSQ

6

DQ6

7

DQ7

8

VDDQ

9

DQ16

10

DQ17

11

VSSQ

12

DQ18

13

DQ19

14

VDDQ

15

VDD

16

V

SS

17

DQ20

18

DQ21

19

V

SSQ

20

DQ22

21

DQ23

22

V

DDQ

23

DQM0

24

DQM2

25

WE#

26

CAS#

27

RAS#

28

CS#

29

BS

31323334353637383940414243444546474849

30

A8

A0A1A2A3VDDNCNCNCNCNCNCNCNCNCNCVSS

Preliminary

2 December

1998

EtronTech

Pin Descriptions

Table 1 shows the details for pin number, symbol, type, and description.

Table 1. Pin Details of EM636327

Pin Number Symbol Type Description

EM636327

55 CLK Input

54 CKE Input

29 BS Input

31-34,
47-50,
30, 51

A0-A9 Input

Clock:

sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.

Clock Enable:

If CKE goes low synchronously with clock(set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the
state of output and burst address is frozen as long as the CKE remains low.
When both banks are in the idle state, deactivating the clock controls the
entry to the Power Down and Self Refresh modes. CKE is synchronous
except after the device enters Power Down and Self Refresh modes, where
CKE becomes asynchronous until exiting the same mode. The input buffers,
including CLK, are disabled during Power Down and Self Refresh modes,
providing low standby power.

Bank Select:

BankPrecharge command is being applied. BS is also used to program the
10th bit of the Mode and Special Mode registers.

Address Inputs:

address A0-A9) and Read/Write command (column address A0-A7 with A9
defining Auto Precharge) to select one location out of the 256K available in
the respective bank. During a Precharge command, A9 is sampled to
determine if both banks are to be precharged (A9 = HIGH). The address
inputs also provide the op-code during a Mode Register Set or Special Mode
Register Set command.

CLK is driven by the system clock. All SGRAM input signals are

CKE activates(HIGH) and deactivates(LOW) the CLK signal.

BS defines to which bank the BankActivate, Read, Write, or

A0-A9 are sampled during the BankActivate command (row

28 CS# Input

27 RAS# Input

26 CAS# Input

25 WE# Input

Chip Select:

command decoder. All commands are masked when CS# is sampled HIGH.
CS# provides for external bank selection on systems with multiple banks. It is
considered part of the command code.

Row Address Strobe:

conjunction with the CAS# and WE# signals and is latched at the positive
edges of CLK. When RAS# and CS# are asserted "LOW" and CAS# is
asserted "HIGH," either the BankActivate command or the Precharge
command is selected by the WE# signal. When the WE# is asserted "HIGH,"
the BankActivate command is selected and the bank designated by BS is
turned on to the active state. When the WE# is asserted "LOW," the
Precharge command is selected and the bank designated by BS is switched
to the idle state after the precharge operation.

Column Address Strobe:

in conjunction with the RAS# and WE# signals and is latched at the positive
edges of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the
column access is started by asserting CAS# "LOW." Then, the Read or Write
command is selected by asserting WE# "LOW" or "HIGH."

Write Enable:

conjunction with the RAS# and CAS# signals and is latched at the positive
edges of CLK. The WE# input is used to select the BankActivate or
Precharge command and Read or Write command.

CS# enables (sampled LOW) and disables (sampled HIGH) the

The RAS# signal defines the operation commands in

The CAS# signal defines the operation commands

The WE# signal defines the operation commands in

Preliminary

3 December

1998

EtronTech

EM636327

53 DSF Input

23, 56, 24,57DQM0 -

DQM3

97, 98, 100,

1, 3, 4, 6 , 7,

60, 61, 63,
64, 68, 69,

71, 72, 9,
10, 12, 13,
17, 18, 20,
21, 74, 75,
77, 78, 80,

81, 83, 84
36-45, 52,

58, 86-95

DQ0-

DQ31

NC -

Input

Input/
Output

Define Special Function:

in conjunction with the RAS# and CAS# and WE# signals and is latched at
the positive edges of CLK. The DSF input is used to select the masked write
disable/enable command and block write command, and the Special Mode
Register Set cycle.

Data Input/Output Mask:

buffer controls. The I/O buffers are placed in a high-z state when DQM is
sampled HIGH. Input data is masked when DQM is sampled HIGH during a
write cycle. Output data is masked (two-clock latency) when DQM is sampled
HIGH during a read cycle. DQM3 masks DQ31-DQ24, DQM2 masks DQ23­DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0.

Data I/O:

positive edges of CLK. The I/Os are byte-maskable during Reads and Writes.
The DQs also serve as column/byte mask inputs during Block Writes.

No Connect:

The DQ0-31 input and output data are synchronized with the

These pins should be left unconnected.

The DSF signal defines the operation commands

DQM0-DQM3 are byte specific, nonpersistent I/O

2, 8, 14, 22,

59, 67, 73,

79

5, 11, 19,
62, 70, 76,

82, 99

15, 35, 65,96V

16, 46, 66,85V

V

V

DDQ

SSQ

DD

SS

Supply

Supply

Supply

Supply

DQ Power:

DQ Ground:

Power Supply:

Ground

Provide isolated power to DQs for improved noise immunity.

Provide isolated ground to DQs for improved noise immunity.

+3.3V±0.3V

Preliminary

4 December

1998

EtronTech

EM636327

Operation Mode

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.

Table 2 shows the truth table for the operation commands.

Table 2. Truth Table (Note (1), (2) )

Command State CKE

BankActivate & Masked Write Disable
BankActivate & Masked Write Enable
BankPrecharge
PrechargeAll
Write
Block Write Command
Write and AutoPrecharge
Block Write and AutoPrecharge
Read
Read and Autoprecharge
Mode Register Set
Special Mode Register Set
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit

Clock Suspend Mode Entry
Power Down Mode Entry

Clock Suspend Mode Exit
Power Down Mode Exit

Data Write/Output Enable
Data Mask/Output Disable

Note:

1. V=Valid X=Don't Care L=Low level H=High level

2. CKEn signal is input level when commands are provided.
CKE

signal is input level one clock cycle before the commands are provided.

n-1

3. These are states of bank designated by BS signal.

4. Device state is 1, 2, 4, 8, and full page burst operation.

5. The Special Mode Register Set is also available in Row Active State.

6. Power Down Mode can not enter in the burst operation.

When this command is asserted in the burst cycle, device state is clock suspend mode.

7. DQM0-3

(7)

BS A9A

CS# RAS# CAS# WE# DSF

0-8

Idle
Idle

(3)
(3)

CKEnDQM

n-1

H X X V V V L L H H L

H X X V V V L L H H H
Any H X X V L X L L H L L
Any H X X X H X L L H L L

(3)

Active
Active
Active
Active
Active
Active

H X X V L V L H L L L

(3)

H X X V L V L H L L H

(3)

H X X V H V L H L L L

(3)

H X X V H V L H L L H

(3)

H X X V L V L H L H L

(3)

H X X V H V L H L H L
Idle H X X V L V L L L L L

(5)

Idle

H X X X X V L L L L H
Any H X X X X X L H H H X

(4)

Active

H X X X X X L H H L L
Any H X X X X X H X X X X
Idle H H X X X X L L L H L
Idle H L X X X X L L L H L
Idle L H X X X X H X X X X

(SelfRefresh)

L H H H X

Active H L X X X X X X X X X

(6)

Any

H L X X X X H X X X X

L H H H L

Active L H X X X X X X X X X

Any L H X X X X H X X X X

(PowerDown)

L H H H L
Active H X L X X X X X X X X
Active H X H X X X X X X X X

Preliminary

5 December

1998

EtronTech

Commands

1 BankActivate & Masked Write Disable command

(RAS# = "L", CAS# = "H", WE# = "H", DSF = "L", BS = Bank, A0-A9 = Row Address)

The BankActivate command activates the idle bank designated by the BS (Bank Select) signal.
By latching the row address on A0 to A9 at the time of this command, the selected row access is
initiated. The read or write operation in the same bank can occur after a time delay of t
from the time of bank activation. A subsequent BankActivate command to a different row in the
same bank can only be issued after the previous active row has been precharged (refer to the
following figure). The minimum time interval between successive BankActivate commands to the
same bank is defined by tRC(min.). The SGRAM has two internal banks on the same chip and
shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back
activation of both banks. t
different banks. After this command is used, the Write command and the Block Write command
perform the no mask write operation.

T0 T 1 T2 T3 Tn+ 3 Tn+4 Tn+5 Tn+ 6

(min.) specifies the minimum time required between activating

RRD

EM636327

(min.)

RCD

CLK

ADDRESS

COM MA ND

Bank A

Row Addr.

Bank A

Activate

RAS# - CAS# delay (

NOP

t

NOP

RCD)

Bank A

Col Addr.

R/W A with

AutoPrecharge

RAS# Cycle time (

..............

..............

..............

Bank B

Row Addr.

Bank B

Activate

t

RC)

AutoPrecharge

Begin

RAS# - RAS# delay time (

NOP

NOP

t

RRD)

: "H" or "L"

BankActivate Command Cycle

(Burst Length = n, CAS# Latency = 3)

2 BankActivate & Masked Write Enable command (refer to the above figure)

(RAS# = "L", CAS# = "H", WE# = "H", DSF = "H", BS = Bank, A0-A9 = Row Address)

The BankActivate command activates the idle bank designated by BS signal. After this
command is performed, the Write command and the Block Write command perform the masked
write operation. In the masked write and the masked block write functions, the I/O mask data that
was stored in the write mask register is used.

3 BankPrecharge command

(RAS# = "L", CAS# = "H", WE# = "L", DSF = "L", BS = Bank, A9 = "L", A0-A8 = Don't care)

The BankPrecharge command precharges the bank disignated by BS signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
t

(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any

RAS

bank can be active is specified by t
in any active bank within t

(max.). At the end of precharge, the precharged bank is still in the idle

RAS

(max.). Therefore, the precharge function must be performed

RAS

state and is ready to be activated again.

Bank A

Row Addr.

Bank A

Activate

4 PrechargeAll command

(RAS# = "L", CAS# = "H", WE# = "L", DSF = "L", BS = Don't care, A9 = "H", A0-A8 = Don't care)

The PrechargeAll command precharges both banks simultaneously and can be issued even if
both banks are not in the active state. Both banks are then switched to the idle state.

5 Read command

(RAS# = "H", CAS# = "L", WE# = "H", DSF = "L", BS = Bank, A9 = "L", A0-A7 = Column Address)

The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least t
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS# latency after the issue of the Read command. Each subsequent data­out element will be valid by the next positive clock edge (refer to the following figure). The DQs go

Preliminary

(min.) before the Read command is

RCD

6 December

1998

EtronTech

EM636327

into high-impedance at the end of the burst unless other command is initiated. The burst length,
burst sequence, and CAS# latency are determined by the mode register, which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).

T0 T 1 T2 T3 T4 T5 T6 T 7 T8

CLK

COM MA ND

CAS# latency=1
t

, DQ's

CK1

CAS# latency=2
t

, DQ's

CK2

CAS# latency=3
t

, DQ's

CK3

READ A NOP

DOUT A0DOUT A

NOP NOP NOP NOP NOP NOP NOP

DOUT A0DOUT A

Burst Read Operation

DOUT A2DOUT A

1

1

DOUT A0DOUT A

3

DOUT A2DOUT A

DOUT A2DOUT A

1

3

(Burst Length = 4, CAS# Latency = 1, 2, 3)

3

The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier
(i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function
may be interrupted by a subsequent Read or Write/Block Write command to the same bank or the
other active bank before the end of the burst length. It may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank too. The interrupt coming from the Read command can
occur on any clock cycle following a previous Read command (refer to the following figure).

T0 T 1 T2 T3 T4 T5 T6 T7 T8

CLK

COM MA ND

READ A READ B NOP NOP NOP NOP N O P NOP NOP

CAS# latency=1
t

, DQ's

CK1

CAS# latency=2
t

, DQ's

CK2

CAS# latency=3
t

, DQ's

CK3

Read Interrupted by a Read

DOUT A0DOUT B

DOUT A0DOUT B

DOUT B1DOUT B

0

DOUT A0DOUT B

(Burst Length = 4, CAS# Latency = 1, 2, 3)

DOUT B1DOUT B

0

DOUT B

2

DOUT B1DOUT B

0

3

DOUT B

2

3

DOUT B

2

3

The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes
from a Write/Block Write command. The DQMs must be asserted (HIGH) at least two clocks prior to
the Write/Block Write command to suppress data-out on the DQ pins. To guarantee the DQ pins
against I/O contention, a single cycle with high-impedance on the DQ pins must occur between the
last read data and the Write/Block Write command (refer to the following three figures). If the data
output of the burst read occurs at the second clock of the burst write, the DQMs must be asserted
(HIGH) at least one clock prior to the Write/Block Write command to avoid internal bus contention.

Preliminary

7 December

1998

EtronTech

CLK

DQM

EM636327

T0 T 1 T2 T3 T4 T5 T6 T 7 T8

COM MA ND

DQ's

: "H" or "L"

CLK

DQM

COM MA ND

CAS# latency=1
t

, DQ's

CK1

CAS# latency=2
t

, DQ's

CK2

: "H" or "L"

NO P

Read to Write Interval

T0 T 1 T2 T3 T4 T5 T6 T7 T8

NOP NOP NOP READ A WRITE A NOP NOP NO P

READ A NOP NOP NOP NOP WRITE B NOP NO P

DOUT A

BANKA

ACTIVATE

(Burst Length

1 Clk Interval

Must be Hi-Z before
the Write Command

0

Must be Hi-Z before
the Write Command

¡Ù

4, CAS# Latency = 3)

DIN A

DIN A

DINB

DIN A

0

0

DIN A

1

1

DINB

0

DIN A

DIN A

DINB

1

DIN A

2

DIN A

2

2

3

3

CLK

DQM

COM MA ND

CAS# latency=1
t

, DQ's

CK1

CAS# latency=2
t

, DQ's

CK2

Read to Write Interval

T0 T 1 T2 T3 T4 T5 T6 T 7 T8

NOP

NOP

READ A

(Burst Length

NOP WRIT E B NOP NOP NOP

DOUT A

0

¡Ù

4, CAS# Latency = 1, 2)

NOP

Must be Hi-Z before
the Write Command

DIN B

DIN B

DIN B

0

0

DIN B

1

1

DIN B

DIN B

2

2

: "H" or "L"

Read to Write Interval

(Burst Length

¡Ù

4, CAS# Latency = 1, 2)

A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS# latency.

DIN B

DIN B

3

3

Preliminary

8 December

1998

EtronTech

CLK

EM636327

T0 T 1 T2 T3 T4 T5 T6 T7 T8

ADDRESS

COM M A ND

CAS# latency=1
t

, DQ's

CK1

CAS# latency=2
t

, DQ's

CK2

CAS# latency=3
t

, DQ's

CK3

Bank,

Col A

READ A

NOP

DOUT A

NOP Precharge

DOUT A

0

DOUT A

1

0

Read to Precharge

Bank(s)

NOP

DOUT A

DOUT A

DOUT A

DOUT A

2

DOUT A

1

0

DOUT A

3

2

1

(CAS# Latency = 1, 2, 3)

NOP

DOUT A

DOUT A

tRP

NOP

3

DOUT A

2

3

Bank,

Row

Activate

6 Read and AutoPrecharge command

(RAS# = "H", CAS# = "L", WE# = "H", DSF = "L", BS = Bank, A9 = "H", A0-A7 = Column Address)

The Read and AutoPrecharge command automatically performs the precharge operation after
the read operation. Once this command is given, any subsequent command cannot occur within a
time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in
this command and the auto precharge function is ignored.

7 Write command

(RAS# = "H", CAS# = "L", WE# = "L", DSF = "L", BS = Bank, A9 = "L", A0-A7 = Column Address)

The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least t

(min.) before the Write command is

RCD

issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).

T0 T 1 T2 T3 T4 T5 T6 T7 T8

NOP

CLK

COM MA ND

DQ0 - DQ3

command is a masked write (Write-Per-Bit). Data is written to the 32 cells (bits) at the selected
column location subject to the data stored in the Mask register. The overall mask consists of the
DQM inputs, which mask on a per-byte basis, and the Mask register, which masks also on a per-bit
basis. This is shown in the following block diagram.

Preliminary

NO P WRITE A

DIN A

0

The first data element and the write
are registered on the same clock edge.

NOP NO P

DIN A

Burst Write Operation

NOP

DIN A

1

DIN A

2

3

Extra data is masked.

NO P

don't care

(Burst Length = 4, CAS# Latency = 1, 2, 3)

NOP

NOP

NOP

Any Write performed to a row that was opened via an BankActivate & Masked Write Enable

9 December

1998

EtronTech

EM636327

DSF

BankA ctivate
command

D
CK

MR7

MR6

MR5

MR4

MR3

MR2

Q

DQM0

DRAM
CE LL

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

MR1

DQ0

MR0

0 = Masked
1 = Not Masked

Note:

Only the lower byte is shown. The operation is identical for other bytes.

Write Per Bit (I/O Mask) Block Diagram

A write burst without the auto precharge function may be interrupted by a subsequent
Write/Block Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst
length. An interrupt coming from Write/Block Write command can occur on any clock cycle
following the previous Write command (refer to the following figure).

T0 T 1 T2 T3 T4 T5 T6 T 7 T8

CLK

COMM A ND

DQ's

NO P WRITE A

1 Clk Interval

DIN A

WRIT E B NOP

DIN B

0

NOP

DIN B

0

NOP

DIN B

1

DIN B

2

3

NO P

NOP

NO P

Write Interrupted by a Write

The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to
avoid data contention, input data must be removed from the DQs at least one clock cycle before the

Preliminary

(Burst Length = 4, CAS# Latency = 1, 2, 3)

10 December

1998

EtronTech

EM636327

first read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.

T0 T 1 T2 T3 T4 T5 T6 T7 T8

CLK

COM MA ND

CAS# latency=1
t

, DQ's

CK1

CAS# latency=2
t

, DQ's

CK2

CAS# latency=3
t

, DQ's

CK3

NOP WRITE A

DIN A

0

DIN A

0

DIN A

0

Input data for the write is masked.

READ B NO P

don't care

don't care don't care

NOP

Write Interrupted by a Read

NOP

DOUT B0DOUT B

DOUT B

DOUT B

1

DOUT B

0

DOUT B

Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.

(Burst Length = 4, CAS# Latency = 1, 2, 3)

NOP

DOUT B

2

DOUT B

1

DOUT B

0

NOP

3

DOUT B

2

1

DOUT B

3

2

The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).

T0 T 1 T2 T3 T4 T5 T6

CLK

NOP

DOUT B

3

DQM

t

RP

COMMAND

ADDRESS

DQ

WRITE

BANK
COL n

DIN

n

NOP

DIN
n + 1

BANK (S)

t

WR

NOPPrecharge NOP NOP Activate

ROW

: don't care

Note:

The DQMs can remain low in this example if the length of the write burst is 1 or 2.

Write to Precharge

When the Burst-Read-Single-Write mode is selected, the write burst length is 1 regardless of
the read burst length (refer to Figures 21 and 22 in Timing Waveforms).

8 Block Write command

(RAS# = "H", CAS# = "L", WE# = "L", DSF = "H", BS = Bank, A9 = "L", A3-A7 = Column Address,
DQ0-DQ31 = Column Mask)

The block writes are non-burst accesses that write to eight column locations simultaneously. A
single data value, which was previously loaded in the Color register, is written to the block of eight
consecutive column locations addressed by inputs A3~A7. The information on the DQs which are

Preliminary

11 December

1998

EtronTech

EM636327

CR0

CR 1CR2

CR3

CR4

CR5

CR6

CR7

registered coincident with the Block Write command is used to mask specific column/byte
combinations within the block. The mapping of the DQ inputs to the column/byte combinations is
shown in following table.

The overall Block Write mask consists of a combination of the DQM inputs, the Mask register,
and the column/byte mask information, as shown in the following figure. The DQM and Mask
register masking operates normally as for a Write command, with the exception that the mask
information is applied simultaneously to all eight columns. Therefore, in a Block Write, a given bit is
written only if a "0" is registered for the corresponding DQM input, a "1" is registered for the
corresponding DQ signal, and the corresponding bit in the Mask register is "1".

Block of Columns

(selected by A3-A7 registered

coincident with Block Write command)

Row in Bank

(selected by A0-A9,

and BS registered

coincident with BankActivate

Command)

Write Command

BankActivate

command

Mask Register

(previously loaded

from corresponding

DQ inputs)

Column Mask

on the DQ

inputs

(registered

coincident

with Block

DSF

CK

QD

MR0
MR 1
MR2
MR3
MR4
MR5
MR6
MR7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM0

Note:

Preliminary

Only the lower byte is shown. The operation is identical for other bytes.

Block-Write Masking Block Diagram

12 December

1998

EtronTech

EM636327

DQ Column Address DQ Planes DQ Column Address DQ Planes

Inputs A2 A1 A0 Controlled Inputs A2 A1 A0 Controlled

DQ0 0 0 0 0~7 DQ16 0 0 0 16~23
DQ1 0 0 1 0~7 DQ17 0 0 1 16~23
DQ2 0 1 0 0~7 DQ18 0 1 0 16~23
DQ3 0 1 1 0~7 DQ19 0 1 1 16~23
DQ4 1 0 0 0~7 DQ20 1 0 0 16~23
DQ5 1 0 1 0~7 DQ21 1 0 1 16~23
DQ6 1 1 0 0~7 DQ22 1 1 0 16~23
DQ7 1 1 1 0~7 DQ23 1 1 1 16~23
DQ8 0 0 0 8~15 DQ24 0 0 0 24~31

DQ9 0 0 1 8~15 DQ25 0 0 1 24~31
DQ10 0 1 0 8~15 DQ26 0 1 0 24~31
DQ11 0 1 1 8~15 DQ27 0 1 1 24~31
DQ12 1 0 0 8~15 DQ28 1 0 0 24~31
DQ13 1 0 1 8~15 DQ29 1 0 1 24~31
DQ14 1 1 0 8~15 DQ30 1 1 0 24~31
DQ15 1 1 1 8~15 DQ31 1 1 1 24~31

A block write access requires a time period of t

NOP cycles(m equals (t

- tCK)/tCK rounded up to the next whole number), after the Block Write

BWC

to execute, so in general, there should be

BWC

command. However, BankActivate or BankPrecharge commands to the other bank are allowed.
When following a Block Write with a BankPrecharge or PrechargeAll command to the same bank,
t

must be met.

BPL

m

9 Write and AutoPrecharge command (refer to the following figure)

(RAS# = "H", CAS# = "L", WE# = "L", DSF = "L", BS = Bank, A9 = "H", A0-A7 = Column Address)

The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is
performed in this command and the auto precharge function is ignored.

T0 T 1 T2 T3 T4 T 5 T6 T7 T8

CLK

COM MA ND

CAS# latency=1
t

, DQ's

CK1

CAS# latency=2
t

, DQ's

CK2

CAS# latency=3
t

, DQ's

CK3

Burst Write with Auto-Precharge

Bank A

Activate

tDAL= tWR + tRP

NO P NO P

NOP NO P

Write A

AutoPrecharge

DIN A

0

DIN A

0

DIN A

0

NOP

DIN A

DIN A

DIN A

NO P

DAL

t

1

*

tDAL

1

*

tDAL

1

*

Begin AutoPrecharge
Bank can be reactivated at completion of tDAL

*

(Burst Length = 2, CAS# Latency = 1, 2, 3)

NOP

Preliminary

13 December

1998

EtronTech

EM636327

10 Block Write and AutoPrecharge command

(RAS# = "H", CAS# = "L", WE# = "H", DSF = "H", BS = Bank, A9 = "H", A3-A7 = Column Address,
DQ0-DQ31 = Column Mask)

The Block Write and AutoPrecharge command performs the precharge operation automatically
after the block write operation. Once this command is given, any subsequent command can not
occur within a time delay of {t

11 Mode Register Set command

(RAS# = "L", CAS# = "L", WE# = "L", DSF = "L", BS, A0-A9 = Register Data)

The mode register stores the data for controlling the various operating modes of SGRAM. The
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
Length in the Mode register to make SGRAM useful for a variety of different applications. The
default values of the Mode Register after power-up are undefined; therefore this command must be
issued at the power-up sequence. The state of pins A0~A8 and BS in the same cycle is the data
written to the mode register. One clock cycle is required to complete the write in the mode register
(refer to the following figure). The contents of the mode register can be changed using the same
command and the clock cycle requirements during operation as long as both banks are in the idle
state.

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10

CLK

t

CK2

CKE

+ tRP(min.)}.

BPL

Clock min.

CS#

RAS#

CAS#

WE#

DSF

BS

A 9

A0-A8

DQM

DQ

Hi-Z

Address Key

RP

t

Preliminary

PrechargeAll

Mode Register

Set Command

Mode Register Set Cycle

14 December

Any
Command

(CAS# Latency = 1, 2, 3)

1998

EtronTech

EM636327

The mode register is divided into various fields depending on functionality.

• Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the

Burst Length to be 1, 2, 4, 8, or full page.

A2 A1 A0 Burst Length

0 0 0 1
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Full Page

• Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode.

Sequential Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only
supports burst length of 4 and 8.

A3 Addressing Mode

0 Sequential
1 Interleave

--- Addressing Sequence of Sequential Mode

An internal column address is performed by increasing the address from the column
address which is input to the device. The internal column address is varied by the Burst
Length as shown in the following table. When the value of column address, (n + m), in
the table is larger than 255, only the least significant 8 bits are effective.

Data n 0 1 2 3 4 5 6 7 - 255 256 257 -

Column Address

Burst Length 4 words:

--- Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting
the address bits in the sequence shown in the following table.

Data n Column Address Burst Length
Data 0 A7 A6 A5 A4 A3 A2 A1 A0
Data 1 A7 A6 A5 A4 A3 A2 A1 A0# 4 words
Data 2 A7 A6 A5 A4 A3 A2 A1# A0
Data 3 A7 A6 A5 A4 A3 A2 A1# A0# 8 words
Data 4 A7 A6 A5 A4 A3 A2# A1 A0
Data 5 A7 A6 A5 A4 A3 A2# A1 A0#
Data 6 A7 A6 A5 A4 A3 A2# A1# A0
Data 7 A7 A6 A5 A4 A3 A2# A1# A0#

• CAS# Latency Field (A6~A4)

n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 -

2 words:

8 words:

Full Page: Column address is repeated until terminated.

Preliminary

15 December

1998

EtronTech

EM636327

This field specifies the number of clock cycles from the assertion of the Read command to
the first read data. The minimum whole value of CAS# Latency depends on the frequency
of CLK. The minimum whole value satisfying the following formula must be programmed
into this field. t

A6 A5 A4 CAS# Latency

0 0 0 Reserved
0 0 1 1 clock
0 1 0 2 clocks
0 1 1 3 clocks
1 X X Reserved

• Test Mode field (A9~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal

operation.

A9 A8 A7 Test Mode

X 0 0 normal mode
X 0 1 Vendor Use Only
X 1 X Vendor Use Only

• Single Write Mode (BS)
This bit is used to select the write mode. When the BS bit is "0", the Burst-Read-Burst-

Write mode is selected. When the BS bit is "1", the Burst-Read-Single-Write mode is
selected.

CAC

(min)

¡Ø

CAS# Latency X t

CK

BS Single Write Mode

0 Burst-Read-Burst-Write
1 Burst-Read-Single-Write

12 Special Mode Register Set command

(RAS# = "L", CAS# = "L", WE# = "L", DSF = "H", BS, A0-A9 = Register Data)

The special mode register is used to load the Color and Mask registers, which are used in Block
Write and masked Write cycles. The control information being written to the Special Mode register
is applied to the address inputs and the data to be written to either the Color register or the Mask
register is applied to the DQs. When A6 is "HIGH" during a Special Mode Register Set cycle, the
Color register will be loaded with the data on the DQs. Similarly, when A5 is "HIGH" during a
Special Mode Register Set cycle, the Mask register will be loaded with the data on the DQs.
A6=A5=1 in the Special Mode Register Set cycle is illegal.

Functions BS A9 ~ A7 A6 A5 A4 ~ A0

Leave Unchanged X X 0 0 X
Load Mask Register X X 0 1 X
Load Color Register X X 1 0 X

Illegal X X 1 1 X

One clock cycle is required to complete the write in the Special Mode register. This command
can be issued during the active state. As in a write operation, this command accepts the data
needed through DQ pins. Therefore, it should be attended not to induce bus contention.

13 No-Operation command

(RAS# = "H", CAS# = "H", WE# = "H")

The No-Operation command is used to perform a NOP to the SGRAM which is selected (CS#
is Low). This prevents unwanted commands from being registered during idle or wait states.

Preliminary

16 December

1998

EtronTech

14 Burst Stop command

(RAS# = "H", CAS# = "H", WE# = "L", DSF = "L")

The Burst Stop command is used to terminate either fixed-length or full-page bursts. This
command is only effective in a read/write burst without the auto precharge function. The terminated
read burst ends after a delay equal to the CAS# latency (refer to the following figure). The
termination of a write burst is shown in the following figure.

T0 T 1 T2 T3 T4 T5 T6 T7 T8

CLK

EM636327

COM MA ND

CAS# latency=1
t

, DQ's

CK1

CAS# latency=2
t

, DQ's

CK2

CAS# latency=3
t

, DQ's

CK3

READ A

NOP

DOUT A0DOUT A

NOP Burst Stop

DOUT A0DOUT A

1

DOUT A0DOUT A

Termination of a Burst Read Operation

T0 T 1 T2 T3 T4 T5 T6 T 7 T8

CLK

COM MA ND

CAS# latency=1, 2, 3
DQ's

NOP WRITE A

DIN A

NOP Burst Stop

DIN A

0

DIN A

1

Termination of a Burst Write Operation

NOP

DOUT A2DOUT A

1

3

DOUT A2DOUT A

1

(Burst Length

NOP

don't care

2

Input data for the Write is masked.

(Burst Length = X, CAS# Latency = 1, 2, 3)

NO P

The burst ends after a delay equal to the CAS# latency.

DOUT A2DOUT A

¡Ö

NOP

NOP

3

NOP

3

4, CAS# Latency = 1, 2, 3)

NOP

NOP

NOP

NO P

15 Device Deselect command

(CS# = "H")

The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar
to the No Operation command.

16 AutoRefresh command (refer to Figures 3 & 4 in Timing Waveforms)

(RAS# = "L", CAS# = "L", WE# = "H", DSF = "L", CKE = "H", BS, A0-A9 = Don't care)

The AutoRefresh command is used during normal operation of the SGRAM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 2048 times within 32ms. The time required to complete the auto
refresh operation is specified by tRC(min.). To provide the AutoRefresh command, both banks need
to be in the idle state and the device must not be in power down mode (CKE is high in the previous
cycle). This command must be followed by NOPs until the auto refresh operation is completed. The
precharge time requirement, tRP(min), must be met before successive auto refresh operations are
performed.

Preliminary

17 December

1998

EtronTech

EM636327

17 SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms)

(RAS# = "L", CAS# = "L", WE# = "H", DSF = "L", CKE = "L", BS, A0-A9 = Don't care)

The SelfRefresh is another refresh mode available in the SGRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh command is registered, all
the inputs to the SGRAM become "don't care" with the exception of CKE, which must remain LOW.
The refresh addressing and timing is internally generated to reduce power consumption. The
SGRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited
by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).

18 SelfRefresh Exit command (refer to Figure 5 in Timing Waveforms)

(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")

This command is used to exit from the SelfRefresh mode. Once this command is registered,
NOP or Device Deselect commands must be issued for tRC(min.) because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
performed during normal operation, a burst of 2048 auto refresh cycles should be completed just
prior to entering and just after exiting the SelfRefresh mode.

19 Clock Suspend Mode Entry / PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in

Timing Waveforms)

(CKE = "L")

When the SGRAM is operating the burst cycle, the internal CLK is suspended(masked) from
the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when both banks are in the idle state, this
command performs entry into the PowerDown mode. All input and output buffers (except the CKE
buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or
PowerDown state longer than the refresh period (32ms) since the command does not perform any
refresh operations.

20 Clock Suspend Mode Exit / PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing

Waveforms)

(CKE= "H")

When the internal CLK has been suspended, the operation of the internal CLK is reinitiated
from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is
in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the
active state. t
subsequent commands can be issued after one clock cycle from the end of this command.

21 Data Write / Output Enable, Data Mask / Output Disable command

(DQM = "L", "H")

During a write cycle, the DQM signal functions as a Data Mask and can control every word of
the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is
also used for device selection, byte selection and bus control in a memory system. DQM0 controls
DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, and DQM3 controls
DQ24 to DQ31. DQM masks the DQ's by a byte regardless that the corresponding DQ's are in a
state of write-per-bit masking or pixel masking. Each DQM0-3 corresponds to DQ0-7, DQ8-15,
DQ16-23, and DQ24-31.

(min.) is required when the device exits from the PowerDown mode. Any

PDE

Preliminary

18 December

1998

EtronTech

EM636327

Absolute Maximum Rating

Symbol Item Rating Unit Note

VIN, V

OUT

VDD, V

DDQ

T

OPR

T

STG

T

SOLDER

P

D

I

OUT

Recommended D.C. Operating Conditions (Ta = 0~70°C)

Symbol Parameter Min. Typ. Max. Unit Note

V

DD

V

DDQ

V

V

Power Supply Voltage(for I/O Buffer) 3.0 3.3 3.6 V 2

IH
IL

LVTTL Input High Voltage 2.0

LVTTL Input Low Voltage - 0.3

Input, Output Voltage - 0.3~VDD + 0.3 V 1

Power Supply Voltage - 0.3~4.6 V 1

Operating Temperature 0~70

Storage Temperature - 55~150

Soldering Temperature (10s) 260

Power Dissipation 1 W 1

Short Circuit Output Current 50 mA 1

Power Supply Voltage 3.0 3.3 3.6 V 2

¡Ð
¡Ð

°C
°C
°C

VDD + 0.3 V 2

0.8 V 2

1
1
1

Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25°C)

Symbol Parameter Min. Max. Unit

C

I

C

I/O

Note: These parameters are periodically sampled and are not 100% tested.

Input Capacitance
Input/Output Capacitance

¡Ð
¡Ð

5 pF
7 pF

Preliminary

19 December

1998

EtronTech

EM636327

Recommended D.C. Operating Conditions (VDD = 3.3V±0.3V, Ta = 0~70°C)

- 55/6/7/8/10

Description/Test condition Symbol

Operating Current

tRC ≥ tRC(min), Outputs Open

Address changed once during t

Burst Length = 2

CK

(min).

1 bank operation
2 bank interleave

operation

Precharge Standby Current in non-power down mode

tCK = tCK(min), CS# ≥ VIH, CKE ≥ VIL(max)
Input signals are changed once during 30ns.
Precharge Standby Current in non-power down mode

tCK = ∞, CKE ≥ VIL(max), Input signals are stable.
Precharge Standby Current in power down mode
tCK = tCK(min), CKE ≤ VIL(max)
Precharge Standby Current in power down mode

tCK = ∞, CKE ≤ VIL(max)
Active Standby Current in power down mode
CKE ≤ VIL(max), tCK = tCK(min)
Active Standby Current in non-power down mode
CKE ≥ VIL(max), tCK = tCK(min)
Operating Current (Burst mode)
tCK=tCK(min), Outputs Open, Multi-bank interleave,gapless data
Refresh Current
tRC ≥ tRC(min)
Self Refresh Current
CKE ≤ 0.2V
Operating Current (Block Write)
tCK=tCK(min), Outputs Open, t

BWC

= t

BWC

(min).

I

DD1

I

DD1B

I

DD2N

I

DD2NS

I

DD2P

I

DD2PS

I

DD3P

I

DD3N

I

DD4

I

DD5

I

DD6

I

DD7

200/190/180/160/130 3
290/270/250/225/180 3

300/280/265/250/200 3, 4
130/125/120/115/110 3

250/240/235/230/220

Max.

Unit

110/90/85/75/60

60/50/45/40/30

3 3
3 mA

18/13/10/9/7 3

100/90/80/70/55

3

Note

3

Parameter Description Min. Max. Unit Note

I

IL

( 0V ≤ V

I

OL

V

OH

V

OL

Input Leakage Current

≤ VDD, All other pins not under test = 0V )

IN

Output Leakage Current

Output disable, 0V ≤ V

OUT

≤ V

DDQ

)

LVTTL Output "H" Level Voltage

( I

= -2mA )

OUT

LVTTL Output "L" Level Voltage

( I

= 2mA )

OUT

- 5 5

- 5 5

2.4

¡Ð

¡Ð

0.4 V

µA

µA

V

Preliminary

20 December

1998

EtronTech

EM636327

Electrical Characteristics and Recommended A.C. Operating Conditions

(VDD = 3.3V

Symbol A.C. Parameter

t

RC

t

RCD

t

RP

t

RRD

t

RAS

t

WR

t

CK1

t

CK2

t

CK3

t

CH

t

CL

t

AC1

t

AC2

t

AC3

t

CCD

t

OH

t

LZ

t

HZ

t

IS

t

IH

t

SRX

t

PDE

t

RSC

t

BWC

t

BPL

t

REF

¡Ó

0.3V, Ta = 0~70°C) (Note: 5, 6, 7, 8)

Row cycle time
(same bank)
RAS# to CAS# delay
(same bank)
Precharge to refresh/row activate command

(same bank)
Row activate to row activate delay
(different banks)
Row activate to precharge time
(same bank)
Write recovery time

CL* = 1

Clock cycle time CL* = 2

CL* = 3
Clock high time
Clock low time
Access time from CLK CL* = 1
(positive edge) CL* = 2

CL* = 3
CAS# to CAS# Delay time
Data output hold time
Data output low impedance
Data output high impedance
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
Minimum CKE "High" for SelfRefresh exit
PowerDown Exit set-up time
(Special) Mode Register Set Cycle time
Block Write Cycle time
Block Write to Precharge command period
Refresh time

- 55/6/7/8/10

Min. Max. Unit Note

48/54/63/72/90 9

16/16/16/16/30 9

16/16/16/16/30 9

11/12/14/16/20 9

32/36/42/48/60 100,000

5.5/6/7/8/10

ns

19/20/20/20/30

7/7.5/8/8/15

5.5/6/7/8/10
2/2/2.5/3/3.5
2/2/2.5/3/3.5

7/8/13/18/27

5.5/6/6.5/7/12

5/5/5.5/6.5/7.5

1 Cycle
2/2/2/2/3 10
1/1/1/2/2

3.5/4/5/6/8 8

2/2/2/2.5/3 11

1 11

5.5/6/7/8/10

ns

3.5/4/5/6/8 11

5.5/6/7/8/10 9
11/12/14/16/20
11/12/14/16/20

32 ms

10

11
11

11

* CL is CAS# Latency.

Preliminary

21 December

1998

EtronTech

EM636327

Note:

1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.

2. All voltages are referenced to VSS.

3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.

4. These parameters depend on the output loading. Specified values are obtained with the output open.

5. Power-up sequence is described in Note 10.

6. A.C. Test Conditions

LVTTL Interface

Reference Level of Output Signals 1.4V / 1.4V

Output Load Reference to the Under Output Load (B)

Input Signal Levels 2.4V / 0.4V

Transition Time (Rise and Fall) of Input Signals 1ns

Reference Level of Input Signals 1.4V

3.3V

1.2kΩ

Ω

50

Output

30pF

LVTTL D.C. Test Load (A) LVTTL A.C. Test Load (B)

7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed
slope (1 ns).

8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference
levels.

9. These parameters account for the number of clock cycle and depend on the operating frequency of the
clock as follows:
the number of clock cycles = specified value of timing/Clock cycle time
(count fractions as a whole number)

10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.

11.Assumed input rise and fall time tT ( tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e.,
[ ( tR + tF ) / 2 -1] ns should be added to the parameter.

870Ω

Output

Z0=

1.4V

Ω

50

30pF

Preliminary

22 December

1998

EtronTech

12. Power up Sequence

Power up must be performed in the following sequence.

EM636327

1) Power must be applied to VDD and V
and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time.

2) After power-up, a pause of 200µseconds minimum is required. Then, it is recommended that DQM
is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.

3) Both banks must be precharged.

4) Mode Register Set command must be asserted to initialize the Mode register.

5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of
the device.

(simultaneously) when all input signals are held "NOP" state

DDQ

Preliminary

23 December

1998

EtronTech

Timing Waveforms

Bank A

Ban

k B

EM636327

Figure 1. AC Parameters for Write Timing

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T1 4 T15 T16 T1 7 T18 T19 T20 T21 T22

CLK

CKE

CS#

RAS#

CA S#

WE#

DSF

BS

tCH

tCL

tIS

tIS
tIH

tCK2

Begin AutoPrecharge

Bank A

(Burst Length=4, CAS# Latency=2)

Begin AutoPrecharge

Bank B

tIS

A 9

A0-A 8

DQM

DQ

Hi-Z

tIS

RAx

RBx

Activate

Command

Bank A

t

IH

RBx

CAx

t

RCD

Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3

Write with

AutoPrecharge

Command

RBx

tRC

Activate

Command

Bank B

CBx RAy

Write with

AutoPrecharge

Command

t

DAL

RAy

Activate

Command

Bank A

tIS

CAy

Write

Command

Bank A

tIH

tWR

Precharge
Command

Bank A

t

RP

RAz

RAz

Activate

Command

Bank A

t

RRD

RBy

RBy

Activate

Command

Bank B

Preliminary

24 December

1998