ESS ES4227, ES4228 Datasheet
ES4228/ES4227
Internet Set-Top Box Solution
Product Brief
DESCRIPTION
The ES4228 MPEG video/audio decoder works as the central
processing unit for Internet set-top box applications, while the
ES4227 compan ion chip integrates all of the nec essary discrete
components for Intern et set-top boxes. The high level of flexibility
and versatility provided by the ES4228/ES4227 chipset makes it
the most cost-effective, high-performance solution for the
Internet set-top box market.
The ES4228 includes a programmable internal RISC processor
core that makes it adaptable for use in embedded systems
applications such as set-top b oxes. The ES42 27 comp anion chi p
supplies prope r vide o sy nc cap abi li ties and p erforms NTS C- and
PAL-based video encoding and decoding as necessary to
provide broadcast quality video to the television screen.
The ES4227 is a mixed-signal chip that includes a high quality
NTSC/PAL encoder, two progra mmab le 16- bit si gma-d elt a a udio
DACs, a PLL clock synthes izer, two microp hone A/D conve rters,
an I/O expansion port, and an echo/surround sound circuit.
The ES4228 controls the ES4227 through a proprietary bus, the
Device Serial Communication (DSC) bus. The ES4227 gets
video input and audio input from the ES4228. Video format is 8bit YUV, and audio format is I
Command and register accesses are issued through the DSC
interface from the ES4228 to the ES4227 through the DSC
interface for accessing the internal registers of the ES4227. The
DSC interfac e port is compri sed of three inte rface signals, the
strobe (DSC_S), data (DSC_D), and clock (DSC_C).
The DSC port is selected when the DSC strobe goes high and
latches the data at the rising edge of the clock. Each 16-bit DSC
transfer is comprised of an address followed by data.
The digital video encoder of the ES4227 uses three 9-bit video
DACs to generate composite and S-video analog signals. One
video DAC handles the composite video output, while the other
two handle the S-video outputs. Color space conversions are
provided t o match the inpu t data to the re quired outp ut format,
then the data is filtered to meet the selected video standards.
The program mable au dio DACs of the ES 4227 offer different ial
audio outputs. These outputs ensure further noise reduction
while providing a dual audio output with a signal-to-noise ratio
better than 90 dB. The expansion I/O port is address-mapped to
the ES4228. Four pins of the port can be configured as edgetriggered interrupts, supporting critical functions such as
handling remote control and modem interrupt requests, DVD/
SVCD loader resets and modem board resets.
The ES4228 is available in an industry-standard 208-pin Plastic
Quad Flat Pack (PQFP) package, while the ES4227 is avai lable
in an industry-standard 100-pin PQFP package.
2
S.
ES4228 FEATURES
• Single-chip MPEG-2 vid eo/ audio de code r a nd syste m
parser in
208-pin PQFP package.
• 640 x 480 NTSC and 640 x 576 PAL television video resolutions
supported.
• Software-configurable for Internet e-mail and web browser
functions.
• Karaoke, On-Screen Display (OSD), Playback Control (PBC)
for Video CD 2.0 and 3.0 and trick mode functions supported.
• VideoCD 1.1, 2.0, Interactive 3.0, Super VCD and Audio CD
compatible (SVCD and DVD configurations only).
• SmartScale™ video scaling supports both X-axis and Y-axis
interpolationa and bidirectional NTSC to PAL and PAL to NTSC
conversion.
• SmartZoom ™supports 4X picture enlargement and reduction
• SmartStream™ supports video bit stream error concealment.
ES4227 FEATURES
• Multi-standard TV encoder in 100-pin PQFP package supports
CCIR601 non-square operation, NTSC/PAL formats,
simultaneous composite and S-video output, and interlaced
operation.
• Two programmable 16-bit sigma-delta audio DACs accept I
format data, and provide dual audio output with SNR better than
90 dB.
2
S
• Dual microphone input and vocal assist hardware support
provided.
• PLL clock synthesizer based on 27 MHz crystal input generates
required clocks for video encoder, audio DAC, echo and
surround sound, and video processor.
• Device Serial Communication (DSC) port for command issued/
register access.
• Digitally controlled echo with up to 130 ms delay.
SOFTWARE SUPPORT
• Software stack support for the POP3, SMTP and SNMP Internet
e-mail protocols defined by RFC 821, RFC 1157and RFC 2449.
• Software stack support provided for the HTTP Web browsing
protocol defined by RFC 1945, RFC 2068 and RFC 2616.
• Software stack support provided for the TCP/IP Internet
protocols defined by RFC 791 and RFC 793.
• Software stack support provided for RTP payload format for
MPEG-1/2 and H.261 video streaming protocols defined by
RFC 2032, RFC 2038 and RFC 2250.
• Character generation and software support for English,
Big 5/GB Chinese and Japanese fonts.
• Software support for infrared remote control and wireless
keyboard.
ESS Technology, Inc. SAM0378-053001 1
ES4228 PINOUT
Figure 1 shows the ES4228 device pinout.
NC
NC
VSS
VCC
NC
VPP
AUX0
AUX1
AUX2
VSS
VCC
AUX3
AUX4
AUX5
AUX6
AUX7
LOE#
VSS
VCC
LCS0#
LCS1#
LCS2#
LCS3#
VSS
LD0
LD1
LD2
LD3
LD4
VCC
VSS
LD5
LD6
LD7
LD8
LD9
LD10
LD11
VSS
VCC
LD12
LD13
LD14
LD15
LWRLL#
LWRHL#
VSS
VCC
NC
NC
LA0
LA1
LA2
LA3
VSS
NC
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
1 2 3 4 5 6 7 8 9101112131415161718192021222324252627282930313233343536373839404142434445464748495051
NC
153
NC
152
NC
NC
VCC
VSS
NC
NC
145
146
147
148
149
150
151
HD4
HD5
HD6
NC
144
NCNCHD15
142
143
VSS
HD13
HD12
HD11
HD10
HD9
HD14
VCC
137
138
139
140
141
HD8
HD7
VCC
130
131
132
133
134
135
136
VSS
129
HD3
125
126
127
128
ES4228
208-Pin PQFP Package
HD2
124
HD1
123
HD0
122
VCC
121
VSS
120
HSYNC#
119
VSYNC#
118
PCLKQSCN
117
ES4228/ES4227 PRODUCT BRIEF
PCLK2XSCN
YUV7
YUV6
YUV5
VSS
VCC
YUV4
YUV3
YUV2
YUV1
YUV0
DCLK
105
106
107
108
109
110
111
112
113
114
115
116
52
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VCC
VSS
DSCK
DQM
DCS0#
VCC
VSS
DCS1#
DB15
DB14
DB13
DB12
VCC
VSS
DB11
DB10
DB9
DB8
DB7
DB6
VSS
VCC
DB5
DB4
DB3
DB2
DB1
DB0
VSS
VCC
DRAS2#
DRAS1#
DRAS0#
DWE#
DOE#/DSCK_EN
DCAS#
VCC
VSS
DMA11
DMA10
DMA9
DMA8
DMA7
DMA6
VSS
VCC
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0
VCC
LA4
LA5
LA6
LA7
LA8
LA9
VSS
VCC
VSS
LA11
LA12
LA13
LA10
VCC
LA14
LA15
LA16
LA17
LA18
LA19
VSS
VCC
LA21
LA20
TDMDR
RESET#
TDMCLK
TDMDX/RSEL
TDMFS
VSS
VCC
TDMTSC#
SEL_PLL2
TSD/SEL_PLL0
TWS/SEL_PLL1
MCLK
NC
VSS
VCC
TBCK
RSD
XIN
VSS
RWS
VCC
XOUT
RBCK
APLLCAP
NC
NC
NC
Figure 1 ES4228 Device Pinout
2 SAM0378-053001 ESS Technology, Inc.
ES4228/ES4227 PRODUCT BRIEF
ES4228 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES4228.
Table 1 ES4228 Pin Descriptions List
Name Number I/O Description
1, 9, 18, 27, 35, 44 , 5 1, 5 9,
VCC
LA[21:0] 23:19, 16:10, 7:2, 207:204 O Device address output.
VSS
RESET# 24 I Reset input, active low.
TDMDX
RSEL
TDMDR 28 I TDM receive data.
TDMCLK 29 I TDM clock input.
TDMFS 30 I TDM frame sync.
TDMTSC# 31 O TDM output enable, active low.
TWS 32 O Audio transmit frame sync.
SEL_PLL1 I Refer to the description and matrix for SEL_PLL0 pin 33.
TSD
SEL_PLL0
68, 75, 83, 92, 99, 104, 1 1 1 ,
121, 130, 139, 148, 157,
164, 172, 183, 193, 201
8, 17, 26, 34, 43, 52, 60,
67, 76, 84, 91 , 98, 103, 1 12,
120, 129, 138, 147, 156,
163, 171, 177, 184, 192,
200, 208
25
33
I
3.45 V power supply.
I
Ground.
O TDM transmit data.
I ROM Select.
RSEL Selection
0 8-bit ROM
1 16-bit ROM
O Audio transmit serial data port.
I System and DSCK output clock frequency selection at reset time. The matrix
below lists the available clock frequencies and their respecitve PLL bit
settings.
SEL_PLL2 SEL_PLL1 SEL_PLL0 Clock Output
000VCO doesn’t work.
0 0 1 27 MHz
0 1 0 Bypass mode
0 1 1 54 MHz
1 0 0 121.5 MHz
1 0 1 81 MHz
1 1 0 94.5 MHz
1 1 1 108 MHz
SEL_PLL2 36 I Refer to the description and matrix for SEL_PLL0 pin 33.
MCLK 39 I/O Audio master clock for audio DAC.
TBCK 40 I/O Audio transmit bit clock.
RSD 45 I Audio receive serial data.
RWS 46 I Audio receive frame sync.
RBCK 47 I Audio receive bit clock.
APLLCAP 48 I Analog PLL Capacitor.
XIN 49 I Crystal input.
XOUT 50 O Crystal output.
ESS Technology, Inc. SAM0378-053001 3
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