ESPROS epc10 Series, epc101, epc100 Reference Manual

Reference Manual epc10x
Reference Manual
epc100 epc101
VDD33
© 2012 ESPROS Photonics Corporation Characteristics subject to change without notice
Page 1/26 Reference Manual epc100 - V2.2
VDD
Interface
Interface
Parameter
Memory
V
LED SCK
LED
LED
VDD18
GND
Processor
Voltage Regulator
CS
SPI
Controller
SI
EN
Signal
Processor
SO
f
PD
D1
Reference Manual epc10x
Table of Contents
1. Introduction.................................................................................................................................................... 3
2. Light Curtain Principle.................................................................................................................................. 4
2.1 System Overview........................................................................................................................................................................................... 4
2.2 Light Curtain Receiver Edge..........................................................................................................................................................................6
2.3 Light Curtain Emitter Edge.............................................................................................................................................................................6
3. 2-Wire Bus...................................................................................................................................................... 7
3.1 General Description....................................................................................................................................................................................... 7
3.2 Bus Wire Considerations............................................................................................................................................................................... 8
3.3 Bus Signal Waveform.................................................................................................................................................................................... 9
4. Parameter Memory...................................................................................................................................... 10
4.1 Receiver Parameters (epc100).................................................................................................................................................................... 11
4.2 Sample Receiver Parameter Setting........................................................................................................................................................... 13
4.3 Transmitter Parameters (epc101)................................................................................................................................................................14
4.4 Sample Transmitter Parameter Setting....................................................................................................................................................... 16
5. Timing........................................................................................................................................................... 17
5.1 Overview...................................................................................................................................................................................................... 17
5.2 Timing Details.............................................................................................................................................................................................. 17
5.3 Special Cases..............................................................................................................................................................................................18
6. SPI Interface................................................................................................................................................. 19
6.1 Timing Specifications...................................................................................................................................................................................19
6.2 General Description..................................................................................................................................................................................... 19
6.3 Command List.............................................................................................................................................................................................. 20
6.4 Detailed Command Descriptions................................................................................................................................................................. 21
7. Address Programming................................................................................................................................ 24
7.1 General Description..................................................................................................................................................................................... 24
7.2 Programming Procedure..............................................................................................................................................................................25
8. Considerations for Safety Applications..................................................................................................... 26
8.1 Data Integrity on the 2-Wire Power-Bus......................................................................................................................................................26
8.2 Residual Error Rate..................................................................................................................................................................................... 26
8.3 Error Cases.................................................................................................................................................................................................. 26
8.4 Error Codes..................................................................................................................................................................................................26
© 2012 ESPROS Photonics Corporation Characteristics subject to change without notice
Page 2/26 Reference Manual epc100 - V2.2
Reference Manual epc10x

1. Introduction

The epc10x chip set is a general purpose CMOS integrated circuit for light-curtain applications. epc100 is used on the receiver side (Rx) whereas epc 101 is on the emitter side (Tx). Up to 1023 devices may be connected to two respecti vely four wires in parallel. Each device can be individually addressed by an epc100 chip which acts as the interface between a microcontroller and the 2-wire bus. It manages the bus traffic between the microcontroller and the individual Rx and Tx elements. Programmable fuses i.e. for the address, sensitivity, LED light pulse width, etc. allow the device to be paramet ­rized in the final system (OTP memory).
The microcontroller activates the Tx elements and reads the status of the Rx in a sequential manner. The status of the Rx elements can be 'no light pulse received', 'low level light pulse received' and 'high level light pulse received'.
Each chip can be put into 'standby mode' or 'operating mode' to reduce power consumption. During 'standby mode', power consumption is reduced and the photo diode is shorted. In the 'operation mode', the device is active and ready to receive a light pulse generated by an LED in the emitter side of the light curtain.
During a normal scan, the microcontroller addresses one device after the other and fetches the result with a delay of three scan periods. Thus, the microcontroller has to manage the emitter light pulses on the emitter edge of the light curtain as well. This function is supported by the epc101 device which is the counterpart of epc100 (refer to a separate data sheet and reference manual).
This Manual describes the various operation and programming modes in order to use Rx and interface chip epc100 and the Tx chip epc101.
© 2012 ESPROS Photonics Corporation Characteristics subject to change without notice
Page 3/26 Reference Manual epc100 - V2.2
Reference Manual epc10x

2. Light Curtain Principle

2.1 System Overview

A light curtain consist of an emitter edge (Tx) and a receiver edge (Rx). The Tx edge contains a number of light emitters, typically infrared LEDs which emit their light towards the Rx edge. The Rx edge contains typically the same number of photo receivers like the number of emitters in the Tx edge. Typical numbers of receivers or emitters are 10, 24, 40 or every figure between 1 and up to 1023 are possible, depending on the application. The following drawing shows a typical light curtain setup.
© 2012 ESPROS Photonics Corporation Characteristics subject to change without notice
Page 4/26 Reference Manual epc100 - V2.2
Micro
Controller
Out
2-Wire Bus
epc101 with LED
epc100 with PD
light cone generated by the LED
active light beam
light beam number
Tx edge
Bus Interface (epc100)
Bus Interface (epc100)
Rx edge
Bus Termination
50Ω, 100nF
SPI-Inte
rface
Figure 1: Light curtain principle
Reference Manual epc10x
The left side of Figure 1 shows the Tx edge containing 10 emitter elements. Each emitter element consist of an epc101 chip with an LED and a few other components. Each of the Tx elements is connected to a 2-wire bus1, which is fed to the Rx edge on the right side of Figure 1. The Rx edge contains 10 receiver elements, consisting of an epc100 chip with a photo diode and a few passive components. A microcontroller which is typically but not necessarily located in the receiver edge controls the 2-wire bus through an epc100 chip. This chip acts as a bus controller. Because every Tx and Rx element has a unique address, the microcontroller has individual access to all bus components.
Each of the Tx elements sends light, typically infrared light, in a cone towards the Rx edge. The emitted light of one LED illuminates usually more than one receiver element because of a rather wide cone angle2 and a small distance between the individual elements in the edge3. If all emitters would be active at the same time, small objects between the Tx and Rx edge would not be detected because of light bypassing. Thus, a sequential operation mode has to be established. This sequential operation is typically like this:
1. The first Rx (Rx1) element is turned on (active mode).
2. Then, the first Tx (Tx1) element is activated so it sends a short light pulse towards the Rx edge, forming the active light
beam .
3. If there is no obstacle between Tx1 and Rx1, Rx1 receives this light pulse and stores it into a local memory.
4. The microcontroller reads out the content of the memory in Rx1 and stores the value (light beam interrupted or not inter­rupted) into its data memory.
5. Finally, Rx1 is turned off (standby mode).
This sequence, which is also called 'scan', is repeated until all beams are checked and their status is stored in the beam status memory of the microcontroller. The last step is to analyze the beam status memory by the microcontroller. If all beams have the status 'not interrupted', the output of the light curtain can be set to this state. If one ore more beams are interrupted, the output of the light curtain is set to the status 'interrupted'.
The above mentioned sequence is repeated until power is switched off. Because of the fact, that an object can enter into the light grid right after a beam has been checked with the above mentioned procedure, up to two full scan sequences are necessary to reliably detect an object. Thus, the overall maximum response time of the light curtain will be
tR=2∗n∗t
beamteval
(1)
where
t
R
= response time of the light curtain n = number of elements or light beams t
beam
= time to evaluate one beam t
eval
= time to evaluate the beam status memory and generate the output signal
For further reference in optical design considerations please refer to the application note AN01.
1 If the LED pulse current is rather high, i.e. 1 A, two separate bus wires for the LED supply current are needed. Please refer to the data
sheet of epc101 for detailed information. 2 Typical cone angles are between 5° and 40°, depending on the application. 3 The spacing between the individual elements of a light curtain is also called 'grid spacing' and is typically in a range of a few millimeters up
to hundreds of millimeters.
© 2012 ESPROS Photonics Corporation Characteristics subject to change without notice
Page 5/26 Reference Manual epc100 - V2.2
Reference Manual epc10x

2.2 Light Curtain Receiver Edge

Figure 2 shows the epc100 in the light curtain application on the receiver side. It can be used in two main functions:
1. Sensor device R1 .. Rn: It senses the current pulse from the photo diode and transmits the information to the interface device over the 2-wire bus.
2. Interface device IF: It interfaces the serial bus from the microprocessor with the 2-wire bus.
From the point of view of the microcontroller, the whole system looks like a single device with several addressable photo diodes: the microcontroller activates one photo diode and fetches the results after a predefined time. During a normal scan, the microcontroller addresses one device after the other and fetches the result with a delay of three scan periods.

2.3 Light Curtain Emitter Edge

On the emitter side, the epc101 controls the LEDs as the epc100 does for the photo diodes.
TP is a test point used for programming the epc101 chip with the parameters needed in the application. This test point has to be physically accessed during final assembly of the emitter edge.
In the circuit in Figure 3, the LED current is defined by a common current source in the I
LED
line. The resistor R
LED
limits the current through the LED and is not needed in non-safety applications. If such a resistor is inserted, a failure mode can be detected, if more than one LED is active due to a short circuit or a failure in the epc100. It is also possible to have a common voltage supply and to generate the LED current by a resistor.
© 2012 ESPROS Photonics Corporation Characteristics subject to change without notice
Page 6/26 Reference Manual epc100 - V2.2
VDDVDDVDD
VDD33
I
F
epc100
GND
SO SCK
SI
CS
µC
GND
VDD µC
VDDR
PD
VDD33
R
1
epc100
GND
VDD18
PD
VDD33
R
2
epc100
GND
VDD18
PD
VDD33
R
n
VDD
epc100
GND
VDD18
Rx Element 1 Rx Element 2 Rx Element n
Bus Termination
R
TE
100nF
R
TE
I
TE
VDD33
VDDR
epc100
GND
SO SCK
SI
CS
µC
GND
VDD µC
VDDR
VDD
PD
epc101
GND
LED
VDD33
R
LED
+ I
LED
- I
LED
Tx Element 1
R
LED
Tx Element 2
VDD
PD
VDD33
epc101
GND
LED
R
LED
Tx Element n
VDD
PD
VDD33
epc101
GND
LED
TP
Bus Termination
R
TE
100nF
TP TP
R
TE
I
TE
Figure 2: epc100 in the light curtain application as receivers and the interface chip to the microcontroller
Figure 3: epc101 in the Tx edge application
Reference Manual epc10x

3. 2-Wire Bus

3.1 General Description

The 2-wire bus and the power supply utilize the same two wires. The data is transmitted by modulating the current on the power-line. The modulated current, together with the resistor in the power supply, produce a voltage signal on the line. All devices receive this signal. The system is designed to operate with a line impedance of 50Ω (±5%). An inductor in parallel of the resistor or a DC regulator with a lowpass feedback shape the pulses and keep the the DC voltage drop over the resistor low. The required corner frequency of this L/R-filter is listed in the table below.
The communication interface has been designed to be used for line lengths of up to 100m and with up to 1023 sensor devices. For line lengths of up to 3m it is possible to operate the line without termination4. Above this length the line has to be terminated by a resistor of 50Ω (±5%) which is equal to the line impedance and a capacitor of 100nF in series.
The data rate on the 2-wire bus is set by the parameter DRATE. It also defines T
SCANmin
(refer to Chapter Timing on page 17) and the required inductor according to Table 1. The maximum data rate allowed on the 2-wire bis is depending on the bus length. The longer the bus wire, the lower the data rate. Table 1 shows the possible bus wire length according to the data rate.
DRATE k Data Rate on
the 2-Wire Bus
Minimal Data Rate
Required on SPI
Interface
Corner
Frequency
L/R
Inductor
I
TE
Bus Wire
Length
5
00 8 250 kbit/s 300 kbit/s 0.5 MHz 16µH 12 … 100m
01 4 500 kbit/s 600 kbit/s 1 MHz 8µH 6 … 12m
10 2 1 Mbit/s 1.2 Mbit/s 2 MHz 4µH 3 … 6m
11 1 2 Mbit/s 2.4 Mbit/s 4 MHz 2µH ≤ 3m
Table 1: Data rate of the 2-wire communication
The default value of DRATE is 00. The parameter DRATE has to be identical for all devices on one physical 2-wire bus.
The SPI bus should be faster than the 2-wire bus, otherwise the communication does not work. Since the command length dependent on the command type, the delay time to the next command has to be adjusted to the previous command. The time delay can be calculated with the given data length in Table 11 on page 20.
The parameter CDET defines the optimal signal amplitude for the receiver. The maximum rate at pin VDD (5.5V) should not be exceeded and signals which are smaller than 70% of the recommended values are not detected.
Since the command length is dependent on the command type, the delay time to the next command has to be adjusted to the previous command. The time delay can be calculated with the given data length in Table 11 on page 20. The data handling chain of the 2-wire communication channel is shown in Figure 4.
Figure 5 shows the different messages with the parity bits. From the interface to the sensor/transmitter device the “normal command” is used except for the register write command. In the other direction only the register readout has a different format. Notice the different start bits
4 Dependent on the electro-mechanical design and the bus location of the edge, the termination network can be necessary. It is in the
responsibility of the system designer that the data integrity on the bus is guaranteed. Data integrity can be tested by readout bus transmission errors. It is strongly recommended to do that during type qualification during EMI qualification tests.
5 The effective length is dependent on the electro-mechanical design of the edge. The values in the table are indicative only.
© 2012 ESPROS Photonics Corporation Characteristics subject to change without notice
Page 7/26 Reference Manual epc100 - V2.2
Command Data
Original
Message
Parity Bits
added
Manchester
Encoder
Current
Sink
Line
Filter
A/D
Converter
Manchester
Decoder +
Error Detection
Error Correction
Received
Message
Command Data
ReceiverTransmitter
Figure 4: Data handling
Reference Manual epc10x
which identify the direction of the transmission: 00 for the direction interface to sensor devices and 01 in the other direction. Between the telegrams, an idle time of 2 clock periods are need to detect the start of the transmission.

3.2 Bus Wire Considerations

The electromechanical design of a system using multiple epc10x devices on a twisted pair cable with an impedance of typically 100 Ohms has an impact on the overall impedance of the system. Figure 6 shows the change of the cable impedance with smaller element pitch.
On the source side the termination is done by the resistor RTE (see Figure 2), on the other side it is highly recommended to terminate the bus line with an AC terminator network (shown in Figure 7) which matches the overall impedance of the system according to Figure 6. In order to avoid high DC currents in the termination resistor, a capacitor of 100nF should be connected in series to the termination resistor. The interface device has to be placed near the L/R circuit (<1m).
© 2012 ESPROS Photonics Corporation Characteristics subject to change without notice
Page 8/26 Reference Manual epc100 - V2.2
R
TE
100nF
1.0
1.8
3.2
5.6
10.0
17.8
31.6
56.2
100.0
0
20
40
60
80
100
120
Pitch [cm]
Impedance [Ohm]
A0A1A2A3A4A5A6A7A8A9C0C1C2P0P1P2P3P4P5P6P7P8P
9
Device Address Command Parity Bits
A0A1A2A8A
9
C0C1C2P0P1P8P9R0R1R2R3R4D0D1D14D15P0P1P8P
9
Device Address
Command
Parity Bits Parity BitsDataRegister
P0P1P8P
9
Parity Bits
D0D1D9D
10
Data
A0A1A2A8A
9
Device Address
R0R1R2R3R4D0D1D14D15P0P1P8P
9
Parity BitsDataRegister
Normal Command
Write Command
Results
Register Readout
C0C1C
2
A0A1A2A8A
9
Device Address
R0R1R2R3R
4
Register
P0P1P8P
9
Parity BitsCommand
Read Command
Figure 5: Message Structure
Figure 6: Line impedance as a function of the element pitch on a 100 Ohm twisted pair cable
Figure 7: Bus termination network
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