* Pins GPIO6 to GPIO11 on the ESP32-D0WD-V3 chip are connected to the SPI flash integrated on the module and are
not led out.
3.3Strapping Pins
ESP32 has five strapping pins, which can be seen in Chapter 7 Schematics:
• MTDI
• GPIO0
• GPIO2
• MTDO
• GPIO5
Software can read the values of these five bits from register ”GPIO_STRAPPING”.
During the chip’s system reset release (power-on-reset, RTC watchdog reset and brownout reset), the latches of
the strapping pins sample the voltage level as strapping bits of ”0” or ”1”, and hold these bits until the chip is
powered down or shut down. The strapping bits configure the device’s boot mode, the operating voltage of
VDD_SDIO and other initial system settings.
Each strapping pin is connected to its internal pull-up/pull-down during the chip reset. Consequently, if a
strapping pin is unconnected or the connected external circuit is high-impedance, the internal weak
pull-up/pull-down will determine the default input level of the strapping pins.
To change the strapping bit values, users can apply the external pull-down/pull-up resistances, or use the host
MCU’s GPIOs to control the voltage level of these pins when powering on ESP32.
After reset release, the strapping pins work as normal-function pins.
Refer to Table 4 for a detailed boot-mode configuration by strapping pins.
Table 4: Strapping Pins
Voltage of Internal LDO (VDD_SDIO)
PinDefault3.3 V1.8 V
MTDIPull-down01
Booting Mode
PinDefaultSPI BootDownload Boot
GPIO0Pull-up10
GPIO2Pull-downDon’t-care0
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3 Pin Definitions
Enabling/Disabling Debugging Log Print over U0TXD During Booting
PinDefaultU0TXD ActiveU0TXD Silent
MTDOPull-up10
Timing of SDIO Slave
PinDefault
FE Sampling
FE Output
FE Sampling
RE Output
RE Sampling
FE Output
RE Sampling
RE Output
MTDOPull-up0011
GPIO5Pull-up0101
Note:
• FE: falling-edge, RE: rising-edge.
• Firmware can configure register bits to change the settings of ”Voltage of Internal LDO (VDD_SDIO)” and ”Timing
of SDIO Slave” after booting.
• Internal pull-up resistor (R9) for MTDI is not populated in the module, as the flash and SRAM in the module only
support a power voltage of 3.3 V (output by VDD_SDIO).
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4 Functional Description
4Functional Description
This chapter describes the modules and functions integrated in ESP32-WROVER-E and
ESP32-WROVER-IE.
4.1CPU and Internal Memory
ESP32-D0WD-V3 contains two low-power Xtensa®32-bit LX6 microprocessors. The internal memory
includes:
• 448 KB of ROM for booting and core functions.
• 520 KB of on-chip SRAM for data and instructions.
• 8 KB of SRAM in RTC, which is called RTC FAST Memory and can be used for data storage; it is accessed
by the main CPU during RTC Boot from the Deep-sleep mode.
• 8 KB of SRAM in RTC, which is called RTC SLOW Memory and can be accessed by the co-processor
during the Deep-sleep mode.
• 1 Kbit of eFuse: 256 bits are used for the system (MAC address and chip configuration) and the remaining
768 bits are reserved for customer applications, including flash-encryption and chip-ID.
4.2External Flash and SRAM
ESP32 supports multiple external QSPI flash and SRAM chips. More details can be found in Chapter SPI in the
ESP32 Technical Reference Manual. ESP32 also supports hardware encryption/decryption based on AES to
protect developers’ programs and data in flash.
ESP32 can access the external QSPI flash and SRAM through high-speed caches.
• The external flash can be mapped into CPU instruction memory space and read-only memory space
simultaneously.
– When external flash is mapped into CPU instruction memory space, up to 11 MB + 248 KB can be
mapped at a time. Note that if more than 3 MB + 248 KB are mapped, cache performance will be
reduced due to speculative reads by the CPU.
– When external flash is mapped into read-only data memory space, up to 4 MB can be mapped at a
time. 8-bit, 16-bit and 32-bit reads are supported.
• External SRAM can be mapped into CPU data memory space. Up to 4 MB can be mapped at a time.
8-bit, 16-bit and 32-bit reads and writes are supported.
ESP32-WROVER-E and ESP32-WROVER-IE integrate a 4 MB SPI flash and an 8 MB PSRAM for more memory
space.
4.3Crystal Oscillators
The module uses a 40-MHz crystal oscillator.
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4 Functional Description
4.4RTC and LowPower Management
With the use of advanced power-management technologies, ESP32 can switch between different power
modes.
For details on ESP32’s power consumption in different power modes, please refer to section ”RTC and
Low-Power Management” in ESP32 Datasheet.
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5 Peripherals and Sensors
5Peripherals and Sensors
Please refer to Section Peripherals and Sensors in ESP32 Datasheet.
Note:
External connections can be made to any GPIO except for GPIOs in the range 6-11, 16, or 17. GPIOs 6-11 are connected
to the module’s integrated SPI flash and PSRAM. GPIOs 16 and 17 are connected to the module’s integrated PSRAM.
For details, please see Section 7 Schematics.
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6 Electrical Characteristics
6Electrical Characteristics
6.1Absolute Maximum Ratings
Stresses beyond the absolute maximum ratings listed in the table below may cause permanent damage to the
device. These are stress ratings only, and do not refer to the functional operation of the device that should follow
the recommended operating conditions.
Table 5: Absolute Maximum Ratings
SymbolParameterMinMaxUnit
VDD33Power supply voltage–0.33.6V
1
I
output
T
store
1. The module worked properly after a 24-hour test in ambient temperature at 25 °C, and the IOs in three domains
(VDD3P3_RTC, VDD3P3_CPU, VDD_SDIO) output high logic level to ground. Please note that pins occupied by flash
and/or PSRAM in the VDD_SDIO power domain were excluded from the test.
2. Please see Appendix IO_MUX in ESP32 Datasheet for IO’s power domain.
Cumulative IO output current-1,100mA
Storage temperature–4085°C
6.2Recommended Operating Conditions
Table 6: Recommended Operating Conditions
SymbolParameterMinTypicalMaxUnit
VDD33Power supply voltage3.03.33.6V
I
V DD
Current delivered by external power supply0.5--A
TOperating temperature–40-85°C
6.3DC Characteristics (3.3 V, 25 °C)
Table 7: DC Characteristics (3.3 V, 25 °C)
SymbolParameterMinTypMaxUnit
C
V
V
I
I
V
V
IN
IH
IL
IH
IL
OH
OL
Pin capacitance-2-pF
High-level input voltage0.75×VDD
1
-VDD1+0.3V
Low-level input voltage–0.3-0.25×VDD1V
High-level input current--50nA
Low-level input current--50nA
High-level output voltage0.8×VDD
1
--V
Low-level output voltage--0.1×VDD1V
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6 Electrical Characteristics
SymbolParameterMinTypMaxUnit
VDD3P3_CPU
power domain
1, 2
VDD3P3_RTC
power domain
1, 2
VDD_SDIO power
domain
1, 3
-40-mA
-40-mA
-20-mA
I
OH
High-level source current
(VDD1= 3.3 V,
VOH>= 2.64 V,
output drive strength set
to the maximum)
Low-level sink current
I
OL
(VDD1= 3.3 V, VOL= 0.495 V,
-28-mA
output drive strength set to the maximum)
R
P U
R
P D
V
IL_nRS T
Notes:
1. Please see Appendix IO_MUX in ESP32 Datasheet for IO’s power domain. VDD is the I/O voltage for a particular power
domain of pins.
2. For VDD3P3_CPU and VDD3P3_RTC power domain, per-pin current sourced in the same domain is gradually reduced
from around 40 mA to around 29 mA, VOH>=2.64 V, as the number of current-source pins increases.
3. Pins occupied by flash and/or PSRAM in the VDD_SDIO power domain were excluded from the test.
Resistance of internal pull-up resistor-45-kΩ
Resistance of internal pull-down resistor-45-kΩ
Low-level input voltage of CHIP_PU
--0.6V
to power off the chip
6.4WiFi Radio
ParameterConditionMinTypicalMaxUnit
Operating frequency range
Output impedance
TX power
Sensitivity
Adjacent channel rejection
note3
note2
Table 8: WiFi Radio Characteristics
note1
-2412-2484MHz
--*-Ω
11n, MCS7121314dBm
11b mode18.519.520.5dBm
11b, 1 Mbps-–97-dBm
11b, 11 Mbps-–88-dBm
11g, 6 Mbps-–92-dBm
11g, 54 Mbps-–75-dBm
11n, HT20, MCS0-–92-dBm
11n, HT20, MCS7-–72-dBm
11n, HT40, MCS0-–89-dBm
11n, HT40, MCS7-–69-dBm
11g, 6 Mbps-27-dB
11g, 54 Mbps-13-dB
11n, HT20, MCS0-27-dB
11n, HT20, MCS7-12-dB
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6 Electrical Characteristics
Notes:
1. Device should operate in the frequency range allocated by regional regulatory authorities. Target operating frequency
range is configurable by software.
2. For the modules that use IPEX antennas, the output impedance is 50 Ω. For other modules without IPEX antennas,
users do not need to concern about the output impedance.
3. Target TX power is configurable based on device or certification requirements.
6.5BLE Radio
6.5.1Receiver
Table 9: Receiver Characteristics – BLE
ParameterConditionsMinTypMaxUnit
Sensitivity @30.8% PER-–94–93–92dBm
Maximum received signal @30.8% PER-0--dBm
Co-channel C/I--+10-dB
F = F0 + 1 MHz-–5-dB
F = F0 – 1 MHz-–5-dB
Adjacent channel selectivity C/I
Out-of-band blocking performance
Intermodulation-–36--dBm
F = F0 + 2 MHz-–25-dB
F = F0 – 2 MHz-–35-dB
F = F0 + 3 MHz-–25-dB
F = F0 – 3 MHz-–45-dB
30 MHz ~ 2000 MHz–10--dBm
2000 MHz ~ 2400 MHz–27--dBm
2500 MHz ~ 3000 MHz–27--dBm
3000 MHz ~ 12.5 GHz–10--dBm
6.5.2Transmitter
Table 10: Transmitter Characteristics – BLE
ParameterConditionsMinTypMaxUnit
RF transmit power--0-dBm
Gain control step--3-dBm
RF power control range-–12-+9dBm
F = F0 ± 2 MHz-–52-dBm
Adjacent channel transmit power
∆ f 1
avg
∆ f 2
max
∆ f 2
avg
/∆ f 1
avg
ICFT--–10-kHz
Drift rate--0.7-kHz/50 µs
Drift--2-kHz
F = F0 ± 3 MHz-–58-dBm
F = F0 ± > 3 MHz-–60-dBm
---265kHz
-247--kHz
--+0.92--
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6 Electrical Characteristics
50
150
0
25
1 ~ 3 ℃/s
0
200
250
200
–1 ~ –5 ℃/s
Cooling zone
100
217
50
100250
Reflow zone
217 ℃ 60 ~ 90 s
Temperature (℃)
Preheating zone
150 ~ 200 ℃ 60 ~ 120 s
Ramp-up zone
Peak Temp.
235 ~ 250 ℃
Soldering time
> 30 s
Time (sec.)
Ramp-up zone — Temp.: 25 ~ 150 ℃ Time: 60 ~ 90 s Ramp-up rate: 1 ~ 3 ℃/s
Preheating zone — Temp.: 150 ~ 200 ℃ Time: 60 ~ 120 s
Reflow zone — Temp.: >217 ℃60 ~ 90 s; Peak Temp.: 235 ~ 250 ℃ Time: 30 ~ 70 s
IO12 should be kept low when the module is powered on.
EN
SENSOR_VP
SENSOR_VN
IO34
IO35
IO32
IO33
IO25
IO26
IO27
IO14
IO13
IO22
TXD0
RXD0
IO21
IO19
IO18
IO4
IO0
IO5
IO23
IO15
IO2
IO12
ENIO14TMS
IO12TDI
IO13TCK
IO15TDO
GND
VDD33
GND
VDD33
GND
GND
GND
GND
GND
SW1
R1
TBD
R20R
JP2
Boot Option
112
2
C2
0.1uF
JP1
UART
1
1
2
2
3
3
4
4
JP3
JTAG
1
1
2
2
3
3
4
4
C3
TBD
U1
ESP32-WROVER-E/ESP32-WROVER-IE
GND1
1
3V3
2
EN
3
SENSOR_VP
4
SENSOR_VN
5
IO34
6
IO35
7
IO32
8
IO33
9
IO25
10
IO26
11
IO27
12
IO14
13
IO12
14
GND2
15
IO13
16
NC
17
NC
18
NC
19
NC
20
NC
21
NC
22
IO15
23
IO2
24
IO0
25
IO4
26
NC
27
NC
28
IO5
29
IO18
30
IO19
31
NC
32
IO21
33
RXD0
34
TXD0
35
IO22
36
IO23
37
GND3
38
P_GND
39
C40.1uF
C1
22uF
8Peripheral Schematics
This is the typical application circuit of the module connected with peripheral components (for example, power
supply, antenna, reset button, JTAG interface, and UART interface).
Figure 7: Peripheral Schematics
Note:
• Soldering Pad 39 to the Ground of the base board is not necessary for a satisfactory thermal performance. If users
do want to solder it, they need to ensure that the correct quantity of soldering paste is applied.
• To ensure the power supply to the ESP32 chip during power-up, it is advised to add an RC delay circuit at the EN pin.
The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 µF. However, specific parameters
should be adjusted based on the power-up timing of the module and the power-up and reset sequence timing
of the chip. For ESP32’s power-up and reset sequence timing diagram, please refer to Section Power Scheme in
ESP32 Datasheet.
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0.1
10.50
18.00±0.15
31.40±0.15
6.22
23.05
15.84
24.09
0.57
1.10
1.27
0.45
0.90
3.70
3.70
0.85
10.45
3.72
0.80
3.30±0.15
16.16
Top View
Side View
Bottom View
Unit: mm
6.22
2.25
0.50
0.50
0.90
0.85
0.90
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9 Physical Dimensions
9Physical Dimensions
ESP32-WROVER-E & ESP32-WROVER-IE Datasheet V1.4
Figure 8: Physical Dimensions
10 Recommended PCB Land Pattern
Unit: mm
Copper
Via for thermal pad
Antenna Area
1
19
20
38
38x1.50
38x0.90
18.00
31.40
1.27
1.10
6.22
0.50
22.86
3.70
0.90
0.50
3.70
0.90
0.50
16.16
7.50
10Recommended PCB Land Pattern
Figure 9: Recommended PCB Land Pattern
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11 U.FL Connector Dimensions
Unit: mm
11U.FL Connector Dimensions
Figure 10: U.FL Connector Dimensions
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12 Learning Resources
12Learning Resources
12.1MustRead Documents
The following link provides documents related to ESP32.
• ESP32 Datasheet
This document provides an introduction to the specifications of the ESP32 hardware, including overview,
pin definitions, functional description, peripheral interface, electrical characteristics, etc.
• ESP32 ECO V3 User Guide
This document describes differences between V3 and previous ESP32 silicon wafer revisions.
• ECO and Workarounds for Bugs in ESP32
This document details hardware errata and workarounds in the ESP32.
• ESP-IDF Programming Guide
It hosts extensive documentation for ESP-IDF ranging from hardware guides to API reference.
• ESP32 Technical Reference Manual
The manual provides detailed information on how to use the ESP32 memory and peripherals.
• ESP32 Hardware Resources
The zip files include the schematics, PCB layout, Gerber and BOM list of ESP32 modules and development
boards.
• ESP32 Hardware Design Guidelines
The guidelines outline recommended design practices when developing standalone or add-on systems
based on the ESP32 series of products, including the ESP32 chip, the ESP32 modules and development
boards.
• ESP32 AT Instruction Set and Examples
This document introduces the ESP32 AT commands, explains how to use them, and provides examples of
several common AT commands.
• Espressif Products Ordering Information
12.2MustHave Resources
Here are the ESP32-related must-have resources.
• ESP32 BBS
This is an Engineer-to-Engineer (E2E) Community for ESP32 where you can post questions, share
knowledge, explore ideas, and help solve problems with fellow engineers.
• ESP32 GitHub
ESP32 development projects are freely distributed under Espressif’s MIT license on GitHub. It is
established to help developers get started with ESP32 and foster innovation and the growth of general
knowledge about the hardware and software surrounding ESP32 devices.
• ESP32 Tools
This is a webpage where users can download ESP32 Flash Download Tools and the zip file ”ESP32
Certification and Test”.
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12 Learning Resources
• ESP-IDF
This webpage links users to the official IoT development framework for ESP32.
• ESP32 Resources
This webpage provides the links to all available ESP32 documents, SDK and tools.
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Revision History
Revision History
DateVersionRelease notes
2021-02-09V1.4
2021-02-02V1.3
2020-11-02V1.2
2020-06-11V1.1
Updated Figure 8: Physical Dimensions
Updated Figure 9: Recommended PCB Land Pattern
Updated the trade mark from TWAI™ to TWAI
Modified the note below Figure 4: Reow Prole
Deleted Reset Circuit and Discharge Circuit for VDD33 Rail in Section 8: Periph-
eral Schematics
Updated Figure 3.1: Pin Layout
Added a note to EPAD in Section 10: Recommended PCB Land Pattern
Updated the note to RC delay circuit in Section 8: Peripheral Schematics
Updated the following figures:
• Figure 1: ESP32-WROER-E Block Diagram
• Figure 2: ESP32-WROVER-IE Block Diagram
®
2020-05-22V1.0Official release
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www.espressif.com
Disclaimer and Copyright Notice
Information in this document, including URL references, is subject to change without notice.
ALL THIRD PARTY’S INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS WITH NO
WARRANTIES TO ITS AUTHENTICITY AND ACCURACY.
NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, NOR DOES ANY WARRANTY
OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
All liability, including liability for infringement of any proprietary rights, relating to use of information
in this document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any
intellectual property rights are granted herein.
The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a
registered trademark of Bluetooth SIG.
All trade names, trademarks and registered trademarks mentioned in this document are property
of their respective owners, and are hereby acknowledged.