ESP32
Technical Reference Manual
www.espressif.com
Version 4.0
Espressif Systems
Copyright © 2018
About This Manual
The ESP32 Technical Reference Manual is addressed to application developers. The manual provides detailed
and complete information on how to use the ESP32 memory and peripherals.
For pin definition, electrical characteristics and package information, please see ESP32 Datasheet.
Revision History
For any changes to this document over time, please refer to the last page.
Related Resources
Additional documentation and other resources about ESP32 can be accessed here: ESP32 Resources.
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Disclaimer and Copyright Notice
Information in this document, including URL references, is subject to change without notice. THIS DOCUMENT IS
PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABIL-
ITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE
ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
All liability, including liability for infringement of any proprietary rights, relating to the use of information in this doc-
ument, is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property rights
are granted herein. The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a
registered trademark of Bluetooth SIG.
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owners, and are hereby acknowledged.
Copyright © 2018 Espressif Inc. All rights reserved.
Contents
1 System and Memory 22
1.1 Introduction 22
1.2 Features 22
1.3 Functional Description 24
1.3.1 Address Mapping 24
1.3.2 Embedded Memory 24
1.3.2.1 Internal ROM 0 25
1.3.2.2 Internal ROM 1 25
1.3.2.3 Internal SRAM 0 26
1.3.2.4 Internal SRAM 1 26
1.3.2.5 Internal SRAM 2 27
1.3.2.6 DMA 27
1.3.2.7 RTC FAST Memory 27
1.3.2.8 RTC SLOW Memory 27
1.3.3 External Memory 27
1.3.4 Cache 28
1.3.5 Peripherals 29
1.3.5.1 Asymmetric PID Controller Peripheral 30
1.3.5.2 Non-Contiguous Peripheral Memory Ranges 30
1.3.5.3 Memory Speed 31
2 Interrupt Matrix 32
2.1 Overview 32
2.2 Features 32
2.3 Functional Description 32
2.3.1 Peripheral Interrupt Source 32
2.3.2 CPU Interrupt 35
2.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU 35
2.3.4 CPU NMI Interrupt Mask 36
2.3.5 Query Current Interrupt Status of Peripheral Interrupt Source 36
3 Reset and Clock 37
3.1 System Reset 37
3.1.1 Introduction 37
3.1.2 Reset Source 37
3.2 System Clock 38
3.2.1 Introduction 38
3.2.2 Clock Source 39
3.2.3 CPU Clock 39
3.2.4 Peripheral Clock 40
3.2.4.1 APB_CLK Source 40
3.2.4.2 REF_TICK Source 41
3.2.4.3 LEDC_SCLK Source 41
3.2.4.4 APLL_SCLK Source 41
3.2.4.5 PLL_D2_CLK Source 41
3.2.4.6 Clock Source Considerations 42
3.2.5 Wi-Fi BT Clock 42
3.2.6 RTC Clock 42
3.2.7 Audio PLL 42
4 IO_MUX and GPIO Matrix 44
4.1 Overview 44
4.2 Peripheral Input via GPIO Matrix 45
4.2.1 Summary 45
4.2.2 Functional Description 45
4.2.3 Simple GPIO Input 46
4.3 Peripheral Output via GPIO Matrix 46
4.3.1 Summary 46
4.3.2 Functional Description 47
4.3.3 Simple GPIO Output 48
4.4 Direct I/O via IO_MUX 48
4.4.1 Summary 48
4.4.2 Functional Description 48
4.5 RTC IO_MUX for Low Power and Analog I/O 48
4.5.1 Summary 48
4.5.2 Functional Description 49
4.6 Light-sleep Mode Pin Functions 49
4.7 Pad Hold Feature 49
4.8 I/O Pad Power Supplies 50
4.8.1 VDD_SDIO Power Domain 51
4.9 Peripheral Signal List 51
4.10 IO_MUX Pad List 56
4.11 RTC_MUX Pin List 57
4.12 Register Summary 57
4.13 Registers 61
5 DPort Register 84
5.1 Introduction 84
5.2 Features 84
5.3 Functional Description 84
5.3.1 System and Memory Register 84
5.3.2 Reset and Clock Registers 84
5.3.3 Interrupt Matrix Register 85
5.3.4 DMA Registers 89
5.3.5 PID/MPU/MMU Registers 89
5.3.6 APP_CPU Controller Registers 92
5.3.7 Peripheral Clock Gating and Reset 92
5.4 Register Summary 95
5.5 Registers 101
6 DMA Controller 115
6.1 Overview 115
6.2 Features 115
6.3 Functional Description 115
6.3.1 DMA Engine Architecture 115
6.3.2 Linked List 116
6.4 UART DMA (UDMA) 117
6.5 SPI DMA Interface 118
6.6 I2S DMA Interface 119
7 SPI 120
7.1 Overview 120
7.2 SPI Features 120
7.3 GP-SPI 121
7.3.1 GP-SPI Four-line Full-duplex Communication 122
7.3.2 GP-SPI Four-line Half-duplex Communication 122
7.3.3 GP-SPI Three-line Half-duplex Communication 123
7.3.4 GP-SPI Data Buffer 123
7.4 GP-SPI Clock Control 124
7.4.1 GP-SPI Clock Polarity (CPOL) and Clock Phase (CPHA) 124
7.4.2 GP-SPI Timing 125
7.5 Parallel QSPI 126
7.5.1 Communication Format of Parallel QSPI 126
7.6 GP-SPI Interrupt Hardware 127
7.6.1 SPI Interrupts 127
7.6.2 DMA Interrupts 127
7.7 Register Summary 128
7.8 Registers 131
8 SDIO Slave 153
8.1 Overview 153
8.2 Features 153
8.3 Functional Description 153
8.3.1 SDIO Slave Block Diagram 153
8.3.2 Sending and Receiving Data on SDIO Bus 154
8.3.3 Register Access 154
8.3.4 DMA 155
8.3.5 Packet-Sending/-Receiving Procedure 156
8.3.5.1 Sending Packets to SDIO Host 156
8.3.5.2 Receiving Packets from SDIO Host 157
8.3.6 SDIO Bus Timing 158
8.3.7 Interrupt 159
8.3.7.1 Host Interrupt 159
8.3.7.2 Slave Interrupt 159
8.4 Register Summary 160
8.5 SLC Registers 162
8.6 SLC Host Registers 170
8.7 HINF Registers 184
9 SD/MMC Host Controller 185
9.1 Overview 185
9.2 Features 185
9.3 SD/MMC External Interface Signals 185
9.4 Functional Description 186
9.4.1 SD/MMC Host Controller Architecture 186
9.4.1.1 BIU 187
9.4.1.2 CIU 187
9.4.2 Command Path 188
9.4.3 Data Path 188
9.4.3.1 Data Transmit Operation 188
9.4.3.2 Data Receive Operation 189
9.5 Software Restrictions for Proper CIU Operation 189
9.6 RAM for Receiving and Sending Data 191
9.6.1 Transmit RAM Module 191
9.6.2 Receive RAM Module 191
9.7 Descriptor Chain 191
9.8 The Structure of a Linked List 191
9.9 Initialization 193
9.9.1 DMAC Initialization 194
9.9.2 DMAC Transmission Initialization 194
9.9.3 DMAC Reception Initialization 194
9.10 Clock Phase Selection 195
9.11 Interrupt 196
9.12 Register Summary 196
9.13 Registers 198
10 Ethernet MAC 216
10.1 Overview 216
10.2 EMAC_CORE 218
10.2.1 Transmit Operation 218
10.2.1.1 Transmit Flow Control 219
10.2.1.2 Retransmission During a Collision 219
10.2.2 Receive Operation 219
10.2.2.1 Reception Protocol 220
10.2.2.2 Receive Frame Controller 220
10.2.2.3 Receive Flow Control 220
10.2.2.4 Reception of Multiple Frames 221
10.2.2.5 Error Handling 221
10.2.2.6 Receive Status Word 221
10.3 MAC Interrupt Controller 221
10.4 MAC Address Filtering 222
10.4.1 Unicast Destination Address Filtering 222
10.4.2 Multicast Destination Address Filtering 222
10.4.3 Broadcast Address Filtering 222
10.4.4 Unicast Source Address Filtering 222
10.4.5 Inverse Filtering Operation 223
10.4.6 Good Transmitted Frames and Received Frames 224
10.5 EMAC_MTL (MAC Transaction Layer) 225
10.6 PHY Interface 225
10.6.1 MII (Media Independent Interface) 225
10.6.1.1 Interface Signals Between MII and PHY 225
10.6.1.2 MII Clock 226
10.6.2 RMII (Reduced Media-Independent Interface) 227
10.6.2.1 RMII Interface Signal Description 227
10.6.2.2 RMII Clock 228
10.6.3 Station Management Agent (SMA) Interface 228
10.7 Ethernet DMA Features 228
10.8 Linked List Descriptors 229
10.8.1 Transmit Descriptors 229
10.8.2 Receive Descriptors 235
10.9 Register Summary 240
10.10Registers 242
11 I²C Controller 280
11.1 Overview 280
11.2 Features 280
11.3 Functional Description 280
11.3.1 Introduction 280
11.3.2 Architecture 281
11.3.3 I²C Bus Timing 282
11.3.4 I²C cmd Structure 282
11.3.5 I²C Master Writes to Slave 283
11.3.6 Master Reads from Slave 287
11.3.7 Interrupts 289
11.4 Register Summary 290
11.5 Registers 292
12 I2S 303
12.1 Overview 303
12.2 Features 304
12.3 The Clock of I2S Module 305
12.4 I2S Mode 306
12.4.1 Supported Audio Standards 306
12.4.1.1 Philips Standard 306
12.4.1.2 MSB Alignment Standard 306
12.4.1.3 PCM Standard 307
12.4.2 Module Reset 307
12.4.3 FIFO Operation 307
12.4.4 Sending Data 308
12.4.5 Receiving Data 309
12.4.6 I2S Master/Slave Mode 311
12.4.7 I2S PDM 311
12.5 LCD Mode 313
12.5.1 LCD Master Transmitting Mode 313
12.5.2 Camera Slave Receiving Mode 314
12.5.3 ADC/DAC mode 315
12.6 I2S Interrupts 316
12.6.1 FIFO Interrupts 316
12.6.2 DMA Interrupts 316
12.7 Register Summary 317
12.8 Registers 319
13 UART Controllers 337
13.1 Overview 337
13.2 UART Features 337
13.3 Functional Description 337
13.3.1 Introduction 337
13.3.2 UART Architecture 338
13.3.3 UART RAM 339
13.3.4 Baud Rate Detection 339
13.3.5 UART Data Frame 340
13.3.6 Flow Control 341
13.3.6.1 Hardware Flow Control 341
13.3.6.2 Software Flow Control 342
13.3.7 UART DMA 342
13.3.8 UART Interrupts 342
13.3.9 UHCI Interrupts 343
13.4 Register Summary 344
13.4.1 UART Registers 344
13.4.2 UHCI Registers 345
13.5 Registers 347
14 LED_PWM 378
14.1 Introduction 378
14.2 Functional Description 378
14.2.1 Architecture 378
14.2.2 Timers 378
14.2.3 Channels 380
14.2.4 Interrupts 381
14.3 Register Summary 381
14.4 Registers 384
15 Remote Control Peripheral 394
15.1 Introduction 394
15.2 Functional Description 394
15.2.1 RMT Architecture 394
15.2.2 RMT RAM 395
15.2.3 Clock 395
15.2.4 Transmitter 396
15.2.5 Receiver 396
15.2.6 Interrupts 396
15.3 Register Summary 396
15.4 Registers 398
16 MCPWM 403
16.1 Introduction 403
16.2 Features 403
16.3 Submodules 405
16.3.1 Overview 405
16.3.1.1 Prescaler Submodule 405
16.3.1.2 Timer Submodule 405
16.3.1.3 Operator Submodule 406
16.3.1.4 Fault Detection Submodule 408
16.3.1.5 Capture Submodule 408
16.3.2 PWM Timer Submodule 408
16.3.2.1 Configurations of the PWM Timer Submodule 408
16.3.2.2 PWM Timer’s Working Modes and Timing Event Generation 409
16.3.2.3 PWM Timer Shadow Register 413
16.3.2.4 PWM Timer Synchronization and Phase Locking 413
16.3.3 PWM Operator Submodule 413
16.3.3.1 PWM Generator Submodule 414
16.3.3.2 Dead Time Generator Submodule 424
16.3.3.3 PWM Carrier Submodule 428
16.3.3.4 Fault Handler Submodule 430
16.3.4 Capture Submodule 432
16.3.4.1 Introduction 432
16.3.4.2 Capture Timer 432
16.3.4.3 Capture Channel 432
16.4 Register Summary 433
16.5 Registers 435
17 PULSE_CNT 482
17.1 Overview 482
17.2 Functional Description 482
17.2.1 Architecture 482
17.2.2 Counter Channel Inputs 482
17.2.3 Watchpoints 483
17.2.4 Examples 484
17.2.5 Interrupts 484
17.3 Register Summary 484
17.4 Registers 486
18 64-bit Timers 490
18.1 Introduction 490
18.2 Functional Description 490
18.2.1 16-bit Prescaler 490
18.2.2 64-bit Time-base Counter 490
18.2.3 Alarm Generation 491
18.2.4 MWDT 491
18.2.5 Interrupts 491
18.3 Register Summary 491
18.4 Registers 493
19 Watchdog Timers 500
19.1 Introduction 500
19.2 Features 500
19.3 Functional Description 500
19.3.1 Clock 500
19.3.1.1 Operating Procedure 501
19.3.1.2 Write Protection 501
19.3.1.3 Flash Boot Protection 501
19.3.1.4 Registers 502
20 eFuse Controller 503
20.1 Introduction 503
20.2 Features 503
20.3 Functional Description 503
20.3.1 Structure 503
20.3.1.1 System Parameter efuse_wr_disable 504
20.3.1.2 System Parameter efuse_rd_disable 505
20.3.1.3 System Parameter coding_scheme 505
20.3.1.4 BLK3_part_reserve 506
20.3.2 Programming of System Parameters 506
20.3.3 Software Reading of System Parameters 509
20.3.4 The Use of System Parameters by Hardware Modules 510
20.3.5 Interrupts 511
20.4 Register Summary 511
20.5 Registers 513
21 AES Accelerator 523
21.1 Introduction 523
21.2 Features 523
21.3 Functional Description 523
21.3.1 AES Algorithm Operations 523
21.3.2 Key, Plaintext and Ciphertext 523
21.3.3 Endianness 524
21.3.4 Encryption and Decryption Operations 526
21.3.5 Speed 526
21.4 Register Summary 526
21.5 Registers 528
22 SHA Accelerator 530
22.1 Introduction 530
22.2 Features 530
22.3 Functional Description 530
22.3.1 Padding and Parsing the Message 530
22.3.2 Message Digest 530
22.3.3 Hash Operation 531
22.3.4 Speed 531
22.4 Register Summary 531
22.5 Registers 533
23 RSA Accelerator 538
23.1 Introduction 538
23.2 Features 538
23.3 Functional Description 538
23.3.1 Initialization 538
23.3.2 Large Number Modular Exponentiation 538
23.3.3 Large Number Modular Multiplication 540
23.3.4 Large Number Multiplication 540
23.4 Register Summary 541
23.5 Registers 542
24 Random Number Generator 544
24.1 Introduction 544
24.2 Feature 544
24.3 Functional Description 544
24.4 Register Summary 544
24.5 Register 544
25 Flash Encryption/Decryption 545
25.1 Overview 545
25.2 Features 545
25.3 Functional Description 545
25.3.1 Key Generator 546
25.3.2 Flash Encryption Block 546
25.3.3 Flash Decryption Block 547
25.4 Register Summary 547
25.5 Register 549
26 PID/MPU/MMU 550
26.1 Introduction 550
26.2 Features 550
26.3 Functional Description 550
26.3.1 PID Controller 550
26.3.2 MPU/MMU 551
26.3.2.1 Embedded Memory 551
26.3.2.2 External Memory 557
26.3.2.3 Peripheral 563
27 PID Controller 565
27.1 Overview 565
27.2 Features 565
27.3 Functional Description 565
27.3.1 Interrupt Identification 566
27.3.2 Information Recording 566
27.3.3 Proactive Process Switching 568
27.4 Register Summary 570
27.5 Registers 571
28 On-Chip Sensors and Analog Signal Processing 575
28.1 Introduction 575
28.2 Capacitive Touch Sensor 575
28.2.1 Introduction 575
28.2.2 Features 575
28.2.3 Available GPIOs 576
28.2.4 Functional Description 576
28.2.5 Touch FSM 577
28.3 SAR ADC 578
28.3.1 Introduction 578
28.3.2 Features 579
28.3.3 Outline of Function 579
28.3.4 RTC SAR ADC Controllers 580
28.3.5 DIG SAR ADC Controllers 581
28.4 Hall Sensor 583
28.4.1 Introduction 583
28.4.2 Features 583
28.4.3 Functional Description 584
28.5 DAC 584
28.5.1 Introduction 584
28.5.2 Features 584
28.5.3 Structure 585
28.5.4 Cosine Waveform Generator 585
28.5.5 DMA support 586
28.6 Register Summary 587
28.6.1 Sensors 587
28.6.2 Advanced Peripheral Bus 587
28.6.3 RTC I/O 588
28.7 Registers 589
28.7.1 Sensors 589
28.7.2 Advanced Peripheral Bus 599
28.7.3 RTC I/O 602
29 ULP Co-processor 603
29.1 Introduction 603
29.2 Features 603
29.3 Functional Description 604
29.4 Instruction Set 604
29.4.1 ALU - Perform Arithmetic/Logic Operations 605
29.4.1.1 Operations Among Registers 605
29.4.1.2 Operations with Immediate Value 606
29.4.1.3 Operations with Stage Count Register 606
29.4.2 ST – Store Data in Memory 607
29.4.3 LD – Load Data from Memory 607
29.4.4 JUMP – Jump to an Absolute Address 608
29.4.5 JUMPR – Jump to a Relative Offset (Conditional upon R0) 608
29.4.6 JUMPS – Jump to a Relative Address (Conditional upon Stage Count Register) 609
29.4.7 HALT – End the Program 609
29.4.8 WAKE – Wake up the Chip 609
29.4.9 Sleep – Set the ULP Timer’s Wake-up Period 610
29.4.10 WAIT – Wait for a Number of Cycles 610
29.4.11 ADC – Take Measurement with ADC 610
29.4.12 I2C_RD/I2C_WR – Read/Write I²C 611
29.4.13 REG_RD – Read from Peripheral Register 612
29.4.14 REG_WR – Write to Peripheral Register 612
29.5 ULP Program Execution 613
29.6 RTC_I2C Controller 614
29.6.1 Configuring RTC_I2C 615
29.6.2 Using RTC_I2C 615
29.6.2.1 I2C_RD - Read a Single Byte 615
29.6.2.2 I2C_WR - Write a Single Byte 616
29.6.2.3 Detecting Error Conditions 616
29.6.2.4 Connecting I²C Signals 617
29.7 Register Summary 617
29.7.1 SENS_ULP Address Space 617
29.7.2 RTC_I2C Address Space 617
29.8 Registers 619
29.8.1 SENS_ULP Address Space 619
29.8.2 RTC_I2C Address Space 621
30 Low-Power Management 628
30.1 Introduction 628
30.2 Features 628
30.3 Functional Description 629
30.3.1 Overview 629
30.3.2 Digital Core Voltage Regulator 629
30.3.3 Low-Power Voltage Regulator 629
30.3.4 Flash Voltage Regulator 630
30.3.5 Brownout Detector 631
30.3.6 RTC Module 631
30.3.7 Low-Power Clocks 633
30.3.8 Power-Gating Implementation 634
30.3.9 Predefined Power Modes 635
30.3.10 Wakeup Source 637
30.3.11 RTC Timer 638
30.3.12 RTC Boot 638
30.4 Register Summary 639
30.5 Registers 642
Revision History 667
List of Tables
1 Address Mapping 24
2 Embedded Memory Address Mapping 25
3 Module with DMA 27
4 External Memory Address Mapping 28
5 Cache memory mode 28
6 Peripheral Address Mapping 29
7 PRO_CPU, APP_CPU Interrupt Configuration 33
8 CPU Interrupts 35
9 PRO_CPU and APP_CPU Reset Reason Values 37
10 CPU_CLK Source 39
11 CPU_CLK Derivation 40
12 Peripheral Clock Usage 40
13 APB_CLK Derivation 41
14 REF_TICK Derivation 41
15 LEDC_SCLK Derivation 41
16 IO_MUX Light-sleep Pin Function Registers 49
17 GPIO Matrix Peripheral Signals 51
18 IO_MUX Pad Summary 56
19 RTC_MUX Pin Summary 57
25 Mapping Between SPI Bus Signals and Pin Function Signals 120
26 Command Definitions Supported by GP-SPI Slave in Half-duplex Mode 122
27 Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Master 124
28 Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Slave 124
33 SD/MMC Signal Description 186
34 DES0 192
35 DES1 193
36 DES2 193
37 DES3 193
39 Destination Address Filtering 223
40 Source Address Filtering 224
41 Transmit Descriptor 0 (TDES0) 229
42 Transmit Descriptor 1 (TDES1) 233
43 Transmit Descriptor 2 (TDES2) 233
44 Transmit Descriptor 3 (TDES3) 233
45 Transmit Descriptor 6 (TDES6) 233
46 Transmit Descriptor 7 (TDES7) 234
47 Receive Descriptor 0 (RDES0) 235
48 Receive Descriptor 1 (RDES1) 237
49 Receive Descriptor 2 (RDES2) 238
50 Receive Descriptor 3 (RDES3) 238
51 Receive Descriptor 4 (RDES4) 238
52 Receive Descriptor 6 (RDES6) 240
53 Receive Descriptor 7 (RDES7) 240
55 SCL Frequency Configuration 282
57 I2S Signal Bus Description 304
58 Register Configuration 308
59 Send Channel Mode 308
60 Modes of Writing Received Data into FIFO and the Corresponding Register Configuration 310
61 The Register Configuration to Which the Four Modes Correspond 310
62 Upsampling Rate Configuration 312
63 Down-sampling Configuration 313
69 Configuration Parameters of the Operator Submodule 407
70 Timing Events Used in PWM Generator 415
71 Timing Events Priority When PWM Timer Increments 415
72 Timing Events Priority when PWM Timer Decrements 416
73 Dead Time Generator Switches Control Registers 425
74 Typical Dead Time Generator Operating Modes 426
79 System Parameter 503
80 BLOCK1/2/3 Encoding 505
81 Program Register 507
82 Timing Configuration 508
83 Software Read Register 509
85 Operation Mode 523
86 AES Text Endianness 524
87 AES-128 Key Endianness 525
88 AES-192 Key Endianness 525
89 AES-256 Key Endianness 525
95 MPU and MMU Structure for Internal Memory 551
96 MPU for RTC FAST Memory 552
97 MPU for RTC SLOW Memory 552
98 Page Mode of MMU for the Remaining 128 KB of Internal SRAM0 and SRAM2 553
99 Page Boundaries for SRAM0 MMU 554
100 Page Boundaries for SRAM2 MMU 554
101 DPORT_DMMU_TABLEn_REG & DPORT_IMMU_TABLEn_REG 555
102 MPU for DMA 556
103 Virtual Address for External Memory 558
104 MMU Entry Numbers for PRO_CPU 558
105 MMU Entry Numbers for APP_CPU 558
106 MMU Entry Numbers for PRO_CPU (Special Mode) 559
107 MMU Entry Numbers for APP_CPU (Special Mode) 559
108 Virtual Address Mode for External SRAM 560
109 Virtual Address for External SRAM ( Normal Mode ) 561
110 Virtual Address for External SRAM ( Low-High Mode ) 561
111 Virtual Address for External SRAM ( Even-Odd Mode ) 561
112 MMU Entry Numbers for External RAM 562
113 MPU for Peripheral 563
114 DPORT_AHBLITE_MPU_TABLE_X_REG 564
115 Interrupt Vector Entry Address 566
116 Configuration of PIDCTRL_LEVEL_REG 566
117 Configuration of PIDCTRL_FROM_n_REG 567
119 ESP32 Capacitive Sensing Touch Pads 576
120 Inputs of SAR ADC module 579
121 ESP32 SAR ADC Controllers 580
122 Fields of the Pattern Table Register 582
123 Fields of Type I DMA Data Format 583
124 Fields of Type II DMA Data Format 583
127 ALU Operations Among Registers 605
128 ALU Operations with Immediate Value 606
129 ALU Operations with Stage Count Register 607
131 Input Signals Measured Using the ADC Instruction 611
135 RTC Power Domains 635
136 Wake-up Source 637
List of Figures
1 System Structure 23
2 System Address Mapping 23
3 Cache Block Diagram 28
4 Interrupt Matrix Structure 32
5 System Reset 37
6 System Clock 38
7 IO_MUX, RTC IO_MUX and GPIO Matrix Overview 44
8 Peripheral Input via IO_MUX, GPIO Matrix 45
9 Output via GPIO Matrix 47
10 ESP32 I/O Pad Power Sources (QFN 6*6, Top View) 50
11 ESP32 I/O Pad Power Sources (QFN 5*5, Top View) 50
12 DMA Engine Architecture 115
13 Linked List Structure 116
14 Data Transfer in UDMA Mode 117
15 SPI DMA 118
16 SPI Architecture 120
17 SPI Master and Slave Full-duplex/Half-duplex Communication 121
18 SPI Data Buffer 123
19 GP-SPI ������ 126
20 Parallel QSPI 126
21 Communication Format of Parallel QSPI 127
22 SDIO Slave Block Diagram 153
23 SDIO Bus Packet Transmission 154
24 CMD53 Content 154
25 SDIO Slave DMA Linked List Structure 155
26 SDIO Slave Linked List 155
27 Packet Sending Procedure (Initiated by Slave) 156
28 Packet Receiving Procedure (Initiated by Host) 157
29 Loading Receiving Buffer 158
30 Sampling Timing Diagram 158
31 Output Timing Diagram 159
32 SD/MMC Controller Topology 185
33 SD/MMC Controller External Interface Signals 186
34 SDIO Host Block Diagram 187
35 Command Path State Machine 188
36 Data Transmit State Machine 189
37 Data Receive State Machine 189
38 Descriptor Chain 191
39 The Structure of a Linked List 192
40 Clock Phase Selection 195
41 Ethernet MAC Functionality Overview 216
42 Ethernet Block Diagram 218
43 MII Interface 225
44 MII Clock 227
45 RMII Interface 227
46 RMII Clock 228
47 Transmit Descriptor 229
48 Receive Descriptor 235
49 IC Master Architecture 281
50 IC Slave Architecture 281
51 IC Sequence Chart 282
52 Structure of The IC Command Register 283
53 IC Master Writes to Slave with 7-bit Address 284
54 IC Master Writes to Slave with 10-bit Address 285
55 IC Master Writes to addrM in RAM of Slave with 7-bit Address 286
56 Master Writes to Slave with 7-bit Address in Three Segments 286
57 Master Reads from Slave with 7-bit Address 287
58 Master Reads from Slave with 10-bit Address 288
59 Master Reads N Bytes of Data from addrM in Slave with 7-bit Address 288
60 Master Reads from Slave with 7-bit Address in Three Segments 289
61 I2S System Block Diagram 303
62 I2S Clock 305
63 Philips Standard 306
64 MSB Alignment Standard 306
65 PCM Standard 307
66 Tx FIFO Data Mode 308
67 The First Stage of Receiving Data 309
68 Modes of Writing Received Data into FIFO 310
69 PDM Transmitting Module 311
70 PDM Sends Signal 312
71 PDM Receives Signal 312
72 PDM Receive Module 313
73 LCD Master Transmitting Mode 313
74 LCD Master Transmitting Data Frame, Form 1 314
75 LCD Master Transmitting Data Frame, Form 2 314
76 Camera Slave Receiving Mode 314
77 ADC Interface of I2S0 315
78 DAC Interface of I2S 315
79 Data Input by I2S DAC Interface 315
80 UART Basic Structure 338
81 UART Shared RAM 339
82 UART Data Frame Structure 340
83 AT_CMD Character Format 340
84 Hardware Flow Control 341
85 LED_PWM Architecture 378
86 LED_PWM High-speed Channel Diagram 379
87 LED_PWM Divider 379
88 LED PWM Output Signal Diagram 380
89 Output Signal Diagram of Fading Duty Cycle 380
90 RMT Architecture 394
91 Data Structure 395
92 MCPWM Module Overview 403
93 Prescaler Submodule 405
94 Timer Submodule 405
95 Operator Submodule 406
96 Fault Detection Submodule 408
97 Capture Submodule 408
98 Count-Up Mode Waveform 409
99 Count-Down Mode Waveforms 410
100 Count-Up-Down Mode Waveforms, Count-Down at Synchronization Event 410
101 Count-Up-Down Mode Waveforms, Count-Up at Synchronization Event 410
102 UTEP and UTEZ Generation in Count-Up Mode 411
103 DTEP and DTEZ Generation in Count-Down Mode 412
104 DTEP and UTEZ Generation in Count-Up-Down Mode 412
105 Submodules Inside the PWM Operator 414
106 Symmetrical Waveform in Count-Up-Down Mode 417
107 Count-Up, Single Edge Asymmetric Waveform, with Independent Modulation on PWMxA and PWMxB
— Active High 418
108 Count-Up, Pulse Placement Asymmetric Waveform with Independent Modulation on PWMxA 419
109 Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA and
PWMxB — Active High 420
110 Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA and
PWMxB — Complementary 421
111 Example of an NCI Software-Force Event on PWMxA 422
112 Example of a CNTU Software-Force Event on PWMxB 423
113 Options for Setting up the Dead Time Generator Submodule 425
114 Active High Complementary (AHC) Dead Time Waveforms 426
115 Active Low Complementary (ALC) Dead Time Waveforms 427
116 Active High (AH) Dead Time Waveforms 427
117 Active Low (AL) Dead Time Waveforms 427
118 Example of Waveforms Showing PWM Carrier Action 429
119 Example of the First Pulse and the Subsequent Sustaining Pulses of the PWM Carrier Submodule 430
120 Possible Duty Cycle Settings for Sustaining Pulses in the PWM Carrier Submodule 430
121 PULSE_CNT Architecture 482
122 PULSE_CNT Upcounting Diagram 484
123 PULSE_CNT Downcounting Diagram 484
124 Flash Encryption/Decryption Module Architecture 545
125 MMU Access Example 553
126 Interrupt Nesting 568
127 Touch Sensor 575
128 Touch Sensor Structure 576
129 Touch Sensor Operating Flow 577
130 Touch FSM Structure 578
131 SAR ADC Depiction 578
132 SAR ADC Outline of Function 579
133 RTC SAR ADC Outline of Function 581
134 Diagram of DIG SAR ADC Controllers 582
135 Hall Sensor 584
136 Diagram of DAC Function 585
137 Cosine Waveform (CW) Generator 586
138 ULP Co-processor Diagram 603
139 The ULP Co-processor Instruction Format 604
140 Instruction Type — ALU for Operations Among Registers 605
141 Instruction Type — ALU for Operations with Immediate Value 606
142 Instruction Type — ALU for Operations with Stage Count Register 606
143 Instruction Type — ST 607
144 Instruction Type — LD 607
145 Instruction Type — JUMP 608
146 Instruction Type — JUMPR 608
147 Instruction Type — JUMP 609
148 Instruction Type — HALT 609
149 Instruction Type — WAKE 609
150 Instruction Type — SLEEP 610
151 Instruction Type — WAIT 610
152 Instruction Type — ADC 610
153 Instruction Type — I²C 611
154 Instruction Type — REG_RD 612
155 Instruction Type — REG_WR 612
156 Control of ULP Program Execution 613
157 Sample of a ULP Operation Sequence 614
158 I²C Read Operation 616
159 I²C Write Operation 616
160 ESP32 Power Control 628
161 Digital Core Voltage Regulator 629
162 Low-Power Voltage Regulator 630
163 Flash Voltage Regulator 631
164 Brownout Detector 631
165 RTC Structure 633
166 RTC Low-Power Clocks 634
167 Digital Low-Power Clocks 634
168 RTC States 634
169 Power Modes 637
170 ESP32 Boot Flow 639
1. System and Memory
1. System and Memory
1.1 Introduction
The ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs. All embedded memory,
external memory and peripherals are located on the data bus and/or the instruction bus of these CPUs.
With some minor exceptions (see below), the address mapping of two CPUs is symmetric, meaning that they use
the same addresses to access the same memory. Multiple peripherals in the system can access embedded
memory via DMA.
The two CPUs are named “PRO_CPU” and “APP_CPU” (for “protocol” and “application”), however, for most
purposes the two CPUs are interchangeable.
1.2 Features
• Address Space
– Symmetric address mapping
– 4 GB (32-bit) address space for both data bus and instruction bus
– 1296 KB embedded memory address space
– 19704 KB external memory address space
– 512 KB peripheral address space
– Some embedded and external memory regions can be accessed by either data bus or instruction bus
– 328 KB DMA address space
• Embedded Memory
– 448 KB Internal ROM
– 520 KB Internal SRAM
– 8 KB RTC FAST Memory
– 8 KB RTC SLOW Memory
• External Memory
Off-chip SPI memory can be mapped into the available address space as external memory. Parts of the
embedded memory can be used as transparent cache for this external memory.
– Supports up to 16 MB off-Chip SPI Flash.
– Supports up to 8 MB off-Chip SPI SRAM.
• Peripherals
– 41 peripherals
• DMA
– 13 modules are capable of DMA operation
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1. System and Memory
The block diagram in Figure 1 illustrates the system structure, and the block diagram in Figure 2 illustrates the
address map structure.
Figure 1: System Structure
Figure 2: System Address Mapping
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1. System and Memory
1.3 Functional Description
1.3.1 Address Mapping
Each of the two Harvard Architecture Xtensa LX6 CPUs has 4 GB (32-bit) address space. Address spaces are
symmetric between the two CPUs.
Addresses below 0x4000_0000 are serviced using the data bus. Addresses in the range 0x4000_0000 ~
0x4FFF_FFFF are serviced using the instruction bus. Finally, addresses over and including 0x5000_0000 are
shared by the data and instruction bus.
The data bus and instruction bus are both little-endian: for example, byte addresses 0x0, 0x1, 0x2, 0x3 access
the least significant, second least significant, second most significant, and the most significant bytes of the 32-bit
word stored at the 0x0 address, respectively. The CPU can access data bus addresses via aligned or non-aligned
byte, half-word and word read-and-write operations. The CPU can read and write data through the instruction
bus, but only in a word aligned manner; non-word-aligned access will cause a CPU exception.
Each CPU can directly access embedded memory through both the data bus and the instruction bus, external
memory which is mapped into the address space (via transparent caching & MMU), and peripherals. Table 1
illustrates address ranges that can be accessed by each CPU’s data bus and instruction bus.
Some embedded memories and some external memories can be accessed via the data bus or the instruction
bus. In these cases, the same memory is available to either of the CPUs at two address ranges.
Table 1: Address Mapping
Bus Type
Data 0x3F40_0000 0x3F7F_FFFF 4 MB External Memory
Data 0x3F80_0000 0x3FBF_FFFF 4 MB External Memory
Data 0x3FF0_0000 0x3FF7_FFFF 512 KB Peripheral
Data 0x3FF8_0000 0x3FFF_FFFF 512 KB Embedded Memory
Instruction 0x4000_0000 0x400C_1FFF 776 KB Embedded Memory
Instruction 0x400C_2000 0x40BF_FFFF 11512 KB External Memory
Data Instruction 0x5000_0000 0x5000_1FFF 8 KB Embedded Memory
Low Address High Address
0x0000_0000 0x3F3F_FFFF Reserved
0x3FC0_0000 0x3FEF_FFFF 3 MB Reserved
0x40C0_0000 0x4FFF_FFFF 244 MB Reserved
0x5000_2000 0xFFFF_FFFF Reserved
Boundary Address
Size Target
1.3.2 Embedded Memory
The Embedded Memory consists of four segments: internal ROM (448 KB), internal SRAM (520 KB), RTC FAST
memory (8 KB) and RTC SLOW memory (8 KB).
The 448 KB internal ROM is divided into two parts: Internal ROM 0 (384 KB) and Internal ROM 1 (64 KB). The
520 KB internal SRAM is divided into three parts: Internal SRAM 0 (192 KB), Internal SRAM 1 (128 KB), and
Internal SRAM 2 (200 KB). RTC FAST Memory and RTC SLOW Memory are both implemented as SRAM.
Table 2 lists all embedded memories and their address ranges on the data and instruction buses.
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1. System and Memory
Table 2: Embedded Memory Address Mapping
Bus Type
Data 0x3FF8_0000 0x3FF8_1FFF 8 KB RTC FAST Memory PRO_CPU Only
Data 0x3FF9_0000 0x3FF9_FFFF 64 KB Internal ROM 1 -
Data 0x3FFA_E000 0x3FFD_FFFF 200 KB Internal SRAM 2 DMA
Data 0x3FFE_0000 0x3FFF_FFFF 128 KB Internal SRAM 1 DMA
Bus Type
Instruction 0x4000_0000 0x4000_7FFF 32 KB Internal ROM 0 Remap
Instruction 0x4000_8000 0x4005_FFFF 352 KB Internal ROM 0 -
Instruction 0x4007_0000 0x4007_FFFF 64 KB Internal SRAM 0 Cache
Instruction 0x4008_0000 0x4009_FFFF 128 KB Internal SRAM 0 -
Instruction 0x400A_0000 0x400A_FFFF 64 KB Internal SRAM 1 -
Instruction 0x400B_0000 0x400B_7FFF 32 KB Internal SRAM 1 Remap
Instruction 0x400B_8000 0x400B_FFFF 32 KB Internal SRAM 1 -
Instruction 0x400C_0000 0x400C_1FFF 8 KB RTC FAST Memory PRO_CPU Only
Bus Type
Data Instruc-
tion
Low Address High Address
0x3FF8_2000 0x3FF8_FFFF 56 KB Reserved -
0x3FFA_0000 0x3FFA_DFFF 56 KB Reserved -
Low Address High Address
0x4006_0000 0x4006_FFFF 64 KB Reserved -
Low Address High Address
0x5000_0000 0x5000_1FFF 8 KB RTC SLOW Memory -
Boundary Address
Boundary Address
Boundary Address
Size Target Comment
Size Target Comment
Size Target Comment
1.3.2.1 Internal ROM 0
The capacity of Internal ROM 0 is 384 KB. It is accessible by both CPUs through the address range
0x4000_0000 ~ 0x4005_FFFF, which is on the instruction bus.
The address range of the first 32 KB of the ROM 0 (0x4000_0000 ~ 0x4000_7FFF) can be remapped in order to
access a part of Internal SRAM 1 that normally resides in a memory range of 0x400B_0000 ~ 0x400B_7FFF.
While remapping, the 32 KB SRAM cannot be accessed by an address range of 0x400B_0000 ~ 0x400B_7FFF
any more, but it can still be accessible through the data bus (0x3FFE_8000 ~ 0x3FFE_FFFF). This can be done
on a per-CPU basis: setting bit 0 of register DPORT_PRO_BOOT_REMAP_CTRL_REG or
DPORT_APP_BOOT_REMAP_CTRL_REG will remap SRAM for the PRO_CPU and APP_CPU,
respectively.
1.3.2.2 Internal ROM 1
The capacity of Internal ROM 1 is 64 KB. It can be read by either CPU at an address range 0x3FF9_0000 ~
0x3FF9_FFFF of the data bus.
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1. System and Memory
1.3.2.3 Internal SRAM 0
The capacity of Internal SRAM 0 is 192 KB. Hardware can be configured to use the first 64 KB to cache external
memory access. When not used as cache, the first 64 KB can be read and written by either CPU at addresses
0x4007_0000 ~ 0x4007_FFFF of the instruction bus. The remaining 128 KB can always be read and written by
either CPU at addresses 0x4008_0000 ~ 0x4009_FFFF of instruction bus.
1.3.2.4 Internal SRAM 1
The capacity of Internal SRAM 1 is 128 KB. Either CPU can read and write this memory at addresses
0x3FFE_0000 ~ 0x3FFF_FFFF of the data bus, and also at addresses 0x400A_0000 ~ 0x400B_FFFF of the
instruction bus.
The address range accessed via the instruction bus is in reverse order (word-wise) compared to access via the
data bus. That is to say, address
0x3FFE_0000 and 0x400B_FFFC access the same word
0x3FFE_0004 and 0x400B_FFF8 access the same word
0x3FFE_0008 and 0x400B_FFF4 access the same word
……
0x3FFF_FFF4 and 0x400A_0008 access the same word
0x3FFF_FFF8 and 0x400A_0004 access the same word
0x3FFF_FFFC and 0x400A_0000 access the same word
The data bus and instruction bus of the CPU are still both little-endian, so the byte order of individual words is not
reversed between address spaces. For example, address
0x3FFE_0000 accesses the least significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0001 accesses the second least significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0002 accesses the second most significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0003 accesses the most significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0004 accesses the least significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0005 accesses the second least significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0006 accesses the second most significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0007 accesses the most significant byte in the word accessed by 0x400B_FFF8.
……
0x3FFF_FFF8 accesses the least significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFF9 accesses the second least significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFA accesses the second most significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFB accesses the most significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFC accesses the least significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFD accesses the second most significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFE accesses the second most significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFF accesses the most significant byte in the word accessed by 0x400A_0000.
Part of this memory can be remapped onto the ROM 0 address space. See Internal Rom 0 for more
information.
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1. System and Memory
1.3.2.5 Internal SRAM 2
The capacity of Internal SRAM 2 is 200 KB. It can be read and written by either CPU at addresses 0x3FFA_E000
~ 0x3FFD_FFFF on the data bus.
1.3.2.6 DMA
DMA uses the same addressing as the CPU data bus to read and write Internal SRAM 1 and Internal SRAM 2.
This means DMA uses an address range of 0x3FFE_0000 ~ 0x3FFF_FFFF to read and write Internal SRAM 1 and
an address range of 0x3FFA_E000 ~ 0x3FFD_FFFF to read and write Internal SRAM 2.
In the ESP32, 13 peripherals are equipped with DMA. Table 3 lists these peripherals.
Table 3: Module with DMA
UART0 UART1 UART2
SPI1 SPI2 SPI3
I2S0 I2S1
SDIO Slave SDMMC
EMAC
BT WIFI
1.3.2.7 RTC FAST Memory
RTC FAST Memory is 8 KB of SRAM. It can be read and written by PRO_CPU only at an address range of
0x3FF8_0000 ~ 0x3FF8_1FFF on the data bus or at an address range of 0x400C_0000 ~ 0x400C_1FFF on the
instruction bus. Unlike most other memory regions, RTC FAST memory cannot be accessed by the
APP_CPU.
The two address ranges of PRO_CPU access RTC FAST Memory in the same order, so, for example, addresses
0x3FF8_0000 and 0x400C_0000 access the same word. On the APP_CPU, these address ranges do not
provide access to RTC FAST Memory or any other memory location.
1.3.2.8 RTC SLOW Memory
RTC SLOW Memory is 8 KB of SRAM which can be read and written by either CPU at an address range of
0x5000_0000 ~ 0x5000_1FFF. This address range is shared by both the data bus and the instruction bus.
1.3.3 External Memory
The ESP32 can access external SPI flash and SPI SRAM as external memory. Table 4 provides a list of external
memories that can be accessed by either CPU at a range of addresses on the data and instruction buses. When
a CPU accesses external memory through the Cache and MMU, the cache will map the CPU’s address to an
external physical memory address (in the external memory’s address space), according to the MMU settings. Due
to this address mapping, the ESP32 can address up to 16 MB External Flash and 8 MB External SRAM.
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1. System and Memory
Table 4: External Memory Address Mapping
Bus Type
Data 0x3F40_0000 0x3F7F_FFFF 4 MB External Flash Read
Data 0x3F80_0000 0x3FBF_FFFF 4 MB External SRAM Read and Write
Bus Type
Instruction 0x400C_2000 0x40BF_FFFF 11512 KB External Flash Read
Low Address High Address
Low Address High Address
Boundary Address
Boundary Address
Size Target Comment
Size Target Comment
1.3.4 Cache
As shown in Figure 3, each of the two CPUs in ESP32 has 32 KB of cache for accessing external storage. PRO
CPU uses bit PRO_CACHE_ENABLE in register DPORT_PRO_CACHE_CTRL_REG to enable the Cache, while
APP CPU uses bit APP_CACHE_ENABLE in register DPORT_APP_CACHE_CTRL_REG to enable the same
function.
Figure 3: Cache Block Diagram
ESP32 uses a two-way set-associative cache. When the Cache function is to be used either by PRO CPU or
APP CPU, bit CACHE_MUX_MODE[1:0] in register DPORT_CACHE_MUX_MODE_REG can be set to select
POOL0 or POOL1 in the Internal SRAM0 as the cache memory. When both PRO CPU and APP CPU use the
Cache function, POOL0 and POOL1 in the Internal SRAM0 will be used simultaneously as the cache memory,
while they can also be used by the instruction bus. This is depicted in table 5 below.
Table 5: Cache memory mode
CACHE_MUX_MODE POOL0 POOL1
0 PRO CPU APP CPU
1 PRO CPU/APP CPU -
2 - PRO CPU/APP CPU
3 APP CPU PRO CPU
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1. System and Memory
As described in table 5, when bit CACHE_MUX_MODE is set to 1 or 2, PRO CPU and APP CPU cannot enable
the Cache function at the same time. When the Cache function is enabled, POOL0 or POOL1 can only be used
as the cache memory, and cannot be used by the instruction bus as well.
ESP32 Cache supports the Flush function. It is worth noting that when the Flush function is used, the data
written in the cache will be disposed rather than being rewritten into the External SRAM. To enable the Flush
function, first clear bit x_CACHE_FLUSH_ENA in register DPORT_x_CACHE_CTRL_REG, then set this bit to 1.
Afterwards, the system hardware will set bit x_CACHE_FLUSH_DONE to 1, where x can be ”PRO” or ”APP”,
indicating that the cache flush operation has been completed.
For more information about the address mapping of ESP32 Cache, please refer to Embedded Memory and
External Memory.
1.3.5 Peripherals
The ESP32 has 41 peripherals. Table 6 specifically describes the peripherals and their respective address
ranges. Nearly all peripheral modules can be accessed by either CPU at the same address with just a single
exception; this being the PID Controller.
Table 6: Peripheral Address Mapping
Bus Type
Data 0x3FF0_0000 0x3FF0_0FFF 4 KB DPort Register
Data 0x3FF0_1000 0x3FF0_1FFF 4 KB AES Accelerator
Data 0x3FF0_2000 0x3FF0_2FFF 4 KB RSA Accelerator
Data 0x3FF0_3000 0x3FF0_3FFF 4 KB SHA Accelerator
Data 0x3FF0_4000 0x3FF0_4FFF 4 KB Secure Boot
Data 0x3FF1_0000 0x3FF1_3FFF 16 KB Cache MMU Table
Data 0x3FF1_F000 0x3FF1_FFFF 4 KB PID Controller Per-CPU peripheral
Data 0x3FF4_0000 0x3FF4_0FFF 4 KB UART0
Data 0x3FF4_2000 0x3FF4_2FFF 4 KB SPI1
Data 0x3FF4_3000 0x3FF4_3FFF 4 KB SPI0
Data 0x3FF4_4000 0x3FF4_4FFF 4 KB GPIO
Data 0x3FF4_8000 0x3FF4_8FFF 4 KB RTC
Data 0x3FF4_9000 0x3FF4_9FFF 4 KB IO MUX
Data 0x3FF4_B000 0x3FF4_BFFF 4 KB SDIO Slave One of three parts
Data 0x3FF4_C000 0x3FF4_CFFF 4 KB UDMA1
Data 0x3FF4_F000 0x3FF4_FFFF 4 KB I2S0
Data 0x3FF5_0000 0x3FF5_0FFF 4 KB UART1
Low Address High Address
0x3FF0_5000 0x3FF0_FFFF 44 KB Reserved
0x3FF1_4000 0x3FF1_EFFF 44 KB Reserved
0x3FF2_0000 0x3FF3_FFFF 128 KB Reserved
0x3FF4_1000 0x3FF4_1FFF 4 KB Reserved
0x3FF4_5000 0x3FF4_7FFF 12 KB Reserved
0x3FF4_A000 0x3FF4_AFFF 4 KB Reserved
0x3FF4_D000 0x3FF4_EFFF 8 KB Reserved
0x3FF5_1000 0x3FF5_2FFF 8 KB Reserved
Boundary Address
Size Target Comment
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1. System and Memory
Bus Type
Data 0x3FF5_3000 0x3FF5_3FFF 4 KB I2C0
Data 0x3FF5_4000 0x3FF5_4FFF 4 KB UDMA0
Data 0x3FF5_5000 0x3FF5_5FFF 4 KB SDIO Slave One of three parts
Data 0x3FF5_6000 0x3FF5_6FFF 4 KB RMT
Data 0x3FF5_7000 0x3FF5_7FFF 4 KB PCNT
Data 0x3FF5_8000 0x3FF5_8FFF 4 KB SDIO Slave One of three parts
Data 0x3FF5_9000 0x3FF5_9FFF 4 KB LED PWM
Data 0x3FF5_A000 0x3FF5_AFFF 4 KB Efuse Controller
Data 0x3FF5_B000 0x3FF5_BFFF 4 KB Flash Encryption
Data 0x3FF5_E000 0x3FF5_EFFF 4 KB PWM0
Data 0x3FF5_F000 0x3FF5_FFFF 4 KB TIMG0
Data 0x3FF6_0000 0x3FF6_0FFF 4 KB TIMG1
Data 0x3FF6_4000 0x3FF6_4FFF 4 KB SPI2
Data 0x3FF6_5000 0x3FF6_5FFF 4 KB SPI3
Data 0x3FF6_6000 0x3FF6_6FFF 4 KB SYSCON
Data 0x3FF6_7000 0x3FF6_7FFF 4 KB I2C1
Data 0x3FF6_8000 0x3FF6_8FFF 4 KB SDMMC
Data 0x3FF6_9000 0x3FF6_AFFF 8 KB EMAC
Data 0x3FF6_C000 0x3FF6_CFFF 4 KB PWM1
Data 0x3FF6_D000 0x3FF6_DFFF 4 KB I2S1
Data 0x3FF6_E000 0x3FF6_EFFF 4 KB UART2
Data 0x3FF6_F000 0x3FF6_FFFF 4 KB PWM2
Data 0x3FF7_0000 0x3FF7_0FFF 4 KB PWM3
Data 0x3FF7_5000 0x3FF7_5FFF 4 KB RNG
Low Address High Address
0x3FF5_C000 0x3FF5_DFFF 8 KB Reserved
0x3FF6_1000 0x3FF6_3FFF 12 KB Reserved
0x3FF6_B000 0x3FF6_BFFF 4 KB Reserved
0x3FF7_1000 0x3FF7_4FFF 16 KB Reserved
0x3FF7_6000 0x3FF7_FFFF 40 KB Reserved
Boundary Address
Size Target Comment
1.3.5.1 Asymmetric PID Controller Peripheral
There are two PID Controllers in the system. They serve the PRO_CPU and the APP_CPU, respectively. The
PRO_CPU and the APP_CPU can only access their own PID Controller and not that of their counterpart.
Each CPU uses the same memory range 0x3FF1_F000 ~ 3FF1_FFFF to access its own PID Controller.
1.3.5.2 Non-Contiguous Peripheral Memory Ranges
The SDIO Slave peripheral consists of three parts and the two CPUs use non-contiguous addresses to access
these. The three parts are accessed at the address ranges 0x3FF4_B000 ~ 3FF4_BFFF, 0x3FF5_5000 ~
3FF5_5FFF and 0x3FF5_8000 ~ 3FF5_8FFF of each CPU’s data bus. Similarly to other peripherals, access to
this peripheral is identical for both CPUs.
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1. System and Memory
1.3.5.3 Memory Speed
The ROM as well as the SRAM are both clocked from CPU_CLK and can be accessed by the CPU in a single
cycle. The RTC FAST memory is clocked from the APB_CLOCK and the RTC SLOW memory from the
FAST_CLOCK, so access to these memories may be slower. DMA uses the APB_CLK to access memory.
Internally, the SRAM is organized in 32K-sized banks. Each CPU and DMA channel can simultaneously access
the SRAM at full speed, provided they access addresses in different memory banks.
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2. Interrupt Matrix
2. Interrupt Matrix
2.1 Overview
The Interrupt Matrix embedded in the ESP32 independently allocates peripheral interrupt sources to the two
CPUs’ peripheral interrupts. This configuration is made to be highly flexible in order to meet many different needs.
2.2 Features
• Accepts 71 peripheral interrupt sources as input.
• Generates 26 peripheral interrupt sources per CPU as output (52 total).
• CPU NMI Interrupt Mask.
• Queries current interrupt status of peripheral interrupt sources.
The structure of the Interrupt Matrix is shown in Figure 4.
Figure 4: Interrupt Matrix Structure
2.3 Functional Description
2.3.1 Peripheral Interrupt Source
ESP32 has 71 peripheral interrupt sources in total. All peripheral interrupt sources are listed in table 7. 67 of 71
ESP32 peripheral interrupt sources can be allocated to either CPU.
The four remaining peripheral interrupt sources are CPU-specific, two per CPU. GPIO_INTERRUPT_PRO and
GPIO_INTERRUPT_PRO_NMI can only be allocated to PRO_CPU. GPIO_INTERRUPT_APP and
GPIO_INTERRUPT_APP_NMI can only be allocated to APP_CPU. As a result, PRO_CPU and APP_CPU each
have 69 peripheral interrupt sources.
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Table 7: PRO_CPU, APP_CPU Interrupt Configuration
2. Interrupt Matrix
PRO_CPU APP_CPU
Peripheral Interrupt
Configuration Register
PRO_MAC_INTR_MAP_REG 0
PRO_MAC_NMI_MAP_REG 1 1 MAC_NMI 1 1 APP_MAC_NMI_MAP_REG
PRO_BB_INT_MAP_REG 2 2 BB_INT 2 2 APP_BB_INT_MAP_REG
PRO_BT_MAC_INT_MAP_REG 3 3 BT_MAC_INT 3 3 APP_BT_MAC_INT_MAP_REG
PRO_BT_BB_INT_MAP_REG 4 4 BT_BB_INT 4 4 APP_BT_BB_INT_MAP_REG
PRO_BT_BB_NMI_MAP_REG 5 5 BT_BB_NMI 5 5 APP_BT_BB_NMI_MAP_REG
PRO_RWBT_IRQ_MAP_REG 6 6 RWBT_IRQ 6 6 APP_RWBT_IRQ_MAP_REG
PRO_BT_BB_NMI_MAP_REG 5 5 BT_BB_NMI 5 5 APP_BT_BB_NMI_MAP_REG
PRO_RWBT_IRQ_MAP_REG 6 6 RWBT_IRQ 6 6 APP_RWBT_IRQ_MAP_REG
PRO_RWBLE_IRQ_MAP_REG 7 7 RWBLE_IRQ 7 7 APP_RWBLE_IRQ_MAP_REG
PRO_RWBT_NMI_MAP_REG 8 8 RWBT_NMI 8 8 APP_RWBT_NMI_MAP_REG
PRO_RWBLE_NMI_MAP_REG 9 9 RWBLE_NMI 9 9 APP_RWBLE_NMI_MAP_REG
PRO_SLC0_INTR_MAP_REG 10 10 SLC0_INTR 10 10 APP_SLC0_INTR_MAP_REG
PRO_SLC1_INTR_MAP_REG 11 11 SLC1_INTR 11 11 APP_SLC1_INTR_MAP_REG
PRO_UHCI0_INTR_MAP_REG 12 12 UHCI0_INTR 12 12 APP_UHCI0_INTR_MAP_REG
PRO_UHCI1_INTR_MAP_REG 13 13 UHCI1_INTR 13 13 APP_UHCI1_INTR_MAP_REG
PRO_TG_T0_LEVEL_INT_MAP_REG 14 14 TG_T0_LEVEL_INT 14 14 APP_TG_T0_LEVEL_INT_MAP_REG
PRO_TG_T1_LEVEL_INT_MAP_REG 15 15 TG_T1_LEVEL_INT 15 15 APP_TG_T1_LEVEL_INT_MAP_REG
PRO_TG_WDT_LEVEL_INT_MAP_REG 16 16 TG_WDT_LEVEL_INT 16 16 APP_TG_WDT_LEVEL_INT_MAP_REG
PRO_TG_LACT_LEVEL_INT_MAP_REG 17 17 TG_LACT_LEVEL_INT 17 17 APP_TG_LACT_LEVEL_INT_MAP_REG
PRO_TG1_T0_LEVEL_INT_MAP_REG 18 18 TG1_T0_LEVEL_INT 18 18 APP_TG1_T0_LEVEL_INT_MAP_REG
PRO_TG1_T1_LEVEL_INT_MAP_REG 19 19 TG1_T1_LEVEL_INT 19 19 APP_TG1_T1_LEVEL_INT_MAP_REG
PRO_TG1_WDT_LEVEL_INT_MAP_REG 20 20 TG1_WDT_LEVEL_INT 20 20 APP_TG1_WDT_LEVEL_INT_MAP_REG
PRO_TG1_LACT_LEVEL_INT_MAP_REG 21 21 TG1_LACT_LEVEL_INT 21 21 APP_TG1_LACT_LEVEL_INT_MAP_REG
PRO_GPIO_INTERRUPT_PRO_MAP_REG
PRO_GPIO_INTERRUPT_PRO_NMI_MAP_REG
PRO_CPU_INTR_FROM_CPU_0_MAP_REG 24 24 CPU_INTR_FROM_CPU_0 24 24 APP_CPU_INTR_FROM_CPU_0_MAP_REG
PRO_CPU_INTR_FROM_CPU_1_MAP_REG 25 25 CPU_INTR_FROM_CPU_1 25 25 APP_CPU_INTR_FROM_CPU_1_MAP_REG
PRO_CPU_INTR_FROM_CPU_2_MAP_REG 26 26 CPU_INTR_FROM_CPU_2 26 26 APP_CPU_INTR_FROM_CPU_2_MAP_REG
PRO_CPU_INTR_FROM_CPU_3_MAP_REG 27 27 CPU_INTR_FROM_CPU_3 27 27 APP_CPU_INTR_FROM_CPU_3_MAP_REG
PRO_SPI_INTR_0_MAP_REG 28 28 SPI_INTR_0 28 28 APP_SPI_INTR_0_MAP_REG
PRO_SPI_INTR_1_MAP_REG 29 29 SPI_INTR_1 29 29 APP_SPI_INTR_1_MAP_REG
PRO_SPI_INTR_2_MAP_REG 30 30 SPI_INTR_2 30 30 APP_SPI_INTR_2_MAP_REG
PRO_SPI_INTR_3_MAP_REG 31 31 SPI_INTR_3 31 31 APP_SPI_INTR_3_MAP_REG
PRO_I2S0_INT_MAP_REG 0
PRO_I2S1_INT_MAP_REG 1 33 I2S1_INT 33 1 APP_I2S1_INT_MAP_REG
PRO_UART_INTR_MAP_REG 2 34 UART_INTR 34 2 APP_UART_INTR_MAP_REG
PRO_UART1_INTR_MAP_REG 3 35 UART1_INTR 35 3 APP_UART1_INTR_MAP_REG
PRO_UART2_INTR_MAP_REG 4 36 UART2_INTR 36 4 APP_UART2_INTR_MAP_REG
PRO_SDIO_HOST_INTERRUPT_MAP_REG 5 37 SDIO_HOST_INTERRUPT 37 5 APP_SDIO_HOST_INTERRUPT_MAP_REG
PRO_EMAC_INT_MAP_REG 6 38 EMAC_INT 38 6 APP_EMAC_INT_MAP_REG
PRO_PWM0_INTR_MAP_REG 7 39 PWM0_INTR 39 7 APP_PWM0_INTR_MAP_REG
PRO_PWM1_INTR_MAP_REG 8 40 PWM1_INTR 40 8 APP_PWM1_INTR_MAP_REG
PRO_PWM2_INTR_MAP_REG 9 41 PWM2_INTR 41 9 APP_PWM2_INTR_MAP_REG
PRO_PWM3_INTR_MAP_REG 10 42 PWM3_INTR 42 10 APP_PWM3_INTR_MAP_REG
PRO_LEDC_INT_MAP_REG 11 43 LEDC_INT 43 11 APP_LEDC_INT_MAP_REG
PRO_EFUSE_INT_MAP_REG 12 44 EFUSE_INT 44 12 APP_EFUSE_INT_MAP_REG
PRO_CAN_INT_MAP_REG 13 45 CAN_INT 45 13 APP_CAN_INT_MAP_REG
PRO_RTC_CORE_INTR_MAP_REG 14 46 RTC_CORE_INTR 46 14 APP_RTC_CORE_INTR_MAP_REG
PRO_RMT_INTR_MAP_REG 15 47 RMT_INTR 47 15 APP_RMT_INTR_MAP_REG
PRO_PCNT_INTR_MAP_REG 16 48 PCNT_INTR 48 16 APP_PCNT_INTR_MAP_REG
PRO_I2C_EXT0_INTR_MAP_REG 17 49 I2C_EXT0_INTR 49 17 APP_I2C_EXT0_INTR_MAP_REG
PRO_I2C_EXT1_INTR_MAP_REG 18 50 I2C_EXT1_INTR 50 18 APP_I2C_EXT1_INTR_MAP_REG
PRO_RSA_INTR_MAP_REG 19 51 RSA_INTR 51 19 APP_RSA_INTR_MAP_REG
PRO_SPI1_DMA_INT_MAP_REG 20 52 SPI1_DMA_INT 52 20 APP_SPI1_DMA_INT_MAP_REG
Status Register Status Register
Bit Name
PRO_INTR_STATUS_REG_0
22 22
23 23
PRO_INTR_STATUS_REG_1
No. Name No.
0 MAC_INTR 0
GPIO_INTERRUPT_PRO GPIO_INTERRUPT_APP
GPIO_INTERRUPT_PRO_NMI GPIO_INTERRUPT_APP_NMI
32 I2S0_INT 32
Peripheral Interrupt Source
Name Bit
APP_INTR_STATUS_REG_0
22 22
23 23
APP_INTR_STATUS_REG_1
Peripheral Interrupt
Configuration Register
0 APP_MAC_INTR_MAP_REG
APP_GPIO_INTERRUPT_APP_MAP_REG
APP_GPIO_INTERRUPT_APP_NMI_MAP_REG
0 APP_I2S0_INT_MAP_REG
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PRO_CPU APP_CPU
Peripheral Interrupt
Configuration Register
PRO_SPI2_DMA_INT_MAP_REG 21
PRO_SPI3_DMA_INT_MAP_REG 22 54 SPI3_DMA_INT 54 22 APP_SPI3_DMA_INT_MAP_REG
PRO_WDG_INT_MAP_REG 23 55 WDG_INT 55 23 APP_WDG_INT_MAP_REG
PRO_TIMER_INT1_MAP_REG 24 56 TIMER_INT1 56 24 APP_TIMER_INT1_MAP_REG
PRO_TIMER_INT2_MAP_REG 25 57 TIMER_INT2 57 25 APP_TIMER_INT2_MAP_REG
PRO_TG_T0_EDGE_INT_MAP_REG 26 58 TG_T0_EDGE_INT 58 26 APP_TG_T0_EDGE_INT_MAP_REG
PRO_TG_T1_EDGE_INT_MAP_REG 27 59 TG_T1_EDGE_INT 59 27 APP_TG_T1_EDGE_INT_MAP_REG
PRO_TG_WDT_EDGE_INT_MAP_REG 28 60 TG_WDT_EDGE_INT 60 28 APP_TG_WDT_EDGE_INT_MAP_REG
PRO_TG_LACT_EDGE_INT_MAP_REG 29 61 TG_LACT_EDGE_INT 61 29 APP_TG_LACT_EDGE_INT_MAP_REG
PRO_TG1_T0_EDGE_INT_MAP_REG 30 62 TG1_T0_EDGE_INT 62 30 APP_TG1_T0_EDGE_INT_MAP_REG
PRO_TG1_T1_EDGE_INT_MAP_REG 31 63 TG1_T1_EDGE_INT 63 31 APP_TG1_T1_EDGE_INT_MAP_REG
PRO_TG1_WDT_EDGE_INT_MAP_REG 0
PRO_TG1_LACT_EDGE_INT_MAP_REG 1 65 TG1_LACT_EDGE_INT 65 1 APP_TG1_LACT_EDGE_INT_MAP_REG
PRO_MMU_IA_INT_MAP_REG 2 66 MMU_IA_INT 66 2 APP_MMU_IA_INT_MAP_REG
PRO_MPU_IA_INT_MAP_REG 3 67 MPU_IA_INT 67 3 APP_MPU_IA_INT_MAP_REG
PRO_CACHE_IA_INT_MAP_REG 4 68 CACHE_IA_INT 68 4 APP_CACHE_IA_INT_MAP_REG
Status Register Status Register
Bit Name
PRO_INTR_STATUS_REG_1
PRO_INTR_STATUS_REG_2
No. Name No.
53 SPI2_DMA_INT 53
64 TG1_WDT_EDGE_INT 64
Peripheral Interrupt Source
Name Bit
APP_INTR_STATUS_REG_1
APP_INTR_STATUS_REG_2
Peripheral Interrupt
Configuration Register
21 APP_SPI2_DMA_INT_MAP_REG
0 APP_TG1_WDT_EDGE_INT_MAP_REG
2. Interrupt Matrix
2. Interrupt Matrix
2.3.2 CPU Interrupt
Both of the two CPUs (PRO and APP) have 32 interrupts each, of which 26 are peripheral interrupts. All
interrupts in a CPU are listed in Table 8.
Table 8: CPU Interrupts
No. Category Type Priority Level
0 Peripheral Level-Triggered 1
1 Peripheral Level-Triggered 1
2 Peripheral Level-Triggered 1
3 Peripheral Level-Triggered 1
4 Peripheral Level-Triggered 1
5 Peripheral Level-Triggered 1
6 Internal Timer.0 1
7 Internal Software 1
8 Peripheral Level-Triggered 1
9 Peripheral Level-Triggered 1
10 Peripheral Edge-Triggered 1
11 Internal Profiling 3
12 Peripheral Level-Triggered 1
13 Peripheral Level-Triggered 1
14 Peripheral NMI NMI
15 Internal Timer.1 3
16 Internal Timer.2 5
17 Peripheral Level-Triggered 1
18 Peripheral Level-Triggered 1
19 Peripheral Level-Triggered 2
20 Peripheral Level-Triggered 2
21 Peripheral Level-Triggered 2
22 Peripheral Edge-Triggered 3
23 Peripheral Level-Triggered 3
24 Peripheral Level-Triggered 4
25 Peripheral Level-Triggered 4
26 Peripheral Level-Triggered 5
27 Peripheral Level-Triggered 3
28 Peripheral Edge-Triggered 4
29 Internal Software 3
30 Peripheral Edge-Triggered 4
31 Peripheral Level-Triggered 5
2.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU
In this section:
• Source_X stands for any particular peripheral interrupt source.
• PRO_X_MAP_REG (or APP_X_MAP_REG) stands for any particular peripheral interrupt configuration
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2. Interrupt Matrix
register of the PRO_CPU (or APP_CPU). The peripheral interrupt configuration register corresponds to the
peripheral interrupt source Source_X. In Table 7 the registers listed under “PRO_CPU (APP_CPU) -
Peripheral Interrupt Configuration Register” correspond to the peripheral interrupt sources listed in
“Peripheral Interrupt Source - Name”.
• Interrupt_P stands for CPU peripheral interrupt, numbered as Num_P. Num_P can take the ranges 0 ~ 5, 8
~ 10, 12 ~ 14, 17 ~ 28, 30 ~ 31.
• Interrupt_I stands for the CPU internal interrupt numbered as Num_I. Num_I can take values 6, 7, 11, 15,
16, 29.
Using this terminology, the possible operations of the Interrupt Matrix controller can be described as
follows:
• Allocate peripheral interrupt source Source_X to CPU (PRO_CPU or APP_CPU)
Set PRO_X_MAP_REG�or APP_X_MAP_REG�to Num_P. Num_P can be any CPU peripheral interrupt
number. CPU interrupts can be shared between multiple peripherals (see below).
• Disable peripheral interrupt source Source_X for CPU (PRO_CPU or APP_CPU)
Set PRO_X_MAP_REG�or APP_X _MAP_REG�for peripheral interrupt source to any Num_I. The specific
choice of internal interrupt number does not change behaviour, as none of the interrupt numbered as
Num_I is connected to either CPU.
• Allocate multiple peripheral sources Source_Xn ORed to PRO_CPU (APP_CPU) peripheral interrupt
Set multiple PRO_Xn_MAP_REG (APP_Xn_MAP_REG) to the same Num_P. Any of these peripheral
interrupts will trigger CPU Interrupt_P.
2.3.4 CPU NMI Interrupt Mask
The Interrupt Matrix temporarily masks all peripheral interrupt sources allocated to PRO_CPU’s ( or APP_CPU’s )
NMI interrupt, if it receives the signal PRO_CPU NMI Interrupt Mask ( or APP_CPU NMI Interrupt Mask ) from the
peripheral PID Controller, respectively.
2.3.5 Query Current Interrupt Status of Peripheral Interrupt Source
The current interrupt status of a peripheral interrupt source can be read via the bit value in
PRO_INTR_STATUS_REG_n (APP_INTR_STATUS_REG_n), as shown in the mapping in Table 7.
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3. Reset and Clock
3. Reset and Clock
3.1 System Reset
3.1.1 Introduction
The ESP32 has three reset levels: CPU reset, Core reset, and System reset. None of these reset levels clear the
RAM. Figure 5 shows the subsystems included in each reset level.
Figure 5: System Reset
• CPU reset: Only resets the registers of one or both of the CPU cores.
• Core reset: Resets all the digital registers, including CPU cores, external GPIO and digital GPIO. The RTC is
not reset.
• System reset: Resets all the registers on the chip, including those of the RTC.
3.1.2 Reset Source
While most of the time the APP_CPU and PRO_CPU will be reset simultaneously, some reset sources are able to
reset only one of the two cores. The reset reason for each core can be looked up individually: the PRO_CPU
reset reason will be stored in RTC_CNTL_RESET_CAUSE_PROCPU, the reset reason for the APP_CPU in
RTC_CNTL_RESET_CAUSE_APPCPU. Table 9 shows the possible reset reason values that can be read from
these registers.
Table 9: PRO_CPU and APP_CPU Reset Reason Values
PRO APP Source Reset Type Note
0x01 0x01 Chip Power On Reset System Reset -
0x10 0x10 RWDT System Reset System Reset See WDT Chapter.
0x0F 0x0F Brown Out Reset System Reset See Power Management Chapter.
0x03 0x03 Software System Reset Core Reset Configure RTC_CNTL_SW_SYS_RST register.
0x05 0x05 Deep Sleep Reset Core Reset See Power Management Chapter.
0x07 0x07 MWDT0 Global Reset Core Reset See WDT Chapter.
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3. Reset and Clock
PRO APP APP Source Reset Type Note
0x08 0x08 MWDT1 Global Reset Core Reset See WDT Chapter.
0x09 0x09 RWDT Core Reset Core Reset See WDT Chapter.
0x0B - MWDT0 CPU Reset CPU Reset See WDT Chapter.
0x0C - Software CPU Reset CPU Reset Configure RTC_CNTL_SW_APPCPU_RST register.
- 0x0B MWDT1 CPU Reset CPU Reset See WDT Chapter.
- 0x0C Software CPU Reset CPU Reset Configure RTC_CNTL_SW_APPCPU_RST register.
0x0D 0x0D RWDT CPU Reset CPU Reset See WDT Chapter.
Indicates that the PRO CPU has indepen-
- 0xE PRO CPU Reset CPU Reset
dently reset the APP CPU by configuring the
DPORT_APPCPU_RESETTING register.
3.2 System Clock
3.2.1 Introduction
The ESP32 integrates multiple clock sources for the CPU cores, the peripherals and the RTC. These clocks can
be configured to meet different requirements. Figure 6 shows the system clock structure.
Figure 6: System Clock
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3. Reset and Clock
3.2.2 Clock Source
The ESP32 can use an external crystal oscillator, an internal PLL or an oscillating circuit as a clock source.
Specifically, the clock sources available are:
• High Speed Clocks
– PLL_CLK is an internal PLL clock with a frequency of 320 MHz.
– XTL_CLK is a clock signal generated using an external crystal with a frequency range of 2 ~ 40 MHz.
• Low Power Clocks
– XTL32K_CLK is a clock generated using an external crystal with a frequency of 32 KHz.
– RTC8M_CLK is an internal clock with a default frequency of 8 MHz. This frequency is adjustable.
– RTC8M_D256_CLK is divided from RTC8M_CLK 256. Its frequency is (RTC8M_CLK / 256). With the
default RTC8M_CLK frequency of 8 MHz, this clock runs at 31.250 KHz.
– RTC_CLK is an internal low power clock with a default frequency of 150 KHz. This frequency is
adjustable.
• Audio Clock
– APLL_CLK is an internal Audio PLL clock with a frequency range of 16 ~ 128 MHz.
3.2.3 CPU Clock
As Figure 6 shows, CPU_CLK is the master clock for both CPU cores. CPU_CLK clock can be as high as 160
MHz when the CPU is in high performance mode. Alternatively, the CPU can run at lower frequencies to reduce
power consumption.
The CPU_CLK clock source is determined by the RTC_CNTL_SOC_CLK_SEL register. PLL_CLK, APLL_CLK,
RTC8M_CLK and XTL_CLK can be set as the CPU_CLK source; see Table 10 and 11.
Table 10: CPU_CLK Source
RTC_CNTL_SOC_CLK_SEL Value Clock Source
0 XTL_CLK
1 PLL_CLK
2 RTC8M_CLK
3 APLL_CLK
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3. Reset and Clock
Table 11: CPU_CLK Derivation
Clock Source SEL* CPU Clock
0 / XTL_CLK -
1 / PLL_CLK 0
1 / PLL_CLK 1
2 / RTC8M_CLK -
3 / APLL_CLK 0 CPU_CLK = APLL_CLK / 4
3 / APLL_CLK 1 CPU_CLK = APLL_CLK / 2
*SEL: DPORT_CPUPERIOD _SEL value
CPU_CLK = XTL_CLK / (APB_CTRL_PRE_DIV_CNT+1)
APB_CTRL_PRE_DIV_CNT range is 0 ~ 1023. Default is 0.
CPU_CLK = PLL_CLK / 4
CPU_CLK frequency is 80 MHz
CPU_CLK = PLL_CLK / 2
CPU_CLK frequency is 160 MHz
CPU_CLK = RTC8M_CLK / (APB_CTRL_PRE_DIV_CNT+1)
APB_CTRL_PRE_DIV_CNT range is 0 ~ 1023. Default is 0.
3.2.4 Peripheral Clock
Peripheral clocks include APB_CLK, REF_TICK, LEDC_SCLK, APLL_CLK and PLL_D2_CLK.
Table 12 shows which clocks can be used by which peripherals.
Table 12: Peripheral Clock Usage
Peripherals APB_CLK REF_TICK LEDC_SCLK APLL_CLK PLL_D2_CLK
EMAC Y N N Y N
TIMG Y N N N N
I2S Y N N Y Y
UART Y Y N N N
RMT Y Y N N N
LED PWM Y Y Y N N
PWM Y N N N N
I2C Y N N N N
SPI Y N N N N
PCNT Y N N N N
Efuse Controller Y N N N N
SDIO Slave Y N N N N
SDMMC Y N N N N
3.2.4.1 APB_CLK Source
The APB_CLK is derived from CPU_CLK as detailed in Table 13. The division factor depends on the CPU_CLK
source.
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3. Reset and Clock
Table 13: APB_CLK Derivation
CPU_CLK Source APB_CLK
PLL_CLK PLL_CLK / 4
APLL_CLK CPU_CLK / 2
XTAL_CLK CPU_CLK
RTC8M_CLK CPU_CLK
3.2.4.2 REF_TICK Source
REF_TICK is derived from APB_CLK via a divider. The divider value used depends on the APB_CLK source,
which in turn depends on the CPU_CLK source.
By configuring correct divider values for each APB_CLK source, the user can ensure that the REF_TICK
frequency does not change when CPU_CLK changes source, causing the APB_CLK frequency to change.
Clock divider registers are shown in Table 14.
Table 14: REF_TICK Derivation
CPU_CLK & APB_CLK Source Clock Divider Register
PLL_CLK APB_CTRL_PLL_TICK_NUM
XTAL_CLK APB_CTRL_XTAL_TICK_NUM
APLL_CLK APB_CTRL_APLL_TICK_NUM
RTC8M_CLK APB_CTRL_CK8M_TICK_NUM
3.2.4.3 LEDC_SCLK Source
The LEDC_SCLK clock source is selected by the LEDC_APB_CLK_SEL register, as shown in Table 15.
Table 15: LEDC_SCLK Derivation
LEDC_APB_CLK_SEL Value LEDC_SCLK Source
0 RTC8M_CLK
1 APB_CLK
3.2.4.4 APLL_SCLK Source
The APLL_CLK is sourced from PLL_CLK, with its output frequency configured using the APLL configuration
registers.
3.2.4.5 PLL_D2_CLK Source
PLL_D2_CLK is half the PLL_CLK frequency.
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3. Reset and Clock
3.2.4.6 Clock Source Considerations
Most peripherals will operate using the APB_CLK frequency as a reference. When this frequency changes, the
peripherals will need to update their clock configuration to operate at the same frequency after the change.
Peripherals accessing REF_TICK can continue operating normally when switching clock sources, without
changing clock source. Please see Table 12 for details.
The LED PWM module can use RTC8M_CLK as a clock source when APB_CLK is disabled. In other words,
when the system is in low-power consumption mode (see Power Management Chapter), normal peripherals will
be halted (APB_CLK is turned off), but the LED PWM can work normally via RTC8M_CLK.
3.2.5 Wi-Fi BT Clock
Wi-Fi and BT can only operate if APB_CLK uses PLL_CLK as its clock source. Suspending PLL_CLK requires
Wi-Fi and BT to both have entered low-power consumption mode first.
For LOW_POWER_CLK, one of RTC_CLK, SLOW_CLK, RTC8M_CLK or XTL_CLK can be selected as the
low-power consumption mode clock source for Wi-Fi and BT.
3.2.6 RTC Clock
The clock sources of SLOW_CLK and FAST_CLK are low-frequency clocks. The RTC module can operate when
most other clocks are stopped.
SLOW_CLK is used to clock the Power Management module. It can be sourced from RTC_CLK, XTL32K_CLK
or RTC8M_D256_CLK
FAST_CLK is used to clock the On-chip Sensor module. It can be sourced from a divided XTL_CLK or from
RTC8M_CLK.
3.2.7 Audio PLL
The operation of audio and other time-critical data-transfer applications requires highly-configurable, low-jitter,
and accurate clock sources. The clock sources derived from system clocks that serve digital peripherals may
carry jitter and, therefore, they do not support a high-precision clock frequency setting.
Providing an integrated precision clock source can minimize system cost. To this end, ESP32 integrates an audio
PLL intended for I2S peripherals. More details on how to clock the I2S module, using an APLL clock, can be
found in Chapter I2S. The Audio PLL formula is as follows:
f
(sdm2 +
out
xtal
=
f
sdm1
2(odiv + 2)
sdm0
+
8
2
+ 4)
16
2
The parameters of this formula are defined below:
• f
: the frequency of the crystal oscillator, usually 40 MHz;
xtal
• sdm0: the value is 0 ~ 255;
• sdm1: the value is 0 ~ 255;
• sdm2: the value is 0 ~ 63;
• odiv: the value is 0 ~ 31;
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3. Reset and Clock
The operating frequency range of the numerator is 350 MHz ~ 500 MHz:
350MHz < f
(sdm2 +
xtal
sdm1
2
sdm0
+
8
+ 4) < 500M Hz
16
2
Please note that sdm1 and sdm0 are not available on revision0 of ESP32. Please consult the silicon revision in
ECO and Workarounds for Bugs in ESP32 for further details.
Audio PLL can be manually enabled or disabled via registers RTC_CNTL_PLLA_FORCE_PU and
RTC_CNTL_PLLA_FORCE_PD, respectively. Disabling it takes priority over enabling it. When
RTC_CNTL_PLLA_FORCE_PU and RTC_CNTL_PLLA_FORCE_PD are 0, PLL will follow the state of the system,
i.e., when the system enters sleep mode, PLL will be disabled automatically; when the system wakes up, PLL will
be enabled automatically.
Espressif Systems 43 ESP32 Technical Reference Manual V4.0
4. IO_MUX and GPIO Matrix
4. IO_MUX and GPIO Matrix
4.1 Overview
The ESP32 chip features 34 physical GPIO pads. Each pad can be used as a general-purpose I/O, or be
connected to an internal peripheral signal. The IO_MUX, RTC IO_MUX and the GPIO matrix are responsible for
routing signals from the peripherals to GPIO pads. Together these systems provide highly configurable I/O.
Note that the I/O GPIO pads are 0-19, 21-23, 25-27, 32-39, while the output GPIOs are 0-19, 21-23, 25-27,
32-33. GPIO pads 34-39 are input-only.
This chapter describes the signal selection and connection between the digital pads (FUN_SEL, IE, OE, WPU,
WDU, etc.), 162 peripheral input and 176 output signals (control signals: SIG_IN_SEL, SIG_OUT_SEL, IE, OE,
etc.), fast peripheral input/output signals (control signals: IE, OE, etc.), and RTC IO_MUX.
Figure 7: IO_MUX, RTC IO_MUX and GPIO Matrix Overview
1. The IO_MUX contains one register per GPIO pad. Each pad can be configured to perform a ”GPIO” function
(when connected to the GPIO Matrix) or a direct function (bypassing the GPIO Matrix). Some high-speed
digital functions (Ethernet, SDIO, SPI, JTAG, UART) can bypass the GPIO Matrix for better high-frequency
digital performance. In this case, the IO_MUX is used to connect these pads directly to the peripheral.)
See Section 4.10 for a list of IO_MUX functions for each I/O pad.
2. The GPIO Matrix is a full-switching matrix between the peripheral input/output signals and the pads.
• For input to the chip: Each of the 162 internal peripheral inputs can select any GPIO pad as the input
source.
• For output from the chip: The output signal of each of the 34 GPIO pads can be from one of the 176
peripheral output signals.
See Section 4.9 for a list of GPIO Matrix peripheral signals.
3. RTC IO_MUX is used to connect GPIO pads to their low-power and analog functions. Only a subset of
GPIO pads have these optional ”RTC” functions.
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4. IO_MUX and GPIO Matrix
GPIO_FUNCy_IN_SEL
GPIO0_in
GPIO1_in
GPIO2_in
GPIO3_in
GPIO39_in
0 (FUNC)
1 (FUNC)
2 (GPIO)
3
39
Peripheral Signal Y
I/O Pad X
In GPIO matrix
In IO MUX
GPIO X in
MCU_SEL
2
1
3
X
GPIOX_in
0
Constant 0 input
Constant 1 input
(0x30)48
(0x38)56
0
1 (GPIO)
GPIO_SIGxx_IN_SEL
FUN_IE = 1
See Section 4.11 for a list of RTC IO_MUX functions.
4.2 Peripheral Input via GPIO Matrix
4.2.1 Summary
To receive a peripheral input signal via the GPIO Matrix, the GPIO Matrix is configured to source the peripheral
signal’s input index (0-18, 23-36, 39-58, 61-90, 95-124, 140-155, 164-181, 190-195, 198-206) from one of the
34 GPIOs (0-19, 21-23, 25-27, 32-39).
The input signal is read from the GPIO pad through the IO_MUX. The IO_MUX must be configured to set the
chosen pad to ”GPIO” function. This causes the GPIO pad input signal to be routed into the GPIO Matrix, which
in turn routes it to the selected peripheral input.
4.2.2 Functional Description
Figure 8 shows the logic for input selection via GPIO Matrix.
To read GPIO pad X into peripheral signal Y, follow the steps below:
Espressif Systems 45 ESP32 Technical Reference Manual V4.0
Figure 8: Peripheral Input via IO_MUX, GPIO Matrix
1. Configure the GPIO_FUNCy_IN_SEL_CFG register corresponding to peripheral signal Y in the GPIO Matrix:
• Set the GPIO_FUNCx_IN_SEL field in this register, corresponding to the GPIO pad X to read from.
Clear all other fields corresponding to other GPIO pads.
2. Configure the GPIO_FUNCx_OUT_SEL_CFG register and clear the GPIO_ENABLE_DATA[x] field
corresponding to GPIO pad X in the GPIO Matrix:
• Set the GPIO_FUNCx_OEN_SEL bit in the GPIO_FUNCx_OUT_SEL_CFG register to force the pin’s
output state to be determined always by the GPIO_ENABLE_DATA[x] field.
• The GPIO_ENABLE_DATA[x] field is a bit in either GPIO_ENABLE_REG (GPIOs 0-31) or
GPIO_ENABLE1_REG (GPIOs 32-39). Clear this bit to disable the output driver for the GPIO pad.
3. Configure the IO_MUX to select the GPIO Matrix. Set the IO_MUX_x_REG register corresponding to GPIO
pad X as follows:
4. IO_MUX and GPIO Matrix
• Set the function field (MCU_SEL) to the IO_MUX function corresponding to GPIO X (this is Function
#3—numeric value 2—for all pins).
• Enable the input by setting the FUN_IE bit.
• Set or clear the FUN_WPU and FUN_WPD bits, as desired, to enable/disable internal
pull-up/pull-down resistors.
Notes:
• One input pad can be connected to multiple input_signals.
• The input signal can be inverted with GPIO_FUNCx_IN_INV_SEL.
• It is possible to have a peripheral read a constantly low or constantly high input value without connecting
this input to a pad. This can be done by selecting a special GPIO_FUNCy_IN_SEL input, instead of a GPIO
number:
– When GPIO_FUNCx_IN_SEL is 0x30, input_signal_x is always 0.
– When GPIO_FUNCx_IN_SEL is 0x38, input_signal_x is always 1.
For example, to connect RMT peripheral channel 0 input signal (RMT_SIG_IN0_IDX, signal index 83) to GPIO 15,
please follow the steps below. Note that GPIO 15 is also named the MTDO pin:
1. Set the GPIO_FUNC83_IN_SEL_CFG register field GPIO_FUNC83_IN_SEL value to 15.
2. As this is an input-only signal, set GPIO_FUNC15_OEN_SEL bit in GPIO_FUNC15_OUT_SEL_CFG_REG.
3. Clear bit 15 of GPIO_ENABLE_REG (field GPIO_ENABLE_DATA[15]).
4. Set the IO_MUX_GPIO15 register MCU_SEL field to 2 (GPIO function) and also set the FUN_IE bit (input
mode).
4.2.3 Simple GPIO Input
The GPIO_IN_REG/GPIO_IN1_REG register holds the input values of each GPIO pad.
The input value of any GPIO pin can be read at any time without configuring the GPIO Matrix for a particular
peripheral signal. However, it is necessary to enable the input in the IO_MUX by setting the FUN_IE bit in the
IO_MUX_x_REG register corresponding to pad X, as mentioned in Section 4.2.2.
4.3 Peripheral Output via GPIO Matrix
4.3.1 Summary
To output a signal from a peripheral via the GPIO Matrix, the GPIO Matrix is configured to route the peripheral
output signal (0-18, 23-37, 61-121, 140-125, 224-228) to one of the 28 GPIOs (0-19, 21-23, 25-27,
32-33).
The output signal is routed from the peripheral into the GPIO Matrix. It is then routed into the IO_MUX, which is
configured to set the chosen pad to ”GPIO” function. This causes the output GPIO signal to be connected to the
pad.
Note:
The peripheral output signals 224 to 228 can be configured to be routed in from one GPIO and output directly from another
GPIO.
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4. IO_MUX and GPIO Matrix
GPIO_FUNCx_OUT_SEL
signal0_out
signal1_out
signal2_out
signal3_out
signal228_out
GPIO_OUT_DATA bit x
0
1
2
3
228
256 (0x100)256sdfsdfasdfgas
GPIOx_out
In GPIO matrix
In IO MUX
0 (FUNC)
1 (FUNC)
2 (GPIO)
I/O Pad x
GPIO X out
MCU_SEL
FUN_OE = 1
4.3.2 Functional Description
One of the 176 output signals can be selected to go through the GPIO matrix into the IO_MUX and then to a pad.
Figure 9 illustrates the configuration.
Figure 9: Output via GPIO Matrix
To output peripheral signal Y to particular GPIO pad X, follow these steps:
1. Configure the GPIO_FUNCx_OUT_SEL_CFG register and GPIO_ENABLE_DATA[x] field corresponding to
GPIO X in the GPIO Matrix:
• Set the GPIO_FUNCx_OUT_SEL field in GPIO_FUNCx_OUT_SEL_CFG to the numeric index (Y) of
desired peripheral output signal Y.
• If the signal should always be enabled as an output, set the GPIO_FUNCx_OEN_SEL bit in the
GPIO_FUNCx_OUT_SEL_CFG register and the GPIO_ENABLE_DATA[x] field in the
GPIO_ENABLE_REG register corresponding to GPIO pad X. To have the output enable signal decided
by internal logic, clear the GPIO_FUNCx_OEN_SEL bit instead.
• The GPIO_ENABLE_DATA[x] field is a bit in either GPIO_ENABLE_REG (GPIOs 0-31) or
GPIO_ENABLE1_REG (GPIOs 32-39). Clear this bit to disable the output driver for the GPIO pad.
2. For an open drain output, set the GPIO_PINx_PAD_DRIVER bit in the GPIO_PINx register corresponding to
GPIO pad X. For push/pull mode (default), clear this bit.
3. Configure the IO_MUX to select the GPIO Matrix. Set the IO_MUX_x_REG register corresponding to GPIO
pad X as follows:
• Set the function field (MCU_SEL) to the IO_MUX function corresponding to GPIO X (this is Function
#3—numeric value 2—for all pins).
• Set the FUN_DRV field to the desired value for output strength (0-3). The higher the drive strength, the
more current can be sourced/sunk from the pin.
• If using open drain mode, set/clear the FUN_WPU and FUN_WPD bits to enable/disable the internal
pull-up/down resistors.
Espressif Systems 47 ESP32 Technical Reference Manual V4.0
4. IO_MUX and GPIO Matrix
Notes:
• The output signal from a single peripheral can be sent to multiple pads simultaneously.
• Only the 28 GPIOs can be used as outputs.
• The output signal can be inverted by setting the GPIO_FUNCx_OUT_INV_SEL bit.
4.3.3 Simple GPIO Output
The GPIO Matrix can also be used for simple GPIO output – setting a bit in the GPIO_OUT_DATA register will
write to the corresponding GPIO pad.
To configure a pad as simple GPIO output, the GPIO Matrix GPIO_FUNCx_OUT_SEL register is configured with a
special peripheral index value (0x100).
4.4 Direct I/O via IO_MUX
4.4.1 Summary
Some high speed digital functions (Ethernet, SDIO, SPI, JTAG, UART) can bypass the GPIO Matrix for better
high-frequency digital performance. In this case, the IO_MUX is used to connect these pads directly to the
peripheral.
Selecting this option is less flexible than using the GPIO Matrix, as the IO_MUX register for each GPIO pad can
only select from a limited number of functions. However, better high-frequency digital performance will be
maintained.
4.4.2 Functional Description
Two registers must be configured in order to bypass the GPIO Matrix for peripheral I/O:
1. IO_MUX for the GPIO pad must be set to the required pad function. (Please refer to section 4.10 for a list of
pad functions.)
2. For inputs, the SIG_IN_SEL register must be set to route the input directly to the peripheral.
4.5 RTC IO_MUX for Low Power and Analog I/O
4.5.1 Summary
18 GPIO pads have low power capabilities (RTC domain) and analog functions which are handled by the RTC
subsystem of ESP32. The IO_MUX and GPIO Matrix are not used for these functions; rather, the RTC_MUX is
used to redirect the I/O to the RTC subsystem.
When configured as RTC GPIOs, the output pads can still retain the output level value when the chip is in
Deep-sleep mode, and the input pads can wake up the chip from Deep-sleep.
Section 4.11 has a list of RTC_MUX pins and their functions.
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4. IO_MUX and GPIO Matrix
4.5.2 Functional Description
Each pad with analog and RTC functions is controlled by the RTC_IO_TOUCH_PADx_TO_GPIO bit in the
RTC_GPIO_PINx register. By default this bit is set to 1, routing all I/O via the IO_MUX subsystem as described in
earlier subsections.
If the RTC_IO_TOUCH_PADx_TO_GPIO bit is cleared, then I/O to and from that pad is routed to the RTC
subsystem. In this mode, the RTC_GPIO_PINx register is used for digital I/O and the analog features of the pad
are also available. See Section 4.11 for a list of RTC pin functions.
See 4.11 for a table mapping GPIO pads to their RTC equivalent pins and analog functions. Note that the
RTC_IO_PINx registers use the RTC GPIO pin numbering, not the GPIO pad numbering.
4.6 Light-sleep Mode Pin Functions
Pins can have different functions when the ESP32 is in Light-sleep mode. If the SLP_SEL bit in the IO_MUX
register for a GPIO pad is set to 1, a different set of registers is used to control the pad when the ESP32 is in
Light-sleep mode:
Table 16: IO_MUX Light-sleep Pin Function Registers
IO_MUX Function
Output Drive Strength FUN_DRV MCU_DRV
Pullup Resistor FUN_WPU MCU_WPU
Pulldown Resistor FUN_WPD MCU_WPD
Output Enable (From GPIO Matrix _OEN field) MCU_OE
If SLP_SEL is set to 0, the pin functions remain the same in both normal execution and Light-sleep mode.
Normal Execution Light-sleep Mode
OR SLP_SEL = 0 AND SLP_SEL = 1
4.7 Pad Hold Feature
Each IO pad (including the RTC pads) has an individual hold function controlled by a RTC register. When the pad
is set to hold, the state is latched at that moment and will not change no matter how the internal signals change
or how the IO_MUX configuration or GPIO configuration is modified. Users can use the hold function for the pads
to retain the pad state through a core reset and system reset triggered by watchdog time-out or Deep-sleep
events.
Note:
• For digital pads, to maintain the pad’s input/output status in Deep-sleep mode, you can set
REG_DG_PAD_FORCE_UNHOLD to 0 before powering down.
For RTC pads, the input and output values are controlled by the corresponding bits of register
RTC_CNTL_HOLD_FORCE_REG, and you can set it to 1 to hold the value or set it to 0 to unhold the value.
• For digital pads, to disable the hold function after the chip is woken up, you can setREG_DG_PAD_FORCE_UNHOLD
to 1. To maintain the hold function of the pad, you can change the corresponding bit in the register by setting
RTC_CNTL_HOLD_FORCE_REG to 1.
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4. IO_MUX and GPIO Matrix
32K_XP 12
VDET_2 11
10
9
8
7
6
5
4
3
2
1
VDET_1
CHIP_PU
SENSOR_VN
SENSOR_CAPN
SENSOR_CAPP
SENSOR_VP
VDD3P3
VDD3P3
LNA_IN
VDDA
25
26
27
28
29
30
31
32
33
34
35
36
GPIO16
VDD_SDIO
GPIO5
VDD3P3_CPU37
GPIO1938
39
40
41
42
43
44
45
46
47
48
GPIO22
U0RXD
U0TXD
GPIO21
XTAL_N
XTAL_P
VDDA
CAP2
CAP1
GPIO2
24
MTDO
23
22
21
20
19
18
17
16
15
14
13
MTCK
VDD3P3_RTC
MTDI
MTMS
GPIO27
GPIO26
GPIO25
32K_XN
SD_DATA_2
SD_DATA_3
SD_CMD
SD_CLK
SD_DATA_0
SD_DATA_1
GPIO4
GPIO0
GPIO23
GPIO18
VDDA
GPIO17
ESP32
49 GND
Analog pads
Pads powered by VDD3P3_CPU
Pads powered by VDD_SDIO
Pads powered by VDD3P3_RTC
10
9
8
7
6
5
4
3
2
1
VDET_1
CHIP_PU
SENSOR_VN
SENSOR_CAPN
SENSOR_CAPP
SENSOR_VP
VDD3P3
VDD3P3
LNA_IN
VDDA
25
26
27
28
29
30
31
32
33
34
GPIO16
VDD_SDIO
GPIO5
VDD3P3_CPU
GPIO19
39
40
41
42
43
44
45
46
47
48
GPIO22
U0RXD
U0TXD
GPIO21
XTAL_N
XTAL_P
VDDA
CAP2
CAP1
GPIO2
24
MTDO
23
22
21
20
19
18
17
16
15
MTCK
VDD3P3_RTC
MTDI
MTMS
GPIO27
GPIO26
GPIO25
32K_XN
SD_DATA_2
SD_DATA_3
SD_CMD
SD_CLK
SD_DATA_0
SD_DATA_1
GPIO4
GPIO0
VDDA
GPIO1732K_XP
VDET_2
GPIO18
GPIO23
11
12
13
14
35
36
37
38
ESP32
49 GND
Analog pads
Pads powered by VDD3P3_CPU
Pads powered by VDD_SDIO
Pads powered by VDD3P3_RTC
4.8 I/O Pad Power Supplies
Figure 10 and 11 show the IO pad power supplies.
Figure 10: ESP32 I/O Pad Power Sources (QFN 6*6, Top View)
Espressif Systems 50 ESP32 Technical Reference Manual V4.0
Figure 11: ESP32 I/O Pad Power Sources (QFN 5*5, Top View)
4. IO_MUX and GPIO Matrix
• Pads marked blue are RTC pads that have their individual analog function and can also act as normal
digital IO pads. For details, please see Section 4.11.
• Pads marked yellow and green have digital functions only.
• Pads marked green can be powered externally or internally via VDD_SDIO (see below).
4.8.1 VDD_SDIO Power Domain
VDD_SDIO can source or sink current, allowing this power domain to be powered externally or internally. To
power VDD_SDIO externally, apply the same power supply of VDD3P3_RTC to the VDD_SDIO pad.
Without an external power supply, the internal regulator will supply VDD_SDIO. The VDD_SDIO voltage can be
configured to be either 1.8V or the same as VDD3P3_RTC, depending on the state of the MTDI pad at reset – a
high level configures 1.8V and a low level configures the voltage to be the same as VDD3P3_RTC. Setting the
efuse bit determines the default voltage of the VDD_SDIO. In addition, software can change the voltage of the
VDD_SDIO by configuring register bits.
4.9 Peripheral Signal List
Table 17 contains a list of Peripheral Input/Output signals used by the GPIO Matrix:
Table 17: GPIO Matrix Peripheral Signals
Signal Input Signal Output Signal Direct I/O in IO_MUX
0 SPICLK_in SPICLK_out YES
1 SPIQ_in SPIQ_out YES
2 SPID_in SPID_out YES
3 SPIHD_in SPIHD_out YES
4 SPIWP_in SPIWP_out YES
5 SPICS0_in SPICS0_out YES
6 SPICS1_in SPICS1_out -
7 SPICS2_in SPICS2_out -
8 HSPICLK_in HSPICLK_out YES
9 HSPIQ_in HSPIQ_out YES
10 HSPID_in HSPID_out YES
11 HSPICS0_in HSPICS0_out YES
12 HSPIHD_in HSPIHD_out YES
13 HSPIWP_in HSPIWP_out YES
14 U0RXD_in U0TXD_out YES
15 U0CTS_in U0RTS_out YES
16 U0DSR_in U0DTR_out -
17 U1RXD_in U1TXD_out YES
18 U1CTS_in U1RTS_out YES
23 I2S0O_BCK_in I2S0O_BCK_out -
24 I2S1O_BCK_in I2S1O_BCK_out -
25 I2S0O_WS_in I2S0O_WS_out -
26 I2S1O_WS_in I2S1O_WS_out -
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4. IO_MUX and GPIO Matrix
Signal Input Signal Output Signal Direct I/O in IO_MUX
27 I2S0I_BCK_in I2S0I_BCK_out -
28 I2S0I_WS_in I2S0I_WS_out -
29 I2CEXT0_SCL_in I2CEXT0_SCL_out -
30 I2CEXT0_SDA_in I2CEXT0_SDA_out -
31 pwm0_sync0_in sdio_tohost_int_out -
32 pwm0_sync1_in pwm0_out0a -
33 pwm0_sync2_in pwm0_out0b -
34 pwm0_f0_in pwm0_out1a -
35 pwm0_f1_in pwm0_out1b -
36 pwm0_f2_in pwm0_out2a -
37 - pwm0_out2b -
39 pcnt_sig_ch0_in0 - -
40 pcnt_sig_ch1_in0 - -
41 pcnt_ctrl_ch0_in0 - -
42 pcnt_ctrl_ch1_in0 - -
43 pcnt_sig_ch0_in1 - -
44 pcnt_sig_ch1_in1 - -
45 pcnt_ctrl_ch0_in1 - -
46 pcnt_ctrl_ch1_in1 - -
47 pcnt_sig_ch0_in2 - -
48 pcnt_sig_ch1_in2 - -
49 pcnt_ctrl_ch0_in2 - -
50 pcnt_ctrl_ch1_in2 - -
51 pcnt_sig_ch0_in3 - -
52 pcnt_sig_ch1_in3 - -
53 pcnt_ctrl_ch0_in3 - -
54 pcnt_ctrl_ch1_in3 - -
55 pcnt_sig_ch0_in4 - -
56 pcnt_sig_ch1_in4 - -
57 pcnt_ctrl_ch0_in4 - -
58 pcnt_ctrl_ch1_in4 - -
61 HSPICS1_in HSPICS1_out -
62 HSPICS2_in HSPICS2_out -
63 VSPICLK_in VSPICLK_out_mux YES
64 VSPIQ_in VSPIQ_out YES
65 VSPID_in VSPID_out YES
66 VSPIHD_in VSPIHD_out YES
67 VSPIWP_in VSPIWP_out YES
68 VSPICS0_in VSPICS0_out YES
69 VSPICS1_in VSPICS1_out -
70 VSPICS2_in VSPICS2_out -
71 pcnt_sig_ch0_in5 ledc_hs_sig_out0 -
72 pcnt_sig_ch1_in5 ledc_hs_sig_out1 -
73 pcnt_ctrl_ch0_in5 ledc_hs_sig_out2 -
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4. IO_MUX and GPIO Matrix
Signal Input Signal Output Signal Direct I/O in IO_MUX
74 pcnt_ctrl_ch1_in5 ledc_hs_sig_out3 -
75 pcnt_sig_ch0_in6 ledc_hs_sig_out4 -
76 pcnt_sig_ch1_in6 ledc_hs_sig_out5 -
77 pcnt_ctrl_ch0_in6 ledc_hs_sig_out6 -
78 pcnt_ctrl_ch1_in6 ledc_hs_sig_out7 -
79 pcnt_sig_ch0_in7 ledc_ls_sig_out0 -
80 pcnt_sig_ch1_in7 ledc_ls_sig_out1 -
81 pcnt_ctrl_ch0_in7 ledc_ls_sig_out2 -
82 pcnt_ctrl_ch1_in7 ledc_ls_sig_out3 -
83 rmt_sig_in0 ledc_ls_sig_out4 -
84 rmt_sig_in1 ledc_ls_sig_out5 -
85 rmt_sig_in2 ledc_ls_sig_out6 -
86 rmt_sig_in3 ledc_ls_sig_out7 -
87 rmt_sig_in4 rmt_sig_out0 -
88 rmt_sig_in5 rmt_sig_out1 -
89 rmt_sig_in6 rmt_sig_out2 -
90 rmt_sig_in7 rmt_sig_out3 -
91 - rmt_sig_out4 -
92 - rmt_sig_out5 -
93 - rmt_sig_out6 -
94 - rmt_sig_out7 -
95 I2CEXT1_SCL_in I2CEXT1_SCL_out -
96 I2CEXT1_SDA_in I2CEXT1_SDA_out -
97 host_card_detect_n_1 host_ccmd_od_pullup_en_n -
98 host_card_detect_n_2 host_rst_n_1 -
99 host_card_write_prt_1 host_rst_n_2 -
100 host_card_write_prt_2 gpio_sd0_out -
101 host_card_int_n_1 gpio_sd1_out -
102 host_card_int_n_2 gpio_sd2_out -
103 pwm1_sync0_in gpio_sd3_out -
104 pwm1_sync1_in gpio_sd4_out -
105 pwm1_sync2_in gpio_sd5_out -
106 pwm1_f0_in gpio_sd6_out -
107 pwm1_f1_in gpio_sd7_out -
108 pwm1_f2_in pwm1_out0a -
109 pwm0_cap0_in pwm1_out0b -
110 pwm0_cap1_in pwm1_out1a -
111 pwm0_cap2_in pwm1_out1b -
112 pwm1_cap0_in pwm1_out2a -
113 pwm1_cap1_in pwm1_out2b -
114 pwm1_cap2_in pwm2_out1h -
115 pwm2_flta pwm2_out1l -
116 pwm2_fltb pwm2_out2h -
117 pwm2_cap1_in pwm2_out2l -
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4. IO_MUX and GPIO Matrix
Signal Input Signal Output Signal Direct I/O in IO_MUX
118 pwm2_cap2_in pwm2_out3h -
119 pwm2_cap3_in pwm2_out3l -
120 pwm3_flta pwm2_out4h -
121 pwm3_fltb pwm2_out4l -
122 pwm3_cap1_in - -
123 pwm3_cap2_in - -
124 pwm3_cap3_in - -
140 I2S0I_DATA_in0 I2S0O_DATA_out0 -
141 I2S0I_DATA_in1 I2S0O_DATA_out1 -
142 I2S0I_DATA_in2 I2S0O_DATA_out2 -
143 I2S0I_DATA_in3 I2S0O_DATA_out3 -
144 I2S0I_DATA_in4 I2S0O_DATA_out4 -
145 I2S0I_DATA_in5 I2S0O_DATA_out5 -
146 I2S0I_DATA_in6 I2S0O_DATA_out6 -
147 I2S0I_DATA_in7 I2S0O_DATA_out7 -
148 I2S0I_DATA_in8 I2S0O_DATA_out8 -
149 I2S0I_DATA_in9 I2S0O_DATA_out9 -
150 I2S0I_DATA_in10 I2S0O_DATA_out10 -
151 I2S0I_DATA_in11 I2S0O_DATA_out11 -
152 I2S0I_DATA_in12 I2S0O_DATA_out12 -
153 I2S0I_DATA_in13 I2S0O_DATA_out13 -
154 I2S0I_DATA_in14 I2S0O_DATA_out14 -
155 I2S0I_DATA_in15 I2S0O_DATA_out15 -
156 - I2S0O_DATA_out16 -
157 - I2S0O_DATA_out17 -
158 - I2S0O_DATA_out18 -
159 - I2S0O_DATA_out19 -
160 - I2S0O_DATA_out20 -
161 - I2S0O_DATA_out21 -
162 - I2S0O_DATA_out22 -
163 - I2S0O_DATA_out23 -
164 I2S1I_BCK_in I2S1I_BCK_out -
165 I2S1I_WS_in I2S1I_WS_out -
166 I2S1I_DATA_in0 I2S1O_DATA_out0 -
167 I2S1I_DATA_in1 I2S1O_DATA_out1 -
168 I2S1I_DATA_in2 I2S1O_DATA_out2 -
169 I2S1I_DATA_in3 I2S1O_DATA_out3 -
170 I2S1I_DATA_in4 I2S1O_DATA_out4 -
171 I2S1I_DATA_in5 I2S1O_DATA_out5 -
172 I2S1I_DATA_in6 I2S1O_DATA_out6 -
173 I2S1I_DATA_in7 I2S1O_DATA_out7 -
174 I2S1I_DATA_in8 I2S1O_DATA_out8 -
175 I2S1I_DATA_in9 I2S1O_DATA_out9 -
176 I2S1I_DATA_in10 I2S1O_DATA_out10 -
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4. IO_MUX and GPIO Matrix
Signal Input Signal Output Signal Direct I/O in IO_MUX
177 I2S1I_DATA_in11 I2S1O_DATA_out11 -
178 I2S1I_DATA_in12 I2S1O_DATA_out12 -
179 I2S1I_DATA_in13 I2S1O_DATA_out13 -
180 I2S1I_DATA_in14 I2S1O_DATA_out14 -
181 I2S1I_DATA_in15 I2S1O_DATA_out15 -
182 - I2S1O_DATA_out16 -
183 - I2S1O_DATA_out17 -
184 - I2S1O_DATA_out18 -
185 - I2S1O_DATA_out19 -
186 - I2S1O_DATA_out20 -
187 - I2S1O_DATA_out21 -
188 - I2S1O_DATA_out22 -
189 - I2S1O_DATA_out23 -
190 I2S0I_H_SYNC pwm3_out1h -
191 I2S0I_V_SYNC pwm3_out1l -
192 I2S0I_H_ENABLE pwm3_out2h -
193 I2S1I_H_SYNC pwm3_out2l -
194 I2S1I_V_SYNC pwm3_out3h -
195 I2S1I_H_ENABLE pwm3_out3l -
196 - pwm3_out4h -
197 - pwm3_out4l -
198 U2RXD_in U2TXD_out YES
199 U2CTS_in U2RTS_out YES
200 emac_mdc_i emac_mdc_o -
201 emac_mdi_i emac_mdo_o -
202 emac_crs_i emac_crs_o -
203 emac_col_i emac_col_o -
204 pcmfsync_in bt_audio0_irq -
205 pcmclk_in bt_audio1_irq -
206 pcmdin bt_audio2_irq -
207 - ble_audio0_irq -
208 - ble_audio1_irq -
209 - ble_audio2_irq -
210 - pcmfsync_out -
211 - pcmclk_out -
212 - pcmdout -
213 - ble_audio_sync0_p -
214 - ble_audio_sync1_p -
215 - ble_audio_sync2_p -
224 - sig_in_func224 -
225 - sig_in_func225 -
226 - sig_in_func226 -
227 - sig_in_func227 -
228 - sig_in_func228 -
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4. IO_MUX and GPIO Matrix
Direct I/O in IO_MUX ”YES” means that this signal is also available directly via IO_MUX. To apply the GPIO
Matrix to these signals, their corresponding SIG_IN_SEL register must be cleared.
4.10 IO_MUX Pad List
Table 18 shows the IO_MUX functions for each I/O pad:
Table 18: IO_MUX Pad Summary
GPIO Pad Name Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Reset Notes
0 GPIO0 GPIO0 CLK_OUT1 GPIO0 - - EMAC_TX_CLK 3 R
1 U0TXD U0TXD CLK_OUT3 GPIO1 - - EMAC_RXD2 3 -
2 GPIO2 GPIO2 HSPIWP GPIO2 HS2_DATA0 SD_DATA0 - 2 R
3 U0RXD U0RXD CLK_OUT2 GPIO3 - - - 3 -
4 GPIO4 GPIO4 HSPIHD GPIO4 HS2_DATA1 SD_DATA1 EMAC_TX_ER 2 R
5 GPIO5 GPIO5 VSPICS0 GPIO5 HS1_DATA6 - EMAC_RX_CLK 3 -
6 SD_CLK SD_CLK SPICLK GPIO6 HS1_CLK U1CTS - 3 -
7 SD_DATA_0 SD_DATA0 SPIQ GPIO7 HS1_DATA0 U2RTS - 3 -
8 SD_DATA_1 SD_DATA1 SPID GPIO8 HS1_DATA1 U2CTS - 3 -
9 SD_DATA_2 SD_DATA2 SPIHD GPIO9 HS1_DATA2 U1RXD - 3 -
10 SD_DATA_3 SD_DATA3 SPIWP GPIO10 HS1_DATA3 U1TXD - 3 -
11 SD_CMD SD_CMD SPICS0 GPIO11 HS1_CMD U1RTS - 3 -
12 MTDI MTDI HSPIQ GPIO12 HS2_DATA2 SD_DATA2 EMAC_TXD3 2 R
13 MTCK MTCK HSPID GPIO13 HS2_DATA3 SD_DATA3 EMAC_RX_ER 1 R
14 MTMS MTMS HSPICLK GPIO14 HS2_CLK SD_CLK EMAC_TXD2 1 R
15 MTDO MTDO HSPICS0 GPIO15 HS2_CMD SD_CMD EMAC_RXD3 3 R
16 GPIO16 GPIO16 - GPIO16 HS1_DATA4 U2RXD EMAC_CLK_OUT 1 -
17 GPIO17 GPIO17 - GPIO17 HS1_DATA5 U2TXD EMAC_CLK_180 1 -
18 GPIO18 GPIO18 VSPICLK GPIO18 HS1_DATA7 - - 1 -
19 GPIO19 GPIO19 VSPIQ GPIO19 U0CTS - EMAC_TXD0 1 -
21 GPIO21 GPIO21 VSPIHD GPIO21 - - EMAC_TX_EN 1 -
22 GPIO22 GPIO22 VSPIWP GPIO22 U0RTS - EMAC_TXD1 1 -
23 GPIO23 GPIO23 VSPID GPIO23 HS1_STROBE - - 1 -
25 GPIO25 GPIO25 - GPIO25 - - EMAC_RXD0 0 R
26 GPIO26 GPIO26 - GPIO26 - - EMAC_RXD1 0 R
27 GPIO27 GPIO27 - GPIO27 - - EMAC_RX_DV 1 R
32 32K_XP GPIO32 - GPIO32 - - - 0 R
33 32K_XN GPIO33 - GPIO33 - - - 0 R
34 VDET_1 GPIO34 - GPIO34 - - - 0 R, I
35 VDET_2 GPIO35 - GPIO35 - - - 0 R, I
36 SENSOR_VP GPIO36 - GPIO36 - - - 0 R, I
37 SENSOR_CAPP GPIO37 - GPIO37 - - - 0 R, I
38 SENSOR_CAPN GPIO38 - GPIO38 - - - 0 R, I
39 SENSOR_VN GPIO39 - GPIO39 - - - 0 R, I
Reset Configurations
”Reset” column shows each pad’s default configurations after reset:
• 0 - IE=0 (input disabled).
• 1 - IE=1 (input enabled).
• 2 - IE=1, WPD=1 (input enabled, pulldown resistor).
• 3 - IE=1, WPU=1 (input enabled, pullup resistor).
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Notes
• R - Pad has RTC/analog functions via RTC_MUX.
• I - Pad can only be configured as input GPIO.
Please refer to the ESP32 Pin Lists in ESP32 Datasheet for more details.
4.11 RTC_MUX Pin List
Table 19 shows the RTC pins and how they correspond to GPIO pads:
Table 19: RTC_MUX Pin Summary
RTC GPIO Num GPIO Num Pad Name
0 36 SENSOR_VP ADC_H ADC1_CH0 -
1 37 SENSOR_CAPP ADC_H ADC1_CH1 -
2 38 SENSOR_CAPN ADC_H ADC1_CH2 -
3 39 SENSOR_VN ADC_H ADC1_CH3 -
4 34 VDET_1 - ADC1_CH6 -
5 35 VDET_2 - ADC1_CH7 -
6 25 GPIO25 DAC_1 ADC2_CH8 -
7 26 GPIO26 DAC_2 ADC2_CH9 -
8 33 32K_XN XTAL_32K_N ADC1_CH5 TOUCH8
9 32 32K_XP XTAL_32K_P ADC1_CH4 TOUCH9
10 4 GPIO4 - ADC2_CH0 TOUCH0
11 0 GPIO0 - ADC2_CH1 TOUCH1
12 2 GPIO2 - ADC2_CH2 TOUCH2
13 15 MTDO - ADC2_CH3 TOUCH3
14 13 MTCK - ADC2_CH4 TOUCH4
15 12 MTDI - ADC2_CH5 TOUCH5
16 14 MTMS - ADC2_CH6 TOUCH6
17 27 GPIO27 - ADC2_CH7 TOUCH7
1 2 3
Analog Function
4.12 Register Summary
Name Description Address Access
GPIO_OUT_REG GPIO 0-31 output register 0x3FF44004 R/W
GPIO_OUT_W1TS_REG GPIO 0-31 output register_W1TS 0x3FF44008 WO
GPIO_OUT_W1TC_REG GPIO 0-31 output register_W1TC 0x3FF4400C WO
GPIO_OUT1_REG GPIO 32-39 output register 0x3FF44010 R/W
GPIO_OUT1_W1TS_REG GPIO 32-39 output bit set register 0x3FF44014 WO
GPIO_OUT1_W1TC_REG GPIO 32-39 output bit clear register 0x3FF44018 WO
GPIO_ENABLE_REG GPIO 0-31 output enable register 0x3FF44020 R/W
GPIO_ENABLE_W1TS_REG GPIO 0-31 output enable register_W1TS 0x3FF44024 WO
GPIO_ENABLE_W1TC_REG GPIO 0-31 output enable register_W1TC 0x3FF44028 WO
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Name Description Address Access
GPIO_ENABLE1_REG GPIO 32-39 output enable register 0x3FF4402C R/W
GPIO_ENABLE1_W1TS_REG GPIO 32-39 output enable bit set register 0x3FF44030 WO
GPIO_ENABLE1_W1TC_REG GPIO 32-39 output enable bit clear register 0x3FF44034 WO
GPIO_STRAP_REG Bootstrap pin value register 0x3FF44038 RO
GPIO_IN_REG GPIO 0-31 input register 0x3FF4403C RO
GPIO_IN1_REG GPIO 32-39 input register 0x3FF44040 RO
GPIO_STATUS_REG GPIO 0-31 interrupt status register 0x3FF44044 R/W
GPIO_STATUS_W1TS_REG GPIO 0-31 interrupt status register_W1TS 0x3FF44048 WO
GPIO_STATUS_W1TC_REG GPIO 0-31 interrupt status register_W1TC 0x3FF4404C WO
GPIO_STATUS1_REG GPIO 32-39 interrupt status register1 0x3FF44050 R/W
GPIO_STATUS1_W1TS_REG GPIO 32-39 interrupt status bit set register 0x3FF44054 WO
GPIO_STATUS1_W1TC_REG GPIO 32-39 interrupt status bit clear register 0x3FF44058 WO
GPIO_ACPU_INT_REG GPIO 0-31 APP_CPU interrupt status 0x3FF44060 RO
GPIO_ACPU_NMI_INT_REG
GPIO 0-31 APP_CPU non-maskable interrupt
status
0x3FF44064 RO
GPIO_PCPU_INT_REG GPIO 0-31 PRO_CPU interrupt status 0x3FF44068 RO
GPIO_PCPU_NMI_INT_REG
GPIO 0-31 PRO_CPU non-maskable interrupt
status
0x3FF4406C RO
GPIO_ACPU_INT1_REG GPIO 32-39 APP_CPU interrupt status 0x3FF44074 RO
GPIO_ACPU_NMI_INT1_REG
GPIO 32-39 APP_CPU non-maskable interrupt
status
0x3FF44078 RO
GPIO_PCPU_INT1_REG GPIO 32-39 PRO_CPU interrupt status 0x3FF4407C RO
GPIO_PCPU_NMI_INT1_REG
GPIO 32-39 PRO_CPU non-maskable interrupt
status
0x3FF44080 RO
GPIO_PIN0_REG Configuration for GPIO pin 0 0x3FF44088 R/W
GPIO_PIN1_REG Configuration for GPIO pin 1 0x3FF4408C R/W
GPIO_PIN2_REG Configuration for GPIO pin 2 0x3FF44090 R/W
... ...
GPIO_PIN38_REG Configuration for GPIO pin 38 0x3FF44120 R/W
GPIO_PIN39_REG Configuration for GPIO pin 39 0x3FF44124 R/W
GPIO_FUNC0_IN_SEL_CFG_REG Peripheral function 0 input selection register 0x3FF44130 R/W
GPIO_FUNC1_IN_SEL_CFG_REG Peripheral function 1 input selection register 0x3FF44134 R/W
... ...
GPIO_FUNC254_IN_SEL_CFG_REG Peripheral function 254 input selection register 0x3FF44528 R/W
GPIO_FUNC255_IN_SEL_CFG_REG Peripheral function 255 input selection register 0x3FF4452C R/W
GPIO_FUNC0_OUT_SEL_CFG_REG Peripheral output selection for GPIO 0 0x3FF44530 R/W
GPIO_FUNC1_OUT_SEL_CFG_REG Peripheral output selection for GPIO 1 0x3FF44534 R/W
... ...
GPIO_FUNC38_OUT_SEL_CFG_REG Peripheral output selection for GPIO 38 0x3FF445C8 R/W
GPIO_FUNC39_OUT_SEL_CFG_REG Peripheral output selection for GPIO 39 0x3FF445CC R/W
Name Description Address Access
IO_MUX_PIN_CTRL Clock output configuration register 0x3FF49000 R/W
IO_MUX_GPIO36_REG Configuration register for pad GPIO36 0x3FF49004 R/W
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Name Description Address Access
IO_MUX_GPIO37_REG Configuration register for pad GPIO37 0x3FF49008 R/W
IO_MUX_GPIO38_REG Configuration register for pad GPIO38 0x3FF4900C R/W
IO_MUX_GPIO39_REG Configuration register for pad GPIO39 0x3FF49010 R/W
IO_MUX_GPIO34_REG Configuration register for pad GPIO34 0x3FF49014 R/W
IO_MUX_GPIO35_REG Configuration register for pad GPIO35 0x3FF49018 R/W
IO_MUX_GPIO32_REG Configuration register for pad GPIO32 0x3FF4901C R/W
IO_MUX_GPIO33_REG Configuration register for pad GPIO33 0x3FF49020 R/W
IO_MUX_GPIO25_REG Configuration register for pad GPIO25 0x3FF49024 R/W
IO_MUX_GPIO26_REG Configuration register for pad GPIO26 0x3FF49028 R/W
IO_MUX_GPIO27_REG Configuration register for pad GPIO27 0x3FF4902C R/W
IO_MUX_MTMS_REG Configuration register for pad MTMS 0x3FF49030 R/W
IO_MUX_MTDI_REG Configuration register for pad MTDI 0x3FF49034 R/W
IO_MUX_MTCK_REG Configuration register for pad MTCK 0x3FF49038 R/W
IO_MUX_MTDO_REG Configuration register for pad MTDO 0x3FF4903C R/W
IO_MUX_GPIO2_REG Configuration register for pad GPIO2 0x3FF49040 R/W
IO_MUX_GPIO0_REG Configuration register for pad GPIO0 0x3FF49044 R/W
IO_MUX_GPIO4_REG Configuration register for pad GPIO4 0x3FF49048 R/W
IO_MUX_GPIO16_REG Configuration register for pad GPIO16 0x3FF4904C R/W
IO_MUX_GPIO17_REG Configuration register for pad GPIO17 0x3FF49050 R/W
IO_MUX_SD_DATA2_REG Configuration register for pad SD_DATA2 0x3FF49054 R/W
IO_MUX_SD_DATA3_REG Configuration register for pad SD_DATA3 0x3FF49058 R/W
IO_MUX_SD_CMD_REG Configuration register for pad SD_CMD 0x3FF4905C R/W
IO_MUX_SD_CLK_REG Configuration register for pad SD_CLK 0x3FF49060 R/W
IO_MUX_SD_DATA0_REG Configuration register for pad SD_DATA0 0x3FF49064 R/W
IO_MUX_SD_DATA1_REG Configuration register for pad SD_DATA1 0x3FF49068 R/W
IO_MUX_GPIO5_REG Configuration register for pad GPIO5 0x3FF4906C R/W
IO_MUX_GPIO18_REG Configuration register for pad GPIO18 0x3FF49070 R/W
IO_MUX_GPIO19_REG Configuration register for pad GPIO19 0x3FF49074 R/W
IO_MUX_GPIO20_REG Configuration register for pad GPIO20 0x3FF49078 R/W
IO_MUX_GPIO21_REG Configuration register for pad GPIO21 0x3FF4907C R/W
IO_MUX_GPIO22_REG Configuration register for pad GPIO22 0x3FF49080 R/W
IO_MUX_U0RXD_REG Configuration register for pad U0RXD 0x3FF49084 R/W
IO_MUX_U0TXD_REG Configuration register for pad U0TXD 0x3FF49088 R/W
IO_MUX_GPIO23_REG Configuration register for pad GPIO23 0x3FF4908C R/W
IO_MUX_GPIO24_REG Configuration register for pad GPIO24 0x3FF49090 R/W
Name Description Address Access
GPIO configuration / data registers
RTCIO_RTC_GPIO_OUT_REG RTC GPIO output register 0x3FF48400 R/W
RTCIO_RTC_GPIO_OUT_W1TS_REG RTC GPIO output bit set register 0x3FF48404 WO
RTCIO_RTC_GPIO_OUT_W1TC_REG RTC GPIO output bit clear register 0x3FF48408 WO
RTCIO_RTC_GPIO_ENABLE_REG RTC GPIO output enable register 0x3FF4840C R/W
RTCIO_RTC_GPIO_ENABLE_W1TS_REG RTC GPIO output enable bit set register 0x3FF48410 WO
RTCIO_RTC_GPIO_ENABLE_W1TC_REG RTC GPIO output enable bit clear register 0x3FF48414 WO
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Name Description Address Access
RTCIO_RTC_GPIO_STATUS_REG RTC GPIO interrupt status register 0x3FF48418 WO
RTCIO_RTC_GPIO_STATUS_W1TS_REG RTC GPIO interrupt status bit set register 0x3FF4841C WO
RTCIO_RTC_GPIO_STATUS_W1TC_REG RTC GPIO interrupt status bit clear register 0x3FF48420 WO
RTCIO_RTC_GPIO_IN_REG RTC GPIO input register 0x3FF48424 RO
RTCIO_RTC_GPIO_PIN0_REG RTC configuration for pin 0 0x3FF48428 R/W
RTCIO_RTC_GPIO_PIN1_REG RTC configuration for pin 1 0x3FF4842C R/W
RTCIO_RTC_GPIO_PIN2_REG RTC configuration for pin 2 0x3FF48430 R/W
RTCIO_RTC_GPIO_PIN3_REG RTC configuration for pin 3 0x3FF48434 R/W
RTCIO_RTC_GPIO_PIN4_REG RTC configuration for pin 4 0x3FF48438 R/W
RTCIO_RTC_GPIO_PIN5_REG RTC configuration for pin 5 0x3FF4843C R/W
RTCIO_RTC_GPIO_PIN6_REG RTC configuration for pin 6 0x3FF48440 R/W
RTCIO_RTC_GPIO_PIN7_REG RTC configuration for pin 7 0x3FF48444 R/W
RTCIO_RTC_GPIO_PIN8_REG RTC configuration for pin 8 0x3FF48448 R/W
RTCIO_RTC_GPIO_PIN9_REG RTC configuration for pin 9 0x3FF4844C R/W
RTCIO_RTC_GPIO_PIN10_REG RTC configuration for pin 10 0x3FF48450 R/W
RTCIO_RTC_GPIO_PIN11_REG RTC configuration for pin 11 0x3FF48454 R/W
RTCIO_RTC_GPIO_PIN12_REG RTC configuration for pin 12 0x3FF48458 R/W
RTCIO_RTC_GPIO_PIN13_REG RTC configuration for pin 13 0x3FF4845C R/W
RTCIO_RTC_GPIO_PIN14_REG RTC configuration for pin 14 0x3FF48460 R/W
RTCIO_RTC_GPIO_PIN15_REG RTC configuration for pin 15 0x3FF48464 R/W
RTCIO_RTC_GPIO_PIN16_REG RTC configuration for pin 16 0x3FF48468 R/W
RTCIO_RTC_GPIO_PIN17_REG RTC configuration for pin 17 0x3FF4846C R/W
RTCIO_DIG_PAD_HOLD_REG RTC GPIO hold register 0x3FF48474 R/W
GPIO RTC function configuration registers
RTCIO_HALL_SENS_REG Hall sensor configuration 0x3FF48478 R/W
RTCIO_SENSOR_PADS_REG Sensor pads configuration register 0x3FF4847C R/W
RTCIO_ADC_PAD_REG ADC configuration register 0x3FF48480 R/W
RTCIO_PAD_DAC1_REG DAC1 configuration register 0x3FF48484 R/W
RTCIO_PAD_DAC2_REG DAC2 configuration register 0x3FF48488 R/W
RTCIO_XTAL_32K_PAD_REG 32KHz crystal pads configuration register 0x3FF4848C R/W
RTCIO_TOUCH_CFG_REG Touch sensor configuration register 0x3FF48490 R/W
RTCIO_TOUCH_PAD0_REG Touch pad configuration register 0x3FF48494 R/W
... ...
RTCIO_TOUCH_PAD9_REG Touch pad configuration register 0x3FF484B8 R/W
RTCIO_EXT_WAKEUP0_REG External wake up configuration register 0x3FF484BC R/W
RTCIO_XTL_EXT_CTR_REG Crystal power down enable GPIO source 0x3FF484C0 R/W
RTCIO_SAR_I2C_IO_REG RTC I2C pad selection 0x3FF484C4 R/W
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4.13 Registers
Register 4.1: GPIO_OUT_REG (0x0004)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
GPIO_OUT_REG GPIO0-31 output value. (R/W)
Register 4.2: GPIO_OUT_W1TS_REG (0x0008)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
GPIO_OUT_W1TS_REG GPIO0-31 output set register. For every bit that is 1 in the value written here,
the corresponding bit in GPIO_OUT_REG will be set. (WO)
Reset
Reset
Register 4.3: GPIO_OUT_W1TC_REG (0x000c)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Reset
GPIO_OUT_W1TC_REG GPIO0-31 output clear register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_OUT_REG will be cleared. (WO)
Register 4.4: GPIO_OUT1_REG (0x0010)
(reserved)
31 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
x x x x x x x x
GPIO_OUT_DATA
Reset
GPIO_OUT_DATA GPIO32-39 output value. (R/W)
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Register 4.5: GPIO_OUT1_W1TS_REG (0x0014)
(reserved)
31 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
x x x x x x x x
GPIO_OUT_DATA
Reset
GPIO_OUT_DATA GPIO32-39 output value set register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_OUT1_DATA will be set. (WO)
Register 4.6: GPIO_OUT1_W1TC_REG (0x0018)
(reserved)
31 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
x x x x x x x x
GPIO_OUT_DATA
Reset
GPIO_OUT_DATA GPIO32-39 output value clear register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_OUT1_DATA will be cleared. (WO)
Register 4.7: GPIO_ENABLE_REG (0x0020)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Reset
GPIO_ENABLE_REG GPIO0-31 output enable. (R/W)
Register 4.8: GPIO_ENABLE_W1TS_REG (0x0024)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Reset
GPIO_ENABLE_W1TS_REG GPIO0-31 output enable set register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_ENABLE will be set. (WO)
Register 4.9: GPIO_ENABLE_W1TC_REG (0x0028)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Reset
GPIO_ENABLE_W1TC_REG GPIO0-31 output enable clear register. For every bit that is 1 in the
value written here, the corresponding bit in GPIO_ENABLE will be cleared. (WO)
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Register 4.10: GPIO_ENABLE1_REG (0x002c)
(reserved)
31 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
x x x x x x x x
GPIO_ENABLE_DATA
Reset
GPIO_ENABLE_DATA GPIO32-39 output enable. (R/W)
Register 4.11: GPIO_ENABLE1_W1TS_REG (0x0030)
(reserved)
31 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
x x x x x x x x
GPIO_ENABLE_DATA
Reset
GPIO_ENABLE_DATA GPIO32-39 output enable set register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_ENABLE1 will be set. (WO)
Register 4.12: GPIO_ENABLE1_W1TC_REG (0x0034)
(reserved)
31 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
x x x x x x x x
GPIO_ENABLE_DATA
Reset
GPIO_ENABLE_DATA GPIO32-39 output enable clear register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_ENABLE1 will be cleared. (WO)
Register 4.13: GPIO_STRAP_REG (0x0038)
(reserved)
31 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 0
x x x x x x x x x x x x x x x x
GPIO_STRAPPING
Reset
GPIO_STRAPPING GPIO strapping results: Bit5-bit0 of boot_sel_chip[5:0] correspond to MTDI,
GPIO0, GPIO2, GPIO4, MTDO, GPIO5, respectively.
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Register 4.14: GPIO_IN_REG (0x003c)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
GPIO_IN_REG GPIO0-31 input value. Each bit represents a pad input value, 1 for high level and 0
for low level. (RO)
Register 4.15: GPIO_IN1_REG (0x0040)
Reset
(reserved)
31 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
x x x x x x x x
GPIO_IN_DATA_NEXT
Reset
GPIO_IN_DATA_NEXT GPIO32-39 input value. Each bit represents a pad input value. (RO)
Register 4.16: GPIO_STATUS_REG (0x0044)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Reset
GPIO_STATUS_REG GPIO0-31 interrupt status register. Each bit can be either of the two interrupt
sources for the two CPUs. The enable bits in GPIO_STATUS_INTERRUPT, corresponding to the
0-4 bits in GPIO_PINn_REG should be set to 1. (R/W)
Register 4.17: GPIO_STATUS_W1TS_REG (0x0048)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Reset
GPIO_STATUS_W1TS_REG GPIO0-31 interrupt status set register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_STATUS_INTERRUPT will be set. (WO)
Register 4.18: GPIO_STATUS_W1TC_REG (0x004c)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Reset
GPIO_STATUS_W1TC_REG GPIO0-31 interrupt status clear register. For every bit that is 1 in the
value written here, the corresponding bit in GPIO_STATUS_INTERRUPT will be cleared. (WO)
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Register 4.19: GPIO_STATUS1_REG (0x0050)
(reserved)
31 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
x x x x x x x x
GPIO_STATUS_INTERRUPT
Reset
GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status. (R/W)
Register 4.20: GPIO_STATUS1_W1TS_REG (0x0054)
(reserved)
31 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
x x x x x x x x
GPIO_STATUS_INTERRUPT
Reset
GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status set register. For every bit that is 1 in the
value written here, the corresponding bit in GPIO_STATUS_INTERRUPT1 will be set. (WO)
Register 4.21: GPIO_STATUS1_W1TC_REG (0x0058)
(reserved)
31 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
x x x x x x x x
GPIO_STATUS_INTERRUPT
Reset
GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status clear register. For every bit that is 1 in the
value written here, the corresponding bit in GPIO_STATUS_INTERRUPT1 will be cleared. (WO)
Register 4.22: GPIO_ACPU_INT_REG (0x0060)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Reset
GPIO_ACPU_INT_REG GPIO0-31 APP CPU interrupt status. (RO)
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Register 4.23: GPIO_ACPU_NMI_INT_REG (0x0064)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
GPIO_ACPU_NMI_INT_REG GPIO0-31 APP CPU non-maskable interrupt status. (RO)
Register 4.24: GPIO_PCPU_INT_REG (0x0068)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
GPIO_PCPU_INT_REG GPIO0-31 PRO CPU interrupt status. (RO)
Register 4.25: GPIO_PCPU_NMI_INT_REG (0x006c)
Reset
Reset
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
GPIO_PCPU_NMI_INT_REG GPIO0-31 PRO CPU non-maskable interrupt status. (RO)
Register 4.26: GPIO_ACPU_INT1_REG (0x0074)
(reserved)
31 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
x x x x x x x x
GPIO_APPCPU_INT
GPIO_APPCPU_INT GPIO32-39 APP CPU interrupt status. (RO)
Register 4.27: GPIO_ACPU_NMI_INT1_REG (0x0078)
Reset
Reset
(reserved)
31 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
x x x x x x x x
GPIO_APPCPU_NMI_INT
Reset
GPIO_APPCPU_NMI_INT GPIO32-39 APP CPU non-maskable interrupt status. (RO)
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Register 4.28: GPIO_PCPU_INT1_REG (0x007c)
(reserved)
31 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
x x x x x x x x
GPIO_PROCPU_INT
GPIO_PROCPU_INT GPIO32-39 PRO CPU interrupt status. (RO)
Register 4.29: GPIO_PCPU_NMI_INT1_REG (0x0080)
(reserved)
31 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
x x x x x x x x
GPIO_PROCPU_NMI_INT
GPIO_PROCPU_NMI_INT GPIO32-39 PRO CPU non-maskable interrupt status. (RO)
Reset
Reset
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Register 4.30: GPIO_PINn_REG (n: 0-39) (0x88+0x4*n)
(reserved)
31 18
0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIO_PINn_INT_ENA
17 13
x x x x x
(reserved)
12 11
0 0
GPIO_PINn_INT_TYPE
GPIO_PINn_WAKEUP_ENABLE
10
9 7
x
x x x
(reserved)
6 3
0 0 0 0
(reserved)
GPIO_PINn_PAD_DRIVER
2
1 0
x
0 0
Reset
GPIO_PINn_INT_ENA Interrupt enable bits for pin n: (R/W)
bit0: APP CPU interrupt enable;
bit1: APP CPU non-maskable interrupt enable;
bit3: PRO CPU interrupt enable;
bit4: PRO CPU non-maskable interrupt enable.
GPIO_PINn_WAKEUP_ENABLE GPIO wake-up enable will only wake up the CPU from Light-sleep.
(R/W)
GPIO_PINn_INT_TYPE Interrupt type selection: (R/W)
0: GPIO interrupt disable;
1: rising edge trigger;
2: falling edge trigger;
3: any edge trigger;
4: low level trigger;
5: high level trigger.
GPIO_PINn_PAD_DRIVER 0: normal output; 1: open drain output. (R/W)
Register 4.31: GPIO_FUNCm_IN_SEL_CFG_REG (m: 0-255) (0x130+0x4*m)
(reserved)
31 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIO_FUNCm_IN_INV_SEL
GPIO_SIGm_IN_SEL
7
6
5 0
x
x
x x x x x x
GPIO_FUNCm_IN_SEL
Reset
GPIO_SIGm_IN_SEL Bypass the GPIO Matrix. 1: route through GPIO Matrix, 0: connect signal
directly to peripheral configured in the IO_MUX. (R/W)
GPIO_FUNCm_IN_INV_SEL Invert the input value. 1: invert; 0: do not invert. (R/W)
GPIO_FUNCm_IN_SEL Selection control for peripheral input m. A value of 0-39 selects which of the
40 GPIO Matrix input pins this signal is connected to, or 0x38 for a constantly high input or 0x30
for a constantly low input. (R/W)
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Register 4.32: GPIO_FUNCn_OUT_SEL_CFG_REG (n: 0-19, 21-23, 25-27, 32-33) (0x530+0x4*n)
(reserved)
31 12
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIO_FUNCn_OEN_INV_SEL
GPIO_FUNCn_OEN_SEL
GPIO_FUNCn_OUT_INV_SEL
11
10
9
8 0
x
x
x
x x x x x x x x x
GPIO_FUNCn_OUT_SEL
Reset
GPIO_FUNCn_OEN_INV_SEL 1: Invert the output enable signal; 0: do not invert the output enable
signal. (R/W)
GPIO_FUNCn_OEN_SEL 1: Force the output enable signal to be sourced from bit n of
GPIO_ENABLE_REG; 0: use output enable signal from peripheral. (R/W)
GPIO_FUNCn_OUT_INV_SEL 1: Invert the output value; 0: do not invert the output value. (R/W)
GPIO_FUNCn_OUT_SEL Selection control for GPIO output n. A value of s (0<=s<256)
connects peripheral output s to GPIO output n. A value of 256 selects bit n of
GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG as the out-
put value and output enable. (R/W)
Register 4.33: IO_MUX_PIN_CTRL (0x3FF49000)
(reserved)
31 12
0x0
PIN_CTRL_CLK3
11 8
0x0
PIN_CTRL_CLK2
7 4
0x0
3 0
0x0
If you want to output clock for I2S0 to:
CLK_OUT1, then set PIN_CTRL[3:0] = 0x0;
CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0;
CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0.
If you want to output clock for I2S1 to:
CLK_OUT1, then set PIN_CTRL[3:0] = 0xF;
CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0;
CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0. (R/W)
Note:
Only the above mentioned combinations of clock source and clock output pins are possible.
The CLK_OUT1-3 can be found in the IO_MUX Pad Summary.
PIN_CTRL_CLK1
Reset
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Register 4.34: IO_MUX_x_REG (x: GPIO0-GPIO39) (0x10+4*x)
(reserved)
31 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCU_SEL
14 12
0x0
FUN_DRV
11 10
0x2
FUN_WPU
FUN_IE
9
8
0
0
FUN_WPD
7
0
MCU_DRV
6 5
0x0
MCU_IE
MCU_WPU
4
3
0
0
MCU_WPD
SLP_SEL
MCU_OE
2
1
0
0
0
0
Reset
MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 1, 1 selects Function 2, etc.
(R/W)
FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength.
(R/W)
FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. (R/W)
FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. (R/W)
FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down dis-
abled. (R/W)
MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with
a higher strength. (R/W)
MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. (R/W)
MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal
pull-up disabled. (R/W)
MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal
pull-down disabled. (R/W)
SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. (R/W)
MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. (R/W)
Register 4.35: RTCIO_RTC_GPIO_OUT_REG (0x0000)
RTCIO_RTC_GPIO_OUT_DATA
31 14
x x x x x x x x x x x x x x x x x x
13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_RTC_GPIO_OUT_DATA GPIO0-17 output register. Bit14 is GPIO[0], bit15 is GPIO[1], etc.
(R/W)
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Register 4.36: RTCIO_RTC_GPIO_OUT_W1TS_REG (0x0004)
RTCIO_RTC_GPIO_OUT_DATA_W1TS
31 14
x x x x x x x x x x x x x x x x x x
13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_RTC_GPIO_OUT_DATA_W1TS GPIO0-17 output set register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_OUT will be set. (WO)
Register 4.37: RTCIO_RTC_GPIO_OUT_W1TC_REG (0x0008)
RTCIO_RTC_GPIO_OUT_DATA_W1TC
31 14
x x x x x x x x x x x x x x x x x x
13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_RTC_GPIO_OUT_DATA_W1TC GPIO0-17 output clear register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_OUT will be cleared. (WO)
Register 4.38: RTCIO_RTC_GPIO_ENABLE_REG (0x000C)
RTCIO_RTC_GPIO_ENABLE
31 14
x x x x x x x x x x x x x x x x x x
13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_RTC_GPIO_ENABLE GPIO0-17 output enable. Bit14 is GPIO[0], bit15 is GPIO[1], etc. 1
means this GPIO pad is output. (R/W)
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Register 4.39: RTCIO_RTC_GPIO_ENABLE_W1TS_REG (0x0010)
RTCIO_RTC_GPIO_ENABLE_W1TS
31 14
x x x x x x x x x x x x x x x x x x
13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_RTC_GPIO_ENABLE_W1TS GPIO0-17 output enable set register. For every bit that is 1 in
the value written here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE will be set. (WO)
Register 4.40: RTCIO_RTC_GPIO_ENABLE_W1TC_REG (0x0014)
RTCIO_RTC_GPIO_ENABLE_W1TC
31 14
x x x x x x x x x x x x x x x x x x
13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_RTC_GPIO_ENABLE_W1TC GPIO0-17 output enable clear register. For every bit that is 1 in
the value written here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE will be cleared. (WO)
Register 4.41: RTCIO_RTC_GPIO_STATUS_REG (0x0018)
RTCIO_RTC_GPIO_STATUS_INT
31 14
x x x x x x x x x x x x x x x x x x
13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_RTC_GPIO_STATUS_INT GPIO0-17 interrupt status. Bit14 is GPIO[0], bit15 is GPIO[1],
etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RT-
CIO_RTC_GPIO_PINn_REG. 1: corresponding interrupt; 0: no interrupt. (R/W)
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Register 4.42: RTCIO_RTC_GPIO_STATUS_W1TS_REG (0x001C)
RTCIO_RTC_GPIO_STATUS_INT_W1TS
31 14
x x x x x x x x x x x x x x x x x x
13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_RTC_GPIO_STATUS_INT_W1TS GPIO0-17 interrupt set register. For every bit that is 1 in
the value written here, the corresponding bit in RTCIO_RTC_GPIO_STATUS_INT will be set. (WO)
Register 4.43: RTCIO_RTC_GPIO_STATUS_W1TC_REG (0x0020)
RTCIO_RTC_GPIO_STATUS_INT_W1TC
31 14
x x x x x x x x x x x x x x x x x x
13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_RTC_GPIO_STATUS_INT_W1TC GPIO0-17 interrupt clear register. For every bit that is 1 in
the value written here, the corresponding bit in RTCIO_RTC_GPIO_STATUS_INT will be cleared.
(WO)
Register 4.44: RTCIO_RTC_GPIO_IN_REG (0x0024)
RTCIO_RTC_GPIO_IN_NEXT
31 14
x x x x x x x x x x x x x x x x x x
13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_RTC_GPIO_IN_NEXT GPIO0-17 input value. Bit14 is GPIO[0], bit15 is GPIO[1], etc. Each
bit represents a pad input value, 1 for high level, and 0 for low level. (RO)
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Register 4.45: RTCIO_RTC_GPIO_PINn_REG (n: 0-17) (28+4*n)
(reserved)
31 11
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTCIO_RTC_GPIO_PINn_WAKEUP_ENABLE
RTCIO_RTC_GPIO_PINn_INT_TYPE
10
9 7
x
x x x
(reserved)
6 3
0 0 0 0
(reserved)
RTCIO_RTC_GPIO_PINn_PAD_DRIVER
2
1 0
x
0 0
Reset
RTCIO_RTC_GPIO_PINn_WAKEUP_ENABLE GPIO wake-up enable. This will only wake up the
ESP32 from Light-sleep. (R/W)
RTCIO_RTC_GPIO_PINn_INT_TYPE GPIO interrupt type selection. (R/W)
0: GPIO interrupt disable;
1: rising edge trigger;
2: falling edge trigger;
3: any edge trigger;
4: low level trigger;
5: high level trigger.
RTCIO_RTC_GPIO_PINn_PAD_DRIVER Pad driver selection. 0: normal output; 1: open drain.
(R/W)
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Register 4.46: RTCIO_DIG_PAD_HOLD_REG (0x0074)
31 0
0
RTCIO_DIG_PAD_HOLD_REG Selects the digital pads which should be put on hold. While 0 allows
normal operation, 1 puts the pad on hold. (R/W)
Name Description
Bit[0] Set to 1 to enable the Hold function of pad U0RTD
Bit[1] Set to 1 to enable the Hold function of pad U0TXD
Bit[2] Set to 1 to enable the Hold function of pad
SD_CLK
Bit[3] Set to 1 to enable the Hold function of pad
SD_DATA0
Bit[4] Set to 1 to enable the Hold function of pad
SD_DATA1
Bit[5] Set to 1 to enable the Hold function of pad
SD_DATA2
Bit[6] Set to 1 to enable the Hold function of pad
SD_DATA3
Bit[7] Set to 1 to enable the Hold function of pad
SD_CMD
Bit[8] Set to 1 to enable the Hold function of pad GPIO5
Bit[9] Set to 1 to enable the Hold function of pad GPIO16
Bit[10] Set to 1 to enable the Hold function of pad GPIO17
Bit[11] Set to 1 to enable the Hold function of pad GPIO18
Bit[12] Set to 1 to enable the Hold function of pad GPIO19
Bit[13] Set to 1 to enable the Hold function of pad GPIO20
Bit[14] Set to 1 to enable the Hold function of pad GPIO21
Bit[15] Set to 1 to enable the Hold function of pad GPIO22
Bit[16] Set to 1 to enable the Hold function of pad GPIO23
Reset
Register 4.47: RTCIO_HALL_SENS_REG (0x0078)
RTCIO_HALL_PHASE
RTCIO_HALL_XPD_HALL
31
30
29 0
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_HALL_XPD_HALL Power on hall sensor and connect to VP and VN. (R/W)
RTCIO_HALL_PHASE Reverse the polarity of the hall sensor. (R/W)
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Register 4.48: RTCIO_SENSOR_PADS_REG (0x007C)
RTCIO_SENSOR_SENSE4_HOLD
RTCIO_SENSOR_SENSE3_HOLD
RTCIO_SENSOR_SENSE2_HOLD
RTCIO_SENSOR_SENSE1_HOLD
31
30
29
28
0
0
0
0
RTCIO_SENSOR_SENSE3_MUX_SEL
RTCIO_SENSOR_SENSE2_MUX_SEL
RTCIO_SENSOR_SENSE1_MUX_SEL
27
0
RTCIO_SENSOR_SENSE4_MUX_SEL
26
25
24
23 22
0
0
0
RTCIO_SENSOR_SENSE1_FUN_SEL
0
RTCIO_SENSOR_SENSE1_FUN_IE
RTCIO_SENSOR_SENSE1_SLP_IE
RTCIO_SENSOR_SENSE1_SLP_SEL
21
20
19
0
0
0
RTCIO_SENSOR_SENSE2_SLP_SEL
RTCIO_SENSOR_SENSE2_FUN_SEL
18 17
16
15
0
0
RTCIO_SENSOR_SENSE3_SLP_IE
RTCIO_SENSOR_SENSE2_FUN_IE
RTCIO_SENSOR_SENSE2_SLP_IE
14
0
0
RTCIO_SENSOR_SENSE3_SLP_SEL
RTCIO_SENSOR_SENSE3_FUN_SEL
13 12
11
10
0
0
0
RTCIO_SENSOR_SENSE4_FUN_SEL
RTCIO_SENSOR_SENSE3_FUN_IE
9
8 7
0
0
RTCIO_SENSOR_SENSE4_FUN_IE
RTCIO_SENSOR_SENSE4_SLP_IE
RTCIO_SENSOR_SENSE4_SLP_SEL
6
5
4
0
0
0
(reserved)
3 0
0 0 0 0
Reset
RTCIO_SENSOR_SENSEn_HOLD Set to 1 to hold the output value on sensen; 0 is for normal op-
eration. (R/W)
RTCIO_SENSOR_SENSEn_MUX_SEL 1: route sensen to the RTC block; 0: route sensen to the
digital IO_MUX. (R/W)
RTCIO_SENSOR_SENSEn_FUN_SEL Select the RTC IO_MUX function for this pad. 0: select Func-
tion 0; 1: select Function 1. (R/W)
RTCIO_SENSOR_SENSEn_SLP_SEL Selection of sleep mode for the pad: set to 1 to put the pad
in sleep mode. (R/W)
RTCIO_SENSOR_SENSEn_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled.
(R/W)
RTCIO_SENSOR_SENSEn_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W)
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Register 4.49: RTCIO_ADC_PAD_REG (0x0080)
RTCIO_ADC_ADC1_MUX_SEL
RTCIO_ADC_ADC2_HOLD
RTCIO_ADC_ADC1_HOLD
31
0
RTCIO_ADC_ADC2_MUX_SEL
30
29
28
0
0
0
RTCIO_ADC_ADC1_SLP_SEL
RTCIO_ADC_ADC1_FUN_SEL
27 26
25
0
0
RTCIO_ADC_ADC2_SLP_IE
RTCIO_ADC_ADC2_SLP_SEL
RTCIO_ADC_ADC1_SLP_IE
24
0
RTCIO_ADC_ADC2_FUN_SEL
RTCIO_ADC_ADC1_FUN_IE
23
22 21
0
0
RTCIO_ADC_ADC2_FUN_IE
20
19
18
0
0
0
17 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_ADC_ADCn_HOLD Set to 1 to hold the output value on the pad; 0 is for normal operation.
(R/W)
RTCIO_ADC_ADCn_MUX_SEL 0: route pad to the digital IO_MUX; (R/W)
1: route pad to the RTC block.
RTCIO_ADC_ADCn_FUN_SEL Select the RTC function for this pad. 0: select Function 0; 1: select
Function 1. (R/W)
RTCIO_ADC_ADCn_SLP_SEL Signal selection of pad’s sleep mode. Set this bit to 1 to put the pad
to sleep. (R/W)
RTCIO_ADC_ADCn_SLP_IE Input enable of the pad in sleep mode. 1 enabled; 0 disabled. (R/W)
RTCIO_ADC_ADCn_FUN_IE Input enable of the pad. 1 enabled; 0 disabled. (R/W)
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Register 4.50: RTCIO_PAD_DAC1_REG (0x0084)
RTCIO_PAD_PDAC1_DRV
31 30
2
RTCIO_PAD_PDAC1_RDE
RTCIO_PAD_PDAC1_HOLD
29
28
0
0
RTCIO_PAD_PDAC1_RUE
27
26 19
0
RTCIO_PAD_PDAC1_DAC
0
RTCIO_PAD_PDAC1_XPD_DAC
18
0
RTCIO_PAD_PDAC1_FUN_SEL
RTCIO_PAD_PDAC1_MUX_SEL
17
16 15
0
0
RTCIO_PAD_PDAC1_SLP_OE
RTCIO_PAD_PDAC1_SLP_IE
RTCIO_PAD_PDAC1_SLP_SEL
14
13
12
11
0
0
0
RTCIO_PAD_PDAC1_DAC_XPD_FORCE
RTCIO_PAD_PDAC1_FUN_IE
10
9 0
0
0
0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_PAD_PDAC1_DRV Select the drive strength of the pad. (R/W)
RTCIO_PAD_PDAC1_HOLD Set to 1 to hold the output value on the pad; set to 0 for normal oper-
ation. (R/W)
RTCIO_PAD_PDAC1_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W)
RTCIO_PAD_PDAC1_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W)
RTCIO_PAD_PDAC1_DAC PAD DAC1 output value. (R/W)
RTCIO_PAD_PDAC1_XPD_DAC Power on DAC1. Usually, PDAC1 needs to be tristated if we power
on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)
RTCIO_PAD_PDAC1_MUX_SEL 0: route pad to the digital IO_MUX; (R/W)
1: route to the RTC block.
RTCIO_PAD_PDAC1_FUN_SEL the functional selection signal of the pad. (R/W)
RTCIO_PAD_PDAC1_SLP_SEL Sleep mode selection signal of the pad. Set this bit to 1 to put the
pad to sleep. (R/W)
RTCIO_PAD_PDAC1_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)
RTCIO_PAD_PDAC1_SLP_OE Output enable of the pad. 1: enabled ; 0: disabled. (R/W)
RTCIO_PAD_PDAC1_FUN_IE Input enable of the pad. 1: enabled it; 0: disabled. (R/W)
RTCIO_PAD_PDAC1_DAC_XPD_FORCE Power on DAC1. Usually, we need to tristate PDAC1 if
we power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)
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Register 4.51: RTCIO_PAD_DAC2_REG (0x0088)
RTCIO_PAD_PDAC2_DRV
31 30
2
RTCIO_PAD_PDAC2_RDE
RTCIO_PAD_PDAC2_HOLD
29
28
0
0
RTCIO_PAD_PDAC2_RUE
27
26 19
0
RTCIO_PAD_PDAC2_DAC
0
RTCIO_PAD_PDAC2_XPD_DAC
18
0
RTCIO_PAD_PDAC2_FUN_SEL
RTCIO_PAD_PDAC2_MUX_SEL
17
16 15
0
0
RTCIO_PAD_PDAC2_SLP_OE
RTCIO_PAD_PDAC2_SLP_IE
RTCIO_PAD_PDAC2_SLP_SEL
14
13
12
11
0
0
0
RTCIO_PAD_PDAC2_DAC_XPD_FORCE
RTCIO_PAD_PDAC2_FUN_IE
10
9 0
0
0
0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_PAD_PDAC2_DRV Select the drive strength of the pad. (R/W)
RTCIO_PAD_PDAC2_HOLD Set to 1 to hold the output value on the pad; 0 is for normal operation.
(R/W)
RTCIO_PAD_PDAC2_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W)
RTCIO_PAD_PDAC2_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W)
RTCIO_PAD_PDAC2_DAC PAD DAC2 output value. (R/W)
RTCIO_PAD_PDAC2_XPD_DAC Power on DAC2. PDAC2 needs to be tristated if we power on the
DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)
RTCIO_PAD_PDAC2_MUX_SEL 0: route pad to the digital IO_MUX; (R/W)
1: route to the RTC block.
RTCIO_PAD_PDAC2_FUN_SEL Select the RTC function for this pad. 0: select Function 0; 1: select
Function 1. (R/W)
RTCIO_PAD_PDAC2_SLP_SEL Sleep mode selection signal of the pad. Set this bit to 1 to put the
pad to sleep. (R/W)
RTCIO_PAD_PDAC2_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)
RTCIO_PAD_PDAC2_SLP_OE Output enable of the pad. 1: enabled; 0: disabled. (R/W)
RTCIO_PAD_PDAC2_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W)
RTCIO_PAD_PDAC2_DAC_XPD_FORCE Power on DAC2. Usually, we need to tristate PDAC2 if
we power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)
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Register 4.52: RTCIO_XTAL_32K_PAD_REG (0x008C)
RTCIO_XTAL_X32N_HOLD
RTCIO_XTAL_X32N_DRV
31 30
2
RTCIO_XTAL_X32N_RDE
29
28
0
0
RTCIO_XTAL_X32P_HOLD
RTCIO_XTAL_X32N_RUE
RTCIO_XTAL_X32P_DRV
27
26 25
0
2
RTCIO_XTAL_X32P_RDE
24
23
22
0
0
0
RTCIO_XTAL_DAC_XTAL_32K
RTCIO_XTAL_X32P_RUE
21 20
0 1
RTCIO_XTAL_X32P_MUX_SEL
RTCIO_XTAL_X32N_MUX_SEL
RTCIO_XTAL_XPD_XTAL_32K
19
18
17
0
0
0
RTCIO_XTAL_X32N_SLP_SEL
RTCIO_XTAL_X32N_FUN_SEL
16 15
14
0
0
RTCIO_XTAL_X32N_FUN_IE
RTCIO_XTAL_X32N_SLP_OE
RTCIO_XTAL_X32N_SLP_IE
13
12
11
0
0
0
RTCIO_XTAL_X32P_SLP_SEL
RTCIO_XTAL_X32P_FUN_SEL
10 9
8
0
0
RTCIO_XTAL_X32P_FUN_IE
RTCIO_XTAL_X32P_SLP_OE
RTCIO_XTAL_X32P_SLP_IE
7
6
5
0
0
0
RTCIO_XTAL_DRES_XTAL_32K
4 3
1 0
(reserved)
RTCIO_XTAL_DBIAS_XTAL_32K
2 1
0
0 0
0
Reset
RTCIO_XTAL_X32N_DRV Select the drive strength of the pad. (R/W)
RTCIO_XTAL_X32N_HOLD Set to 1 to hold the output value on the pad; 0 is for normal operation.
(R/W)
RTCIO_XTAL_X32N_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W)
RTCIO_XTAL_X32N_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W)
RTCIO_XTAL_X32P_DRV Select the drive strength of the pad. (R/W)
RTCIO_XTAL_X32P_HOLD Set to 1 to hold the output value on the pad, 0 is for normal operation.
(R/W)
RTCIO_XTAL_X32P_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W)
RTCIO_XTAL_X32P_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W)
RTCIO_XTAL_DAC_XTAL_32K 32K XTAL bias current DAC value. (R/W)
RTCIO_XTAL_XPD_XTAL_32K Power up 32 KHz crystal oscillator. (R/W)
RTCIO_XTAL_X32N_MUX_SEL 0: route X32N pad to the digital IO_MUX; 1: route to RTC block.
(R/W)
RTCIO_XTAL_X32P_MUX_SEL 0: route X32P pad to the digital IO_MUX; 1: route to RTC block.
(R/W)
RTCIO_XTAL_X32N_FUN_SEL Select the RTC function. 0: select function 0; 1: select function 1.
(R/W)
RTCIO_XTAL_X32N_SLP_SEL Sleep mode selection. Set this bit to 1 to put the pad to sleep. (R/W)
RTCIO_XTAL_X32N_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)
RTCIO_XTAL_X32N_SLP_OE Output enable of the pad. 1: enabled; 0; disabled. (R/W)
RTCIO_XTAL_X32N_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W)
RTCIO_XTAL_X32P_FUN_SEL Select the RTC function. 0: select function 0; 1: select function 1.
(R/W)
RTCIO_XTAL_X32P_SLP_SEL Sleep mode selection. Set this bit to 1 to put the pad to sleep. (R/W)
RTCIO_XTAL_X32P_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)
Continued on the next page...
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4. IO_MUX and GPIO Matrix
Register 4.52: RTCIO_XTAL_32K_PAD_REG (0x008C)
Continued from the previous page...
RTCIO_XTAL_X32P_SLP_OE Output enable of the pad in sleep mode. 1: enabled; 0: disabled.
(R/W)
RTCIO_XTAL_X32P_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W)
RTCIO_XTAL_DRES_XTAL_32K 32K XTAL resistor bias control. (R/W)
RTCIO_XTAL_DBIAS_XTAL_32K 32K XTAL self-bias reference control. (R/W)
Register 4.53: RTCIO_TOUCH_CFG_REG (0x0090)
RTCIO_TOUCH_DREFH
RTCIO_TOUCH_DREFL
RTCIO_TOUCH_XPD_BIAS
31
30 29
28 27
0
1 1
0 0
RTCIO_TOUCH_DRANGE
26 25
1 1
RTCIO_TOUCH_DCUR
24 23
22 0
0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_TOUCH_XPD_BIAS Touch sensor bias power on bit. 1: power on; 0: disabled. (R/W)
RTCIO_TOUCH_DREFH Touch sensor saw wave top voltage. (R/W)
RTCIO_TOUCH_DREFL Touch sensor saw wave bottom voltage. (R/W)
RTCIO_TOUCH_DRANGE Touch sensor saw wave voltage range. (R/W)
RTCIO_TOUCH_DCUR Touch sensor bias current. When BIAS_SLEEP is enabled, this setting is
available. (R/W)
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4. IO_MUX and GPIO Matrix
Register 4.54: RTCIO_TOUCH_PADn_REG (n: 0-9) (94+4*n)
(reserved)
31 26
0 0 0 0 0 0
RTCIO_TOUCH_PADn_START
RTCIO_TOUCH_PADn_DAC
25 23
0x4
22
0
RTCIO_TOUCH_PADn_TO_GPIO
RTCIO_TOUCH_PADn_XPD
RTCIO_TOUCH_PADn_TIE_OPT
21
20
19
18 0
0
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_TOUCH_PADn_DAC Touch sensor slope control. 3-bit for each touch pad, defaults to 100.
(R/W)
RTCIO_TOUCH_PADn_START Start touch sensor. (R/W)
RTCIO_TOUCH_PADn_TIE_OPT Default touch sensor tie option. 0: tie low; 1: tie high. (R/W)
RTCIO_TOUCH_PADn_XPD Touch sensor power on. (R/W)
RTCIO_TOUCH_PADn_TO_GPIO Connect the RTC pad input to digital pad input; 0 is available.
(R/W)
Register 4.55: RTCIO_EXT_WAKEUP0_REG (0x00BC)
RTCIO_EXT_WAKEUP0_SEL
31 27
0
26 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_EXT_WAKEUP0_SEL GPIO[0-17] can be used to wake up the chip when the chip is in the
sleep mode. This register prompts the pad source to wake up the chip when the latter is in
deep/light sleep mode. 0: select GPIO0; 1: select GPIO2, etc. (R/W)
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4. IO_MUX and GPIO Matrix
Register 4.56: RTCIO_XTL_EXT_CTR_REG (0x00C0)
RTCIO_XTL_EXT_CTR_SEL
31 27
0
26 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_XTL_EXT_CTR_SEL Select the external crystal power down enable source to get into
sleep mode. 0: select GPIO0; 1: select GPIO2, etc. The input value on this pin XOR RT-
CIO_RTC_EXT_XTAL_CONF_REG[30] is the crystal power down enable signal. (R/W)
Register 4.57: RTCIO_SAR_I2C_IO_REG (0x00C4)
RTCIO_SAR_I2C_SDA_SEL
RTCIO_SAR_I2C_SCL_SEL
31 30
29 28
27 0
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
Reset
RTCIO_SAR_I2C_SDA_SEL Selects a different pad as the RTC I2C SDA signal. 0: use pad
TOUCH_PAD[1]; 1: use pad TOUCH_PAD[3]. (R/W)
RTCIO_SAR_I2C_SCL_SEL Selects a different pad as the RTC I2C SCL signal. 0: use pad
TOUCH_PAD[0]; 1: use pad TOUCH_PAD[2]. (R/W)
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5. DPort Register
5. DPort Register
5.1 Introduction
The ESP32 integrates a large number of peripherals, and enables the control of individual peripherals to achieve
optimal characteristics in performance-vs-power-consumption scenarios. The DPort registers control clock
management (clock gating), power management, and the configuration of peripherals and core-system modules.
The system arranges each module with configuration registers contained in the DPort Register.
5.2 Features
DPort registers correspond to different peripheral blocks and core modules:
• System and memory
• Reset and clock
• Interrupt matrix
• DMA
• PID/MPU/MMU
• APP_CPU
• Peripheral clock gating and reset
5.3 Functional Description
5.3.1 System and Memory Register
The following registers are used for system and memory configuration, such as cache configuration and memory
remapping. For a detailed description of these registers, please refer to Chapter System and Memory.
• DPORT_PRO_BOOT_REMAP_CTRL_REG
• DPORT_APP_BOOT_REMAP_CTRL_REG
• DPORT_CACHE_MUX_MODE_REG
5.3.2 Reset and Clock Registers
The following register is used for Reset and Clock. For a detailed description of the register, please refer to Reset
and Clock.
• DPORT_CPU_PER_CONF_REG
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5. DPort Register
5.3.3 Interrupt Matrix Register
The following registers are used for configuring and mapping interrupts through the interrupt matrix. For a
detailed description of the registers, please refer to Interrupt Matrix.
• DPORT_CPU_INTR_FROM_CPU_0_REG
• DPORT_CPU_INTR_FROM_CPU_1_REG
• DPORT_CPU_INTR_FROM_CPU_2_REG
• DPORT_CPU_INTR_FROM_CPU_3_REG
• DPORT_PRO_INTR_STATUS_0_REG
• DPORT_PRO_INTR_STATUS_1_REG
• DPORT_PRO_INTR_STATUS_2_REG
• DPORT_APP_INTR_STATUS_0_REG
• DPORT_APP_INTR_STATUS_1_REG
• DPORT_APP_INTR_STATUS_2_REG
• DPORT_PRO_MAC_INTR_MAP_REG
• DPORT_PRO_MAC_NMI_MAP_REG
• DPORT_PRO_BB_INT_MAP_REG
• DPORT_PRO_BT_MAC_INT_MAP_REG
• DPORT_PRO_BT_BB_INT_MAP_REG
• DPORT_PRO_BT_BB_NMI_MAP_REG
• DPORT_PRO_RWBT_IRQ_MAP_REG
• DPORT_PRO_RWBLE_IRQ_MAP_REG
• DPORT_PRO_RWBT_NMI_MAP_REG
• DPORT_PRO_RWBLE_NMI_MAP_REG
• DPORT_PRO_SLC0_INTR_MAP_REG
• DPORT_PRO_SLC1_INTR_MAP_REG
• DPORT_PRO_UHCI0_INTR_MAP_REG
• DPORT_PRO_UHCI1_INTR_MAP_REG
• DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG
• DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG
• DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG
• DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG
• DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG
• DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG
• DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG
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5. DPort Register
• DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG
• DPORT_PRO_GPIO_INTERRUPT_MAP_REG
• DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG
• DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG
• DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG
• DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG
• DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG
• DPORT_PRO_SPI_INTR_0_MAP_REG
• DPORT_PRO_SPI_INTR_1_MAP_REG
• DPORT_PRO_SPI_INTR_2_MAP_REG
• DPORT_PRO_SPI_INTR_3_MAP_REG
• DPORT_PRO_I2S0_INT_MAP_REG
• DPORT_PRO_I2S1_INT_MAP_REG
• DPORT_PRO_UART_INTR_MAP_REG
• DPORT_PRO_UART1_INTR_MAP_REG
• DPORT_PRO_UART2_INTR_MAP_REG
• DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG
• DPORT_PRO_EMAC_INT_MAP_REG
• DPORT_PRO_PWM0_INTR_MAP_REG
• DPORT_PRO_PWM1_INTR_MAP_REG
• DPORT_PRO_PWM2_INTR_MAP_REG
• DPORT_PRO_PWM3_INTR_MAP_REG
• DPORT_PRO_LEDC_INT_MAP_REG
• DPORT_PRO_EFUSE_INT_MAP_REG
• DPORT_PRO_CAN_INT_MAP_REG
• DPORT_PRO_RTC_CORE_INTR_MAP_REG
• DPORT_PRO_RMT_INTR_MAP_REG
• DPORT_PRO_PCNT_INTR_MAP_REG
• DPORT_PRO_I2C_EXT0_INTR_MAP_REG
• DPORT_PRO_I2C_EXT1_INTR_MAP_REG
• DPORT_PRO_RSA_INTR_MAP_REG
• DPORT_PRO_SPI1_DMA_INT_MAP_REG
• DPORT_PRO_SPI2_DMA_INT_MAP_REG
• DPORT_PRO_SPI3_DMA_INT_MAP_REG
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5. DPort Register
• DPORT_PRO_WDG_INT_MAP_REG
• DPORT_PRO_TIMER_INT1_MAP_REG
• DPORT_PRO_TIMER_INT2_MAP_REG
• DPORT_PRO_TG_T0_EDGE_INT_MAP_REG
• DPORT_PRO_TG_T1_EDGE_INT_MAP_REG
• DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG
• DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG
• DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG
• DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG
• DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG
• DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG
• DPORT_PRO_MMU_IA_INT_MAP_REG
• DPORT_PRO_MPU_IA_INT_MAP_REG
• DPORT_PRO_CACHE_IA_INT_MAP_REG
• DPORT_APP_MAC_INTR_MAP_REG
• DPORT_APP_MAC_NMI_MAP_REG
• DPORT_APP_BB_INT_MAP_REG
• DPORT_APP_BT_MAC_INT_MAP_REG
• DPORT_APP_BT_BB_INT_MAP_REG
• DPORT_APP_BT_BB_NMI_MAP_REG
• DPORT_APP_RWBT_IRQ_MAP_REG
• DPORT_APP_RWBLE_IRQ_MAP_REG
• DPORT_APP_RWBT_NMI_MAP_REG
• DPORT_APP_RWBLE_NMI_MAP_REG
• DPORT_APP_SLC0_INTR_MAP_REG
• DPORT_APP_SLC1_INTR_MAP_REG
• DPORT_APP_UHCI0_INTR_MAP_REG
• DPORT_APP_UHCI1_INTR_MAP_REG
• DPORT_APP_TG_T0_LEVEL_INT_MAP_REG
• DPORT_APP_TG_T1_LEVEL_INT_MAP_REG
• DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG
• DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG
• DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG
• DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG
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5. DPort Register
• DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG
• DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG
• DPORT_APP_GPIO_INTERRUPT_MAP_REG
• DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG
• DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG
• DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG
• DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG
• DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG
• DPORT_APP_SPI_INTR_0_MAP_REG
• DPORT_APP_SPI_INTR_1_MAP_REG
• DPORT_APP_SPI_INTR_2_MAP_REG
• DPORT_APP_SPI_INTR_3_MAP_REG
• DPORT_APP_I2S0_INT_MAP_REG
• DPORT_APP_I2S1_INT_MAP_REG
• DPORT_APP_UART_INTR_MAP_REG
• DPORT_APP_UART1_INTR_MAP_REG
• DPORT_APP_UART2_INTR_MAP_REG
• DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG
• DPORT_APP_EMAC_INT_MAP_REG
• DPORT_APP_PWM0_INTR_MAP_REG
• DPORT_APP_PWM1_INTR_MAP_REG
• DPORT_APP_PWM2_INTR_MAP_REG
• DPORT_APP_PWM3_INTR_MAP_REG
• DPORT_APP_LEDC_INT_MAP_REG
• DPORT_APP_EFUSE_INT_MAP_REG
• DPORT_APP_CAN_INT_MAP_REG
• DPORT_APP_RTC_CORE_INTR_MAP_REG
• DPORT_APP_RMT_INTR_MAP_REG
• DPORT_APP_PCNT_INTR_MAP_REG
• DPORT_APP_I2C_EXT0_INTR_MAP_REG
• DPORT_APP_I2C_EXT1_INTR_MAP_REG
• DPORT_APP_RSA_INTR_MAP_REG
• DPORT_APP_SPI1_DMA_INT_MAP_REG
• DPORT_APP_SPI2_DMA_INT_MAP_REG
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5. DPort Register
• DPORT_APP_SPI3_DMA_INT_MAP_REG
• DPORT_APP_WDG_INT_MAP_REG
• DPORT_APP_TIMER_INT1_MAP_REG
• DPORT_APP_TIMER_INT2_MAP_REG
• DPORT_APP_TG_T0_EDGE_INT_MAP_REG
• DPORT_APP_TG_T1_EDGE_INT_MAP_REG
• DPORT_APP_TG_WDT_EDGE_INT_MAP_REG
• DPORT_APP_TG_LACT_EDGE_INT_MAP_REG
• DPORT_APP_TG1_T0_EDGE_INT_MAP_REG
• DPORT_APP_TG1_T1_EDGE_INT_MAP_REG
• DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG
• DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG
• DPORT_APP_MMU_IA_INT_MAP_REG
• DPORT_APP_MPU_IA_INT_MAP_REG
• DPORT_APP_CACHE_IA_INT_MAP_REG
5.3.4 DMA Registers
The following register is used for the SPI DMA configuration. For a detailed description of the register, please refer
to DMA.
• DPORT_SPI_DMA_CHAN_SEL_REG
5.3.5 PID/MPU/MMU Registers
The following registers are used for PID/MPU/MMU configuration and operation control. For a detailed
description of the registers, please refer to PID/MPU/MMU.
• DPORT_PRO_CACHE_CTRL_REG
• DPORT_APP_CACHE_CTRL_REG
• DPORT_IMMU_PAGE_MODE_REG
• DPORT_DMMU_PAGE_MODE_REG
• DPORT_AHB_MPU_TABLE_0_REG
• DPORT_AHB_MPU_TABLE_1_REG
• DPORT_AHBLITE_MPU_TABLE_UART_REG
• DPORT_AHBLITE_MPU_TABLE_SPI1_REG
• DPORT_AHBLITE_MPU_TABLE_SPI0_REG
• DPORT_AHBLITE_MPU_TABLE_GPIO_REG
• DPORT_AHBLITE_MPU_TABLE_FE2_REG
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5. DPort Register
• DPORT_AHBLITE_MPU_TABLE_FE_REG
• DPORT_AHBLITE_MPU_TABLE_TIMER_REG
• DPORT_AHBLITE_MPU_TABLE_RTC_REG
• DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG
• DPORT_AHBLITE_MPU_TABLE_WDG_REG
• DPORT_AHBLITE_MPU_TABLE_HINF_REG
• DPORT_AHBLITE_MPU_TABLE_UHCI1_REG
• DPORT_AHBLITE_MPU_TABLE_I2S0_REG
• DPORT_AHBLITE_MPU_TABLE_UART1_REG
• DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG
• DPORT_AHBLITE_MPU_TABLE_UHCI0_REG
• DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG
• DPORT_AHBLITE_MPU_TABLE_RMT_REG
• DPORT_AHBLITE_MPU_TABLE_PCNT_REG
• DPORT_AHBLITE_MPU_TABLE_SLC_REG
• DPORT_AHBLITE_MPU_TABLE_LEDC_REG
• DPORT_AHBLITE_MPU_TABLE_EFUSE_REG
• DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG
• DPORT_AHBLITE_MPU_TABLE_PWM0_REG
• DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG
• DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG
• DPORT_AHBLITE_MPU_TABLE_SPI2_REG
• DPORT_AHBLITE_MPU_TABLE_SPI3_REG
• DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG
• DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG
• DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG
• DPORT_AHBLITE_MPU_TABLE_EMAC_REG
• DPORT_AHBLITE_MPU_TABLE_PWM1_REG
• DPORT_AHBLITE_MPU_TABLE_I2S1_REG
• DPORT_AHBLITE_MPU_TABLE_UART2_REG
• DPORT_AHBLITE_MPU_TABLE_PWM2_REG
• DPORT_AHBLITE_MPU_TABLE_PWM3_REG
• DPORT_AHBLITE_MPU_TABLE_PWR_REG
• DPORT_IMMU_TABLE0_REG
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5. DPort Register
• DPORT_IMMU_TABLE1_REG
• DPORT_IMMU_TABLE2_REG
• DPORT_IMMU_TABLE3_REG
• DPORT_IMMU_TABLE4_REG
• DPORT_IMMU_TABLE5_REG
• DPORT_IMMU_TABLE6_REG
• DPORT_IMMU_TABLE7_REG
• DPORT_IMMU_TABLE8_REG
• DPORT_IMMU_TABLE9_REG
• DPORT_IMMU_TABLE10_REG
• DPORT_IMMU_TABLE11_REG
• DPORT_IMMU_TABLE12_REG
• DPORT_IMMU_TABLE13_REG
• DPORT_IMMU_TABLE14_REG
• DPORT_IMMU_TABLE15_REG
• DPORT_DMMU_TABLE0_REG
• DPORT_DMMU_TABLE1_REG
• DPORT_DMMU_TABLE2_REG
• DPORT_DMMU_TABLE3_REG
• DPORT_DMMU_TABLE4_REG
• DPORT_DMMU_TABLE5_REG
• DPORT_DMMU_TABLE6_REG
• DPORT_DMMU_TABLE7_REG
• DPORT_DMMU_TABLE8_REG
• DPORT_DMMU_TABLE9_REG
• DPORT_DMMU_TABLE10_REG
• DPORT_DMMU_TABLE11_REG
• DPORT_DMMU_TABLE12_REG
• DPORT_DMMU_TABLE13_REG
• DPORT_DMMU_TABLE14_REG
• DPORT_DMMU_TABLE15_REG
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5. DPort Register
5.3.6 APP_CPU Controller Registers
DPort registers are used for some basic configuration of the APP_CPU, such as performing a stalling execution,
and for configuring the ROM boot jump address.
• APP_CPU is reset when DPORT_APPCPU_RESETTING=1. It is released when
DPORT_APPCPU_RESETTING=0.
• When DPORT_APPCPU_CLKGATE_EN=0, the APP_CPU clock can be disabled to reduce power
consumption.
• When DPORT_APPCPU_RUNSTALL=1, the APP_CPU can be put into a stalled state.
• When APP_CPU is booted up with a ROM code, it will jump to the address stored in the
DPORT_APPCPU_BOOT_ADDR register.
5.3.7 Peripheral Clock Gating and Reset
Reset and clock gating registers covered in this section are active-high registers. Note that the reset bits are not
self-cleared by hardware. When a clock-gating register bit is set to 1, the corresponding clock is enabled. Setting
the register bit to 0 disables the clock. Setting a reset register bit to 1 puts the peripheral in a reset state, while
setting the register bit to 0 disables the reset state, thus enabling normal operation.
• DPORT_PERI_CLK_EN_REG: enables the hardware accelerator clock.
– BIT4, Digital Signature
– BIT3, Secure boot
– BIT2, RSA Accelerator
– BIT1, SHA Accelerator
– BIT0, AES Accelerator
• DPORT_PERI_RST_EN_REG: resets the accelerator.
– BIT4, Digital Signature
AES Accelerator and RSA Accelerator will also be reset.
– BIT3, Secure boot
AES Accelerator and SHA Accelerator will also be reset.
– BIT2, RSA Accelerator
– BIT1, SHA Accelerator
– BIT0, AES Accelerator
• DPORT_PERIP_CLK_EN_REG=1: enables the peripheral clock.
– BIT26, PWM3
– BIT25, PWM2
– BIT24, UART MEM
All UART-shared memory. As long as a UART is working, the UART memory clock cannot be in the
gating state.
– BIT23, UART2
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5. DPort Register
– BIT22, SPI_DMA
– BIT21, I2S1
– BIT20, PWM1
– BIT19, CAN
– BIT18, I2C1
– BIT17, PWM0
– BIT16, SPI3
– BIT15, Timer Group1
– BIT14, eFuse
– BIT13, Timer Group0
– BIT12, UHCI1
– BIT11, LED_PWM
– BIT10, PULSE_CNT
– BIT9, Remote Controller
– BIT8, UHCI0
– BIT7, I2C0
– BIT6, SPI2
– BIT5, UART1
– BIT4, I2S0
– BIT3, WDG
– BIT2, UART
– BIT1, SPI
– BIT0, Timers
• DPORT_PERIP_RST_EN_REG: resets peripherals
– BIT26, PWM3
– BIT25, PWM2
– BIT24, UART MEM
– BIT23, UART2
– BIT22, SPI_DMA
– BIT21, I2S1
– BIT20, PWM1
– BIT19, CAN
– BIT18, I2C1
– BIT17, PWM0
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5. DPort Register
– BIT16, SPI3
– BIT15, Timer Group1
– BIT14, eFuse
– BIT13, Timer Group0
– BIT12, UHCI1
– BIT11, LED_PWM
– BIT10, PULSE_CNT
– BIT9, Remote Controller
– BIT8, UHCI0
– BIT7, I2C0
– BIT6, SPI2
– BIT5, UART1
– BIT4, I2S0
– BIT3, WDG
– BIT2, UART
– BIT1, SPI
– BIT0, Timers
• DPORT_WIFI_CLK_EN_REG: used for Wi-Fi and BT clock gating.
• DPORT_WIFI_RST_EN_REG: used for Wi-Fi and BT reset.
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5. DPort Register
5.4 Register Summary
Name Description Address Access
PRO_BOOT_REMAP_CTRL_REG remap mode for PRO_CPU 0x3FF00000 R/W
APP_BOOT_REMAP_CTRL_REG remap mode for APP_CPU 0x3FF00004 R/W
PERI_CLK_EN_REG clock gate for peripherals 0x3FF0001C R/W
PERI_RST_EN_REG reset for peripherals 0x3FF00020 R/W
APPCPU_CTRL_REG_A_REG reset for APP_CPU 0x3FF0002C R/W
APPCPU_CTRL_REG_B_REG clock gate for APP_CPU 0x3FF00030 R/W
APPCPU_CTRL_REG_C_REG stall for APP_CPU 0x3FF00034 R/W
APPCPU_CTRL_REG_D_REG boot address for APP_CPU 0x3FF00038 R/W
PRO_CACHE_CTRL_REG
APP_CACHE_CTRL_REG
CACHE_MUX_MODE_REG
IMMU_PAGE_MODE_REG
DMMU_PAGE_MODE_REG
SRAM_PD_CTRL_REG_0_REG powers down internal SRAM_REG 0x3FF00098 R/W
SRAM_PD_CTRL_REG_1_REG powers down internal SRAM_REG 0x3FF0009C R/W
AHB_MPU_TABLE_0_REG MPU for configuring DMA 0x3FF000B4 R/W
AHB_MPU_TABLE_1_REG MPU for configuring DMA 0x3FF000B8 R/W
PERIP_CLK_EN_REG clock gate for peripherals 0x3FF000C0 R/W
PERIP_RST_EN_REG reset for peripherals 0x3FF000C4 R/W
SLAVE_SPI_CONFIG_REG enables decryption in external flash 0x3FF000C8 R/W
WIFI_CLK_EN_REG clock gate for Wi-Fi 0x3FF000CC R/W
WIFI_RST_EN_REG reset for Wi-Fi 0x3FF000D0 R/W
CPU_INTR_FROM_CPU_0_REG interrupt 0 in both CPUs 0x3FF000DC R/W
CPU_INTR_FROM_CPU_1_REG interrupt 1 in both CPUs 0x3FF000E0 R/W
CPU_INTR_FROM_CPU_2_REG interrupt 2 in both CPUs 0x3FF000E4 R/W
CPU_INTR_FROM_CPU_3_REG interrupt 3 in both CPUs 0x3FF000E8 R/W
PRO_INTR_STATUS_REG_0_REG PRO_CPU interrupt status 0 0x3FF000EC RO
PRO_INTR_STATUS_REG_1_REG PRO_CPU interrupt status 1 0x3FF000F0 RO
PRO_INTR_STATUS_REG_2_REG PRO_CPU interrupt status 2 0x3FF000F4 RO
APP_INTR_STATUS_REG_0_REG APP_CPU interrupt status 0 0x3FF000F8 RO
APP_INTR_STATUS_REG_1_REG APP_CPU interrupt status 1 0x3FF000FC RO
APP_INTR_STATUS_REG_2_REG APP_CPU interrupt status 2 0x3FF00100 RO
PRO_MAC_INTR_MAP_REG interrupt map 0x3FF00104 R/W
PRO_MAC_NMI_MAP_REG interrupt map 0x3FF00108 R/W
PRO_BB_INT_MAP_REG interrupt map 0x3FF0010C R/W
PRO_BT_MAC_INT_MAP_REG interrupt map 0x3FF00110 R/W
determines the virtual address mode
of the external SRAM
determines the virtual address mode
of the external SRAM
the mode of the two caches sharing
the memory
page size in the MMU for the internal
SRAM 0
page size in the MMU for the internal
SRAM 2
0x3FF00040 R/W
0x3FF00058 R/W
0x3FF0007C R/W
0x3FF00080 R/W
0x3FF00084 R/W
Espressif Systems 95 ESP32 Technical Reference Manual V4.0
5. DPort Register
Name Description Address Access
PRO_BT_BB_INT_MAP_REG interrupt map 0x3FF00114 R/W
PRO_BT_BB_NMI_MAP_REG interrupt map 0x3FF00118 R/W
PRO_RWBT_IRQ_MAP_REG interrupt map 0x3FF0011C R/W
PRO_RWBLE_IRQ_MAP_REG interrupt map 0x3FF00120 R/W
PRO_RWBT_NMI_MAP_REG interrupt map 0x3FF00124 R/W
PRO_RWBLE_NMI_MAP_REG interrupt map 0x3FF00128 R/W
PRO_SLC0_INTR_MAP_REG interrupt map 0x3FF0012C R/W
PRO_SLC1_INTR_MAP_REG interrupt map 0x3FF00130 R/W
PRO_UHCI0_INTR_MAP_REG interrupt map 0x3FF00134 R/W
PRO_UHCI1_INTR_MAP_REG interrupt map 0x3FF00138 R/W
PRO_TG_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF0013C R/W
PRO_TG_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00140 R/W
PRO_TG_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00144 R/W
PRO_TG_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF00148 R/W
PRO_TG1_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF0014C R/W
PRO_TG1_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00150 R/W
PRO_TG1_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00154 R/W
PRO_TG1_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF00158 R/W
PRO_GPIO_INTERRUPT_MAP_REG interrupt map 0x3FF0015C R/W
PRO_GPIO_INTERRUPT_NMI_MAP_REG interrupt map 0x3FF00160 R/W
PRO_CPU_INTR_FROM_CPU_0_MAP_REG interrupt map 0x3FF00164 R/W
PRO_CPU_INTR_FROM_CPU_1_MAP_REG interrupt map 0x3FF00168 R/W
PRO_CPU_INTR_FROM_CPU_2_MAP_REG Interrupt map 0x3FF0016C R/W
PRO_CPU_INTR_FROM_CPU_3_MAP_REG interrupt map 0x3FF00170 R/W
PRO_SPI_INTR_0_MAP_REG interrupt map 0x3FF00174 R/W
PRO_SPI_INTR_1_MAP_REG interrupt map 0x3FF00178 R/W
PRO_SPI_INTR_2_MAP_REG interrupt map 0x3FF0017C R/W
PRO_SPI_INTR_3_MAP_REG interrupt map 0x3FF00180 R/W
PRO_I2S0_INT_MAP_REG interrupt map 0x3FF00184 R/W
PRO_I2S1_INT_MAP_REG interrupt map 0x3FF00188 R/W
PRO_UART_INTR_MAP_REG interrupt map 0x3FF0018C R/W
PRO_UART1_INTR_MAP_REG interrupt map 0x3FF00190 R/W
PRO_UART2_INTR_MAP_REG interrupt map 0x3FF00194 R/W
PRO_SDIO_HOST_INTERRUPT_MAP_REG interrupt map 0x3FF00198 R/W
PRO_EMAC_INT_MAP_REG interrupt map 0x3FF0019C R/W
PRO_PWM0_INTR_MAP_REG interrupt map 0x3FF001A0 R/W
PRO_PWM1_INTR_MAP_REG interrupt map 0x3FF001A4 R/W
PRO_PWM2_INTR_MAP_REG interrupt map 0x3FF001A8 R/W
PRO_PWM3_INTR_MAP_REG interrupt map 0x3FF001AC R/W
PRO_LEDC_INT_MAP_REG interrupt map 0x3FF001B0 R/W
PRO_EFUSE_INT_MAP_REG interrupt map 0x3FF001B4 R/W
PRO_CAN_INT_MAP_REG interrupt map 0x3FF001B8 R/W
Espressif Systems 96 ESP32 Technical Reference Manual V4.0
5. DPort Register
Name Description Address Access
PRO_RTC_CORE_INTR_MAP_REG interrupt map 0x3FF001BC R/W
PRO_RMT_INTR_MAP_REG interrupt map 0x3FF001C0 R/W
PRO_PCNT_INTR_MAP_REG interrupt map 0x3FF001C4 R/W
PRO_I2C_EXT0_INTR_MAP_REG interrupt map 0x3FF001C8 R/W
PRO_I2C_EXT1_INTR_MAP_REG interrupt map 0x3FF001CC R/W
PRO_RSA_INTR_MAP_REG interrupt map 0x3FF001D0 R/W
PRO_SPI1_DMA_INT_MAP_REG interrupt map 0x3FF001D4 R/W
PRO_SPI2_DMA_INT_MAP_REG interrupt map 0x3FF001D8 R/W
PRO_SPI3_DMA_INT_MAP_REG interrupt map 0x3FF001DC R/W
PRO_WDG_INT_MAP_REG interrupt map 0x3FF001E0 R/W
PRO_TIMER_INT1_MAP_REG interrupt map 0x3FF001E4 R/W
PRO_TIMER_INT2_MAP_REG interrupt map 0x3FF001E8 R/W
PRO_TG_T0_EDGE_INT_MAP_REG interrupt map 0x3FF001EC R/W
PRO_TG_T1_EDGE_INT_MAP_REG interrupt map 0x3FF001F0 R/W
PRO_TG_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF001F4 R/W
PRO_TG_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF001F8 R/W
PRO_TG1_T0_EDGE_INT_MAP_REG interrupt map 0x3FF001FC R/W
PRO_TG1_T1_EDGE_INT_MAP_REG interrupt map 0x3FF00200 R/W
PRO_TG1_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF00204 R/W
PRO_TG1_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF00208 R/W
PRO_MMU_IA_INT_MAP_REG interrupt map 0x3FF0020C R/W
PRO_MPU_IA_INT_MAP_REG interrupt map 0x3FF00210 R/W
PRO_CACHE_IA_INT_MAP_REG interrupt map 0x3FF00214 R/W
APP_MAC_INTR_MAP_REG interrupt map 0x3FF00218 R/W
APP_MAC_NMI_MAP_REG interrupt map 0x3FF0021C R/W
APP_BB_INT_MAP_REG interrupt map 0x3FF00220 R/W
APP_BT_MAC_INT_MAP_REG interrupt map 0x3FF00224 R/W
APP_BT_BB_INT_MAP_REG interrupt map 0x3FF00228 R/W
APP_BT_BB_NMI_MAP_REG interrupt map 0x3FF0022C R/W
APP_RWBT_IRQ_MAP_REG interrupt map 0x3FF00230 R/W
APP_RWBLE_IRQ_MAP_REG interrupt map 0x3FF00234 R/W
APP_RWBT_NMI_MAP_REG interrupt map 0x3FF00238 R/W
APP_RWBLE_NMI_MAP_REG interrupt map 0x3FF0023C R/W
APP_SLC0_INTR_MAP_REG interrupt map 0x3FF00240 R/W
APP_SLC1_INTR_MAP_REG interrupt map 0x3FF00244 R/W
APP_UHCI0_INTR_MAP_REG interrupt map 0x3FF00248 R/W
APP_UHCI1_INTR_MAP_REG interrupt map 0x3FF0024C R/W
APP_TG_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF00250 R/W
APP_TG_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00254 R/W
APP_TG_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00258 R/W
APP_TG_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF0025C R/W
APP_TG1_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF00260 R/W
Espressif Systems 97 ESP32 Technical Reference Manual V4.0
5. DPort Register
Name Description Address Access
APP_TG1_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00264 R/W
APP_TG1_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00268 R/W
APP_TG1_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF0026C R/W
APP_GPIO_INTERRUPT_MAP_REG interrupt map 0x3FF00270 R/W
APP_GPIO_INTERRUPT_NMI_MAP_REG interrupt map 0x3FF00274 R/W
APP_CPU_INTR_FROM_CPU_0_MAP_REG interrupt map 0x3FF00278 R/W
APP_CPU_INTR_FROM_CPU_1_MAP_REG interrupt map 0x3FF0027C R/W
APP_CPU_INTR_FROM_CPU_2_MAP_REG interrupt map 0x3FF00280 R/W
APP_CPU_INTR_FROM_CPU_3_MAP_REG interrupt map 0x3FF00284 R/W
APP_SPI_INTR_0_MAP_REG interrupt map 0x3FF00288 R/W
APP_SPI_INTR_1_MAP_REG interrupt map 0x3FF0028C R/W
APP_SPI_INTR_2_MAP_REG interrupt map 0x3FF00290 R/W
APP_SPI_INTR_3_MAP_REG interrupt map 0x3FF00294 R/W
APP_I2S0_INT_MAP_REG interrupt map 0x3FF00298 R/W
APP_I2S1_INT_MAP_REG interrupt map 0x3FF0029C R/W
APP_UART_INTR_MAP_REG interrupt map 0x3FF002A0 R/W
APP_UART1_INTR_MAP_REG interrupt map 0x3FF002A4 R/W
APP_UART2_INTR_MAP_REG interrupt map 0x3FF002A8 R/W
APP_SDIO_HOST_INTERRUPT_MAP_REG interrupt map 0x3FF002AC R/W
APP_EMAC_INT_MAP_REG interrupt map 0x3FF002B0 R/W
APP_PWM0_INTR_MAP_REG interrupt map 0x3FF002B4 R/W
APP_PWM1_INTR_MAP_REG interrupt map 0x3FF002B8 R/W
APP_PWM2_INTR_MAP_REG interrupt map 0x3FF002BC R/W
APP_PWM3_INTR_MAP_REG interrupt map 0x3FF002C0 R/W
APP_LEDC_INT_MAP_REG interrupt map 0x3FF002C4 R/W
APP_EFUSE_INT_MAP_REG interrupt map 0x3FF002C8 R/W
APP_CAN_INT_MAP_REG interrupt map 0x3FF002CC R/W
APP_RTC_CORE_INTR_MAP_REG interrupt map 0x3FF002D0 R/W
APP_RMT_INTR_MAP_REG interrupt map 0x3FF002D4 R/W
APP_PCNT_INTR_MAP_REG interrupt map 0x3FF002D8 R/W
APP_I2C_EXT0_INTR_MAP_REG interrupt map 0x3FF002DC R/W
APP_I2C_EXT1_INTR_MAP_REG interrupt map 0x3FF002E0 R/W
APP_RSA_INTR_MAP_REG interrupt map 0x3FF002E4 R/W
APP_SPI1_DMA_INT_MAP_REG interrupt map 0x3FF002E8 R/W
APP_SPI2_DMA_INT_MAP_REG interrupt map 0x3FF002EC R/W
APP_SPI3_DMA_INT_MAP_REG interrupt map 0x3FF002F0 R/W
APP_WDG_INT_MAP_REG interrupt map 0x3FF002F4 R/W
APP_TIMER_INT1_MAP_REG interrupt map 0x3FF002F8 R/W
APP_TIMER_INT2_MAP_REG interrupt map 0x3FF002FC R/W
APP_TG_T0_EDGE_INT_MAP_REG interrupt map 0x3FF00300 R/W
APP_TG_T1_EDGE_INT_MAP_REG interrupt map 0x3FF00304 R/W
APP_TG_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF00308 R/W
Espressif Systems 98 ESP32 Technical Reference Manual V4.0
5. DPort Register
Name Description Address Access
APP_TG_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF0030C R/W
APP_TG1_T0_EDGE_INT_MAP_REG interrupt map 0x3FF00310 R/W
APP_TG1_T1_EDGE_INT_MAP_REG interrupt map 0x3FF00314 R/W
APP_TG1_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF00318 R/W
APP_TG1_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF0031C R/W
APP_MMU_IA_INT_MAP_REG interrupt map 0x3FF00320 R/W
APP_MPU_IA_INT_MAP_REG interrupt map 0x3FF00324 R/W
APP_CACHE_IA_INT_MAP_REG interrupt map 0x3FF00328 R/W
AHBLITE_MPU_TABLE_UART_REG MPU for peripherals 0x3FF0032C R/W
AHBLITE_MPU_TABLE_SPI1_REG MPU for peripherals 0x3FF00330 R/W
AHBLITE_MPU_TABLE_SPI0_REG MPU for peripherals 0x3FF00334 R/W
AHBLITE_MPU_TABLE_GPIO_REG MPU for peripherals 0x3FF00338 R/W
AHBLITE_MPU_TABLE_RTC_REG MPU for peripherals 0x3FF00348 R/W
AHBLITE_MPU_TABLE_IO_MUX_REG MPU for peripherals 0x3FF0034C R/W
AHBLITE_MPU_TABLE_HINF_REG MPU for peripherals 0x3FF00354 R/W
AHBLITE_MPU_TABLE_UHCI1_REG MPU for peripherals 0x3FF00358 R/W
AHBLITE_MPU_TABLE_I2S0_REG MPU for peripherals 0x3FF00364 R/W
AHBLITE_MPU_TABLE_UART1_REG MPU for peripherals 0x3FF00368 R/W
AHBLITE_MPU_TABLE_I2C_EXT0_REG MPU for peripherals 0x3FF00374 R/W
AHBLITE_MPU_TABLE_UHCI0_REG MPU for peripherals 0x3FF00378 R/W
AHBLITE_MPU_TABLE_SLCHOST_REG MPU for peripherals 0x3FF0037C R/W
AHBLITE_MPU_TABLE_RMT_REG MPU for peripherals 0x3FF00380 R/W
AHBLITE_MPU_TABLE_PCNT_REG MPU for peripherals 0x3FF00384 R/W
AHBLITE_MPU_TABLE_SLC_REG MPU for peripherals 0x3FF00388 R/W
AHBLITE_MPU_TABLE_LEDC_REG MPU for peripherals 0x3FF0038C R/W
AHBLITE_MPU_TABLE_EFUSE_REG MPU for peripherals 0x3FF00390 R/W
AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG MPU for peripherals 0x3FF00394 R/W
AHBLITE_MPU_TABLE_PWM0_REG MPU for peripherals 0x3FF0039C R/W
AHBLITE_MPU_TABLE_TIMERGROUP_REG MPU for peripherals 0x3FF003A0 R/W
AHBLITE_MPU_TABLE_TIMERGROUP1_REG MPU for peripherals 0x3FF003A4 R/W
AHBLITE_MPU_TABLE_SPI2_REG MPU for peripherals 0x3FF003A8 R/W
AHBLITE_MPU_TABLE_SPI3_REG MPU for peripherals 0x3FF003AC R/W
AHBLITE_MPU_TABLE_APB_CTRL_REG MPU for peripherals 0x3FF003B0 R/W
AHBLITE_MPU_TABLE_I2C_EXT1_REG MPU for peripherals 0x3FF003B4 R/W
AHBLITE_MPU_TABLE_SDIO_HOST_REG MPU for peripherals 0x3FF003B8 R/W
AHBLITE_MPU_TABLE_EMAC_REG MPU for peripherals 0x3FF003BC R/W
AHBLITE_MPU_TABLE_PWM1_REG MPU for peripherals 0x3FF003C4 R/W
AHBLITE_MPU_TABLE_I2S1_REG MPU for peripherals 0x3FF003C8 R/W
AHBLITE_MPU_TABLE_UART2_REG MPU for peripherals 0x3FF003CC R/W
AHBLITE_MPU_TABLE_PWM2_REG MPU for peripherals 0x3FF003D0 R/W
AHBLITE_MPU_TABLE_PWM3_REG MPU for peripherals 0x3FF003D4 R/W
AHBLITE_MPU_TABLE_PWR_REG MPU for peripherals 0x3FF003E4 R/W
Espressif Systems 99 ESP32 Technical Reference Manual V4.0
5. DPort Register
Name Description Address Access
IMMU_TABLE0_REG MMU register 1 for internal SRAM 0 0x3FF00504 R/W
IMMU_TABLE1_REG MMU register 1 for internal SRAM 0 0x3FF00508 R/W
IMMU_TABLE2_REG MMU register 1 for Internal SRAM 0 0x3FF0050C R/W
IMMU_TABLE3_REG MMU register 1 for internal SRAM 0 0x3FF00510 R/W
IMMU_TABLE4_REG MMU register 1 for internal SRAM 0 0x3FF00514 R/W
IMMU_TABLE5_REG MMU register 1 for internal SRAM 0 0x3FF00518 R/W
IMMU_TABLE6_REG MMU register 1 for internal SRAM 0 0x3FF0051C R/W
IMMU_TABLE7_REG MMU register 1 for internal SRAM 0 0x3FF00520 R/W
IMMU_TABLE8_REG MMU register 1 for internal SRAM 0 0x3FF00524 R/W
IMMU_TABLE9_REG MMU register 1 for internal SRAM 0 0x3FF00528 R/W
IMMU_TABLE10_REG MMU register 1 for internal SRAM 0 0x3FF0052C R/W
IMMU_TABLE11_REG MMU register 1 for internal SRAM 0 0x3FF00530 R/W
IMMU_TABLE12_REG MMU register 1 for Internal SRAM 0 0x3FF00534 R/W
IMMU_TABLE13_REG MMU register 1 for internal SRAM 0 0x3FF00538 R/W
IMMU_TABLE14_REG MMU register 1 for internal SRAM 0 0x3FF0053C R/W
IMMU_TABLE15_REG MMU register 1 for internal SRAM 0 0x3FF00540 R/W
DMMU_TABLE0_REG MMU register 1 for Internal SRAM 2 0x3FF00544 R/W
DMMU_TABLE1_REG MMU register 1 for internal SRAM 2 0x3FF00548 R/W
DMMU_TABLE2_REG MMU register 1 for internal SRAM 2 0x3FF0054C R/W
DMMU_TABLE3_REG MMU register 1 for internal SRAM 2 0x3FF00550 R/W
DMMU_TABLE4_REG MMU register 1 for internal SRAM 2 0x3FF00554 R/W
DMMU_TABLE5_REG MMU register 1 for internal SRAM 2 0x3FF00558 R/W
DMMU_TABLE6_REG MMU register 1 for internal SRAM 2 0x3FF0055C R/W
DMMU_TABLE7_REG MMU register 1 for internal SRAM 2 0x3FF00560 R/W
DMMU_TABLE8_REG MMU register 1 for internal SRAM 2 0x3FF00564 R/W
DMMU_TABLE9_REG MMU register 1 for internal SRAM 2 0x3FF00568 R/W
DMMU_TABLE10_REG MMU register 1 for internal SRAM 2 0x3FF0056C R/W
DMMU_TABLE11_REG MMU register 1 for internal SRAM 2 0x3FF00570 R/W
DMMU_TABLE12_REG MMU register 1 for internal SRAM 2 0x3FF00574 R/W
DMMU_TABLE13_REG MMU register 1 for internal SRAM 2 0x3FF00578 R/W
DMMU_TABLE14_REG MMU register 1 for internal SRAM 2 0x3FF0057C R/W
DMMU_TABLE15_REG MMU register 1 for internal SRAM 2 0x3FF00580 R/W
SECURE_BOOT_CTRL_REG mode for secure_boot 0x3FF005A4 R/W
SPI_DMA_CHAN_SEL_REG
selects DMA channel for SPI1, SPI2,
and SPI3
0x3FF005A8 R/W
Espressif Systems 100 ESP32 Technical Reference Manual V4.0
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