Espressif Systems ESP32 Service Manual
ESP32 Technical Reference Manual
Espressif Systems
August 31, 2016
About This Manual
ESP32 Technical Reference Manual targets application developers. The manual provides detailed and
complete information on how to use the ESP32 memory and peripherals.
Release Notes
Date Version Release notes
2016.08 V1.0 Initial release.
Disclaimer and Copyright Notice
Information in this document, including URL references, is subject to change without notice. THIS DOCUMENT
IS PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF
MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY
OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
All liability, including liability for infringement of any proprietary rights, relating to use of information in this
document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property
rights are granted herein. The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth
logo is a registered trademark of Bluetooth SIG.
All trade names, trademarks and registered trademarks mentioned in this document are property of their
respective owners, and are hereby acknowledged.
Copyright © 2016 Espressif Inc. All rights reserved.
Contents
1 System and Memory 8
1.1 Introduction 8
1.2 Features 8
1.3 Functional Description 10
1.3.1 Address Mapping 10
1.3.2 Embedded Memory 10
1.3.2.1 Internal ROM 0 11
1.3.2.2 Internal ROM 1 11
1.3.2.3 Internal SRAM 0 12
1.3.2.4 Internal SRAM 1 12
1.3.2.5 Internal SRAM 2 13
1.3.2.6 DMA 13
1.3.2.7 RTC FAST Memory 13
1.3.2.8 RTC SLOW Memory 13
1.3.3 External Memory 13
1.3.4 Peripherals 14
1.3.4.1 Asymmetric PID Controller Peripheral 15
1.3.4.2 Non-Contiguous Peripheral Memory Ranges 15
1.3.4.3 Memory Speed 16
2 Interrupt Matrix 17
2.1 Introduction 17
2.2 Features 17
2.3 Functional Description 17
2.3.1 Peripheral Interrupt Source 17
2.3.2 CPU Interrupt 20
2.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU 20
2.3.4 CPU NMI Interrupt Mask 21
2.3.5 Query Current Interrupt Status of Peripheral Interrupt Source 21
3 Reset and Clock 22
3.1 System Reset 22
3.1.1 Introduction 22
3.1.2 Reset Source 22
3.2 System Clock 23
3.2.1 Introduction 23
3.2.2 Clock Source 24
3.2.3 CPU Clock 24
3.2.4 Peripheral Clock 25
3.2.4.1 APB_CLK Source 25
3.2.4.2 REF_TICK Source 26
3.2.4.3 LEDC_SCLK Source 26
3.2.4.4 APLL_SCLK Source 26
3.2.4.5 PLL_D2_CLK Source 26
3.2.4.6 Clock Source Considerations 27
3.2.5 Wi-Fi BT Clock 27
3.2.6 RTC Clock 27
4 IO_MUX and GPIO Matrix 28
4.1 Introduction 28
4.2 Peripheral Input via GPIO Matrix 29
4.2.1 Summary 29
4.2.2 Functional Description 29
4.2.3 Simple GPIO Input 30
4.3 Peripheral Output via GPIO Matrix 30
4.3.1 Summary 30
4.3.2 Functional Description 30
4.3.3 Simple GPIO Output 31
4.4 Direct I/O via IO_MUX 31
4.4.1 Summary 31
4.4.2 Functional Description 32
4.5 RTC IO_MUX for Low Power and Analog I/O 32
4.5.1 Summary 32
4.5.2 Functional Description 32
4.6 Light-sleep Mode Pin Functions 32
4.7 Pad Hold Feature 33
4.8 I/O Pad Power Supply 33
4.8.1 VDD_SDIO Power Domain 33
4.9 Peripheral Signal List 34
4.10 IO_MUX Pad List 38
4.11 RTC_MUX Pin List 39
4.12 Register Summary 40
4.13 Registers 45
5 LED_PWM 66
5.1 Introduction 66
5.2 Functional Description 66
5.2.1 Architecture 66
5.2.2 Timers 67
5.2.3 Channels 67
5.2.4 Interrupts 68
5.3 Register Summary 68
5.4 Registers 71
6 Remote Controller Peripheral 81
6.1 Introduction 81
6.2 Functional Description 81
6.2.1 RMT Architecture 81
6.2.2 RMT RAM 82
6.2.3 Clock 82
6.2.4 Transmitter 82
6.2.5 Receiver 83
6.2.6 Interrupts 83
6.3 Register Summary 84
6.4 Registers 85
7 PULSE_CNT 90
7.1 Introduction 90
7.2 Functional Description 90
7.2.1 Architecture 90
7.2.2 Counter Channel Inputs 90
7.2.3 Watchpoints 91
7.2.4 Examples 92
7.2.5 Interrupts 92
7.3 Register Summary 92
7.4 Registers 94
8 64-bit Timers 98
8.1 Introduction 98
8.2 Functional Description 98
8.2.1 16-bit Prescaler 98
8.2.2 64-bit Time-base Counter 98
8.2.3 Alarm Generation 99
8.2.4 MWDT 99
8.2.5 Interrupts 99
8.3 Register summary 99
8.4 Registers 101
9 Watchdog Timers 108
9.1 Introduction 108
9.2 Features 108
9.3 Functional Description 108
9.3.1 Clock 108
9.3.1.1 Operating Procedure 109
9.3.1.2 Write Protection 109
9.3.1.3 Flash Boot Protection 109
9.3.1.4 Registers 110
10 AES Accelerator 111
10.1 Introduction 111
10.2 Features 111
10.3 Functional Description 111
10.3.1 AES Algorithm Operations 111
10.3.2 Key, Plaintext and Ciphertext 111
10.3.3 Endianness 112
10.3.4 Encryption and Decryption Operations 114
10.3.5 Speed 114
10.4 Register summary 114
10.5 Registers 116
11 SHA Accelerator 118
11.1 Introduction 118
11.2 Features 118
11.3 Functional Description 118
11.3.1 Padding and Parsing the Message 118
11.3.2 Message Digest 118
11.3.3 Hash Operation 119
11.3.4 Speed 119
11.4 Register Summary 119
11.5 Registers 121
List of Tables
1 Address Mapping 10
2 Embedded Memory Address Mapping 11
3 Module with DMA 13
4 External Memory Address Mapping 14
5 Peripheral Address Mapping 14
6 PRO_CPU, APP_CPU interrupt configuration 18
7 CPU Interrupts 20
8 PRO_CPU and APP_CPU reset reason values 22
9 CPU_CLK Source 24
10 CPU_CLK Derivation 25
11 Peripheral Clock Usage 25
12 APB_CLK Derivation 26
13 REF_TICK Derivation 26
14 LEDC_SCLK Derivation 26
15 IO_MUX Light-sleep Pin Function Registers 32
16 GPIO Matrix Peripheral Signals 34
17 IO_MUX Pad Summary 38
18 RTC_MUX Pin Summary 39
26 Operation Mode 111
27 AES Text Endianness 112
28 AES-128 Key Endianness 113
29 AES-192 Key Endianness 113
30 AES-256 Key Endianness 113
List of Figures
1 System Structure 9
2 System Address Mapping 9
3 Interrupt Matrix Structure 17
4 System Reset 22
5 System Clock 23
6 IO_MUX, RTC IO_MUX and GPIO Matrix Overview 28
7 Peripheral Input via IO_MUX, GPIO Matrix 29
8 Output via GPIO Matrix 31
9 ESP32 I/O Pad Power Sources 33
10 LED_PWM Architecture 66
11 LED_PWM High-speed Channel Diagram 66
12 LED PWM Output Signal Diagram 67
13 Output Signal Diagram of Gradient Duty Cycle 68
14 RMT Architecture 81
15 Data Structure 82
16 PULSE_CNT Architecture 90
17 PULSE_CNT Upcounting Diagram 92
18 PULSE_CNT Downcounting Diagram 92
1 SYSTEM AND MEMORY
1. System and Memory
1.1 Introduction
The ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs. All embedded memory,
external memory and peripherals are located on the data bus and/or the instruction bus of these CPUs.
With some minor exceptions (see below), the address mapping of two CPUs is symmetric, meaning they use the
same addresses to access the same memory. Multiple peripherals in the system can access embedded memory
via DMA.
The two CPUs are named “PRO_CPU” and “APP_CPU” (for “protocol” and “application”), however for most
purposes the two CPUs are interchangeable.
1.2 Features
• Address Space
– Symmetric address mapping
– 4 GB (32-bit) address space for both data bus and instruction bus
– 1296 KB embedded memory address space
– 19704 KB external memory address space
– 512 KB peripheral address space
– Some embedded and external memory regions can be accessed by either data bus or instruction bus
– 328 KB DMA address space
• Embedded Memory
– 448 KB Internal ROM
– 520 KB Internal SRAM
– 8 KB RTC FAST Memory
– 8 KB RTC SLOW Memory
• External Memory
Off-chip SPI memory can be mapped into the available address space as external memory. Parts of the
embedded memory can be used as transparent cache for this external memory.
– Supports up to 16 MB off-Chip SPI Flash.
– Supports up to 8 MB off-Chip SPI SRAM.
• Peripherals
– 41 peripherals
• DMA
– 13 modules are capable of DMA operation
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1.2 Features 1 SYSTEM AND MEMORY
Figure 1 block diagram illustrates the system structure, the block diagram in Figure 2 illustrates the address map
structure.
Figure 1: System Structure
Figure 2: System Address Mapping
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1.3 Functional Description 1 SYSTEM AND MEMORY
1.3 Functional Description
1.3.1 Address Mapping
Each of the two Harvard Architecture Xtensa LX6 CPUs has 4 GB (32-bit) address space. Address spaces are
symmetric between the two CPUs.
Addresses below 0x4000_0000 are serviced using the data bus. Addresses in the range 0x4000_0000 ~
0x4FFF_FFFF are serviced using the instruction bus. Finally, addresses over and including 0x5000_0000 are
shared by the data and instruction bus.
The data bus and instruction bus are both little-endian: for example, byte addresses 0x0, 0x1, 0x2, 0x3 access
the least significant, second least significant, second most significant, and most significant bytes of the 32-bit
word stored at address 0x0, respectively. The CPU can access data bus addresses via aligned or non-aligned
byte, half-word and word read and write operations. The CPU can read and write data through the instruction
bus, but only in a word aligned manner; non-word-aligned access will cause a CPU exception.
Each CPU can directly access embedded memory through both the data bus and the instruction bus, external
memory which is mapped into the address space (via transparent caching & MMU) and peripherals. Table 1
illustrates address ranges that can be accessed by each CPU’s data bus and instruction bus.
Some embedded memories and some external memories can be accessed via the data bus or the instruction
bus. In these cases, the same memory is available to either of the CPUs at two address ranges.
Table 1: Address Mapping
Bus Type
Data 0x3F40_0000 0x3F7F_FFFF 4 MB External Memory
Data 0x3F80_0000 0x3FBF_FFFF 4 MB External Memory
Data 0x3FF0_0000 0x3FF7_FFFF 512 KB Peripheral
Data 0x3FF8_0000 0x3FFF_FFFF 512 KB Embedded Memory
Instruction 0x4000_0000 0x400C_1FFF 776 KB Embedded Memory
Instruction 0x400C_2000 0x40BF_FFFF 11512 KB External Memory
Data Instruction 0x5000_0000 0x5000_1FFF 8 KB Embedded Memory
Low Address High Address
0x0000_0000 0x3F3F_FFFF Reserved
0x3FC0_0000 0x3FEF_FFFF 3 MB Reserved
0x40C0_0000 0x4FFF_FFFF 244 MB Reserved
0x5000_2000 0xFFFF_FFFF Reserved
Boundary Address
Size Target
1.3.2 Embedded Memory
The Embedded Memory consists of four segments: internal ROM (448 KB), internal SRAM (520 KB), RTC FAST
memory (8 KB) and RTC SLOW memory (8 KB).
The 448 KB internal ROM is divided into two parts: Internal ROM 0 (384 KB) and Internal ROM 1 (64 KB).
The 520 KB internal SRAM is divided into three parts: Internal SRAM 0 (192 KB), Internal SRAM 1 (128 KB), and
Internal SRAM 2 (200 KB).
RTC FAST Memory and RTC SLOW Memory are both implemented as SRAM.
Table 2 lists all embedded memories and their address ranges on the data and instruction buses.
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1.3 Functional Description 1 SYSTEM AND MEMORY
Table 2: Embedded Memory Address Mapping
Bus Type
Data 0x3FF8_0000 0x3FF8_1FFF 8 KB RTC FAST Memory PRO_CPU Only
Data 0x3FF9_0000 0x3FF9_FFFF 64 KB Internal ROM 1 -
Data 0x3FFA_E000 0x3FFD_FFFF 200 KB Internal SRAM 2 DMA
Data 0x3FFE_0000 0x3FFF_FFFF 128 KB Internal SRAM 1 DMA
Bus Type
Instruction 0x4000_0000 0x4000_7FFF 32 KB Internal ROM 0 Remap
Instruction 0x4000_8000 0x4005_FFFF 352 KB Internal ROM 0 -
Instruction 0x4007_0000 0x4007_FFFF 64 KB Internal SRAM 0 Cache
Instruction 0x4008_0000 0x4009_FFFF 128 KB Internal SRAM 0 -
Instruction 0x400A_0000 0x400A_FFFF 64 KB Internal SRAM 1 -
Instruction 0x400B_0000 0x400B_7FFF 32 KB Internal SRAM 1 Remap
Instruction 0x400B_8000 0x400B_FFFF 32 KB Internal SRAM 1 -
Instruction 0x400C_0000 0x400C_1FFF 8 KB RTC FAST Memory PRO_CPU Only
Bus Type
Data Instruc-
tion
Low Address High Address
0x3FF8_2000 0x3FF8_FFFF 56 KB Reserved -
0x3FFA_0000 0x3FFA_DFFF 56 KB Reserved -
Low Address High Address
0x4006_0000 0x4006_FFFF 64 KB Reserved -
Low Address High Address
0x5000_0000 0x5000_1FFF 8 KB RTC SLOW Memory -
Boundary Address
Boundary Address
Boundary Address
Size Target Comment
Size Target Comment
Size Target Comment
1.3.2.1 Internal ROM 0
The capacity of Internal ROM 0 is 384 KB, It is accessible by both CPUs through the address range
0x4000_0000 ~ 0x4005_FFFF, which is on the instruction bus.
The address range of the first 32 KB of the ROM 0 (0x4000_0000 ~ 0x4000_7FFF) can be re-mapped to access
a part of Internal SRAM 1 that normally resides in the memory range 0x400B_0000 ~ 0x400B_7FFF instead.
While remapping, such 32 KB SRAM can not be accessed by address range 0x400B_0000 ~ 0x400B_7FFF any
more, but it can still be accessible through the data bus (0x3FFE_8000 ~ 0x3FFE_FFFF). This can be done on a
per-CPU basis: setting bit 0 of register DPORT_PRO_BOOT_REMAP_CTRL_REG or
DPORT_APP_BOOT_REMAP_CTRL_REG will remap SRAM for the PRO_CPU and APP_CPU,
respectively.
1.3.2.2 Internal ROM 1
The capacity of Internal ROM 1 is 64 KB. It can be read by either CPU at address range 0x3FF9_0000 ~
0x3FF9_FFFF of the data bus.
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1.3 Functional Description 1 SYSTEM AND MEMORY
1.3.2.3 Internal SRAM 0
The capacity of Internal SRAM 0 is 192 KB. Hardware can be configured to use the first 64KB to cache external
memory access. When not used as cache, the first 64KB can be read and written by either CPU at addresses
0x4007_0000 ~ 0x4007_7FFF of the instruction bus. The remaining 128 KB can always be read and written by
either CPU at addresses 0x4007_8000 ~ 0x4007_FFFF of instruction bus.
1.3.2.4 Internal SRAM 1
The capacity of Internal SRAM 1 is 128 KB. Either CPU can read and write this memory at addresses
0x3FFE_0000 ~ 0x3FFF_FFFF of the data bus, and also at addresses 0x400A_0000 ~ 0x400B_FFFF of the
instruction bus.
The address range accessed via the instruction bus is in reverse order (word-wise) compared to access via the
data bus. That is to say, address
0x3FFE_0000 and 0x400B_FFFC access the same word
0x3FFE_0004 and 0x400B_FFF8 access the same word
0x3FFE_0008 and 0x400B_FFF4 access the same word
……
0x3FFF_FFF4 and 0x400A_0008 access the same word
0x3FFF_FFF8 and 0x400A_0004 access the same word
0x3FFF_FFFC and 0x400A_0000 access the same word
The data bus and instruction bus of the CPU are still both little endian, so the byte order of individual words is not
reversed between address spaces. For example, address
0x3FFE_0000 accesses the least significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0001 accesses the second least significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0002 accesses the second most significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0003 accesses the most significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0004 accesses the least significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0005 accesses the second least significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0006 accesses the second most significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0007 accesses the most significant byte in the word accessed by 0x400B_FFF8.
……
0x3FFF_FFF8 accesses the least significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFF9 accesses the second least significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFA accesses the second most significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFB accesses the most significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFC accesses the least significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFD accesses the second most significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFE accesses the second most significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFF accesses the most significant byte in the word accessed by 0x400A_0000.
Part of this memory can be remapped to the ROM 0 address space. See Internal Rom 0 for more
information.
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1.3 Functional Description 1 SYSTEM AND MEMORY
1.3.2.5 Internal SRAM 2
The capacity of Internal SRAM 2 is 200 KB. It can be read and written by either CPU at addresses 0x3FFA_E000
~ 0x3FFD_FFFF on the data bus.
1.3.2.6 DMA
DMA uses the same addressing as the CPU data bus to read and write Internal SRAM 1 and Internal SRAM 2.
This means DMA uses address range 0x3FFE_0000 ~ 0x3FFF_FFFF to read and write Internal SRAM 1 and
address range 0x3FFA_E000 ~ 0x3FFD_FFFF to read and write Internal SRAM 2.
In the ESP32, 13 peripherals are equipped with DMA. Table 3 lists these peripherals.
Table 3: Module with DMA
UART0 UART1 UART2
SPI1 SPI2 SPI3
I2S0 I2S1
SDIO Slave SDMMC
EMAC
BT WIFI
1.3.2.7 RTC FAST Memory
RTC FAST Memory is 8 KB of SRAM. It can be read and written by PRO_CPU only at address range
0x3FF8_0000 ~ 0x3FF8_1FFF on the data bus or address range 0x400C_0000 ~ 0x400C_1FFF on the
instruction bus. Unlike most other memory regions, RTC FAST memory cannot be accessed by the
APP_CPU.
The two address ranges of PRO_CPU access RTC FAST Memory in the same order, so for example, address
0x3FF8_0000 and 0x400C_0000 access the same word. On the APP_CPU, these address ranges do not
provide access to RTC FAST Memory or any other memory location.
1.3.2.8 RTC SLOW Memory
RTC SLOW Memory is 8 KB of SRAM which can be read from and written by either CPU at address range
0x5000_0000 ~ 0x5000_1FFF. This address range is shared by both the data bus and the instruction bus.
1.3.3 External Memory
The ESP32 can access external SPI flash and SPI SRAM as external memory. Table 4 provides a list of external
memories that can be accessed by either CPU at a range of addresses on the data and instruction buses. When
a CPU accesses external memory through the Cache and MMU, the cache will map the CPU’s address to an
external physical memory address (in the external memory’s address space), according to the MMU settings. Due
to this address mapping, the ESP32 can address up to 16 MB External Flash and 8 MB External SRAM.
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1.3 Functional Description 1 SYSTEM AND MEMORY
Table 4: External Memory Address Mapping
Bus Type
Data 0x3F40_0000 0x3F7F_FFFF 4 MB External Flash Read
Data 0x3F80_0000 0x3FBF_FFFF 4 MB External SRAM Read and Write
Bus Type
Instruction 0x400C_2000 0x40BF_FFFF 11512 KB External Flash Read
Low Address High Address
Low Address High Address
Boundary Address
Boundary Address
Size Target Comment
Size Target Comment
1.3.4 Peripherals
The ESP32 has 41 peripherals. Table 5 specifically describes the peripherals their respective address ranges.
Almost all peripheral modules can be accessed by either CPU at the same address, the only exception being the
PID Controller.
Table 5: Peripheral Address Mapping
Bus Type
Data 0x3FF0_0000 0x3FF0_0FFF 4 KB DPort Register
Data 0x3FF0_1000 0x3FF0_1FFF 4 KB AES Accelerator
Data 0x3FF0_2000 0x3FF0_2FFF 4 KB RSA Accelerator
Data 0x3FF0_3000 0x3FF0_3FFF 4 KB SHA Accelerator
Data 0x3FF0_4000 0x3FF0_4FFF 4 KB Secure Boot
Data 0x3FF1_0000 0x3FF1_3FFF 16 KB Cache MMU Table
Data 0x3FF1_F000 0x3FF1_FFFF 4 KB PID Controller Per-CPU peripheral
Data 0x3FF4_0000 0x3FF4_0FFF 4 KB UART0
Data 0x3FF4_2000 0x3FF4_2FFF 4 KB SPI1
Data 0x3FF4_3000 0x3FF4_3FFF 4 KB SPI0
Data 0x3FF4_4000 0x3FF4_4FFF 4 KB GPIO
Data 0x3FF4_8000 0x3FF4_8FFF 4 KB RTC
Data 0x3FF4_9000 0x3FF4_9FFF 4 KB IO MUX
Data 0x3FF4_B000 0x3FF4_BFFF 4 KB SDIO Slave One of three parts
Data 0x3FF4_C000 0x3FF4_CFFF 4 KB UDMA1
Data 0x3FF4_F000 0x3FF4_FFFF 4 KB I2S0
Data 0x3FF5_0000 0x3FF5_0FFF 4 KB UART1
Data 0x3FF5_3000 0x3FF5_3FFF 4 KB I2C0
Data 0x3FF5_4000 0x3FF5_4FFF 4 KB UDMA0
Low Address High Address
0x3FF0_5000 0x3FF0_FFFF 44 KB Reserved
0x3FF1_4000 0x3FF1_EFFF 44 KB Reserved
0x3FF2_0000 0x3FF3_FFFF 128 KB Reserved
0x3FF4_1000 0x3FF4_1FFF 4 KB Reserved
0x3FF4_5000 0x3FF4_7FFF 12 KB Reserved
0x3FF4_A000 0x3FF4_AFFF 4 KB Reserved
0x3FF4_D000 0x3FF4_EFFF 8 KB Reserved
0x3FF5_1000 0x3FF5_2FFF 8 KB Reserved
Boundary Address
Size Target Comment
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1.3 Functional Description 1 SYSTEM AND MEMORY
Bus Type
Data 0x3FF5_5000 0x3FF5_5FFF 4 KB SDIO Slave One of three parts
Data 0x3FF5_6000 0x3FF5_6FFF 4 KB RMT
Data 0x3FF5_7000 0x3FF5_7FFF 4 KB PCNT
Data 0x3FF5_8000 0x3FF5_8FFF 4 KB SDIO Slave One of three parts
Data 0x3FF5_9000 0x3FF5_9FFF 4 KB LED PWM
Data 0x3FF5_A000 0x3FF5_AFFF 4 KB Efuse Controller
Data 0x3FF5_B000 0x3FF5_BFFF 4 KB Flash Encryption
Data 0x3FF5_E000 0x3FF5_EFFF 4 KB PWM0
Data 0x3FF5_F000 0x3FF5_FFFF 4 KB TIMG0
Data 0x3FF6_0000 0x3FF6_0FFF 4 KB TIMG1
Data 0x3FF6_4000 0x3FF6_4FFF 4 KB SPI2
Data 0x3FF6_5000 0x3FF6_5FFF 4 KB SPI3
Data 0x3FF6_6000 0x3FF6_6FFF 4 KB SYSCON
Data 0x3FF6_7000 0x3FF6_7FFF 4 KB I2C1
Data 0x3FF6_8000 0x3FF6_8FFF 4 KB SDMMC
Data 0x3FF6_9000 0x3FF6_AFFF 8 KB EMAC
Data 0x3FF6_C000 0x3FF6_CFFF 4 KB PWM1
Data 0x3FF6_D000 0x3FF6_DFFF 4 KB I2S1
Data 0x3FF6_E000 0x3FF6_EFFF 4 KB UART2
Data 0x3FF6_F000 0x3FF6_FFFF 4 KB PWM2
Data 0x3FF7_0000 0x3FF7_0FFF 4 KB PWM3
Data 0x3FF7_5000 0x3FF7_5FFF 4 KB RNG
Low Address High Address
0x3FF5_C000 0x3FF5_DFFF 8 KB Reserved
0x3FF6_1000 0x3FF6_3FFF 12 KB Reserved
0x3FF6_B000 0x3FF6_BFFF 4 KB Reserved
0x3FF7_1000 0x3FF7_4FFF 16 KB Reserved
0x3FF7_6000 0x3FF7_FFFF 40 KB Reserved
Boundary Address
Size Target Comment
1.3.4.1 Asymmetric PID Controller Peripheral
There are two PID Controllers in the system. They serve the PRO_CPU and the APP_CPU, respectively. The
PRO_CPU and the APP_CPU can only access their own PID Controller and not their counterpart’s PID
Controller. Each CPU uses the same memory range 0x3FF1_F000 ~ 3FF1_FFFF to access its own PID
Controller.
1.3.4.2 Non-Contiguous Peripheral Memory Ranges
The SDIO Slave peripheral consists of three parts and the two CPUs use non-contiguous addresses to access
these. The three parts are accessed at the address ranges 0x3FF4_B000 ~ 3FF4_BFFF, 0x3FF5_5000 ~
3FF5_5FFF and 0x3FF5_8000 ~ 3FF5_8FFF of each CPU’s data bus. Similar to other peripherals, access to this
peripheral is identical for both CPUs.
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1.3 Functional Description 1 SYSTEM AND MEMORY
1.3.4.3 Memory Speed
The ROM as well as the SRAM are both clocked from CPU_CLK and can be accessed by the CPU in a single
cycle. The RTC FAST memory is clocked from the APB_CLOCK and the RTC SLOW memory from the
FAST_CLOCK, so access to these memories may be slower. DMA uses the APB_CLK to access memory.
Internally, the SRAM is organized in 32K-sized banks. Each CPU and DMA channel can access the SRAM at full
speed and simultaneously, provided they access address different memory banks.
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2 INTERRUPT MATRIX
2. Interrupt Matrix
2.1 Introduction
The Interrupt Matrix embedded in the ESP32 independently allocates peripheral interrupt sources to the two
CPUs’ peripheral interrupts. This configuration is highly flexible in order to meet many different needs.
2.2 Features
• Accepts 71 peripheral interrupt sources as input.
• Generates 26 peripheral interrupt sources per CPU as output (52 total).
• CPU NMI Interrupt Mask.
• Queries current interrupt status of peripheral interrupt sources.
The structure of the Interrupt Matrix is shown in Figure 3.
Figure 3: Interrupt Matrix Structure
2.3 Functional Description
2.3.1 Peripheral Interrupt Source
ESP32 has 71 peripheral interrupt sources in total. All peripheral interrupt sources are listed in table 6. 67 of 71
ESP32 peripheral interrupt sources can be allocated to either CPU.
The four remaining peripheral interrupt sources are CPU-specific, two per CPU. GPIO_INTERRUPT_PRO and
GPIO_INTERRUPT_PRO_NMI can only be allocated to PRO_CPU. GPIO_INTERRUPT_APP and
GPIO_INTERRUPT_APP_NMI can only be allocated to APP_CPU. As a result, PRO_CPU and APP_CPU each
have 69 peripheral interrupt sources.
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Table 6: PRO_CPU, APP_CPU interrupt configuration
2.3 Functional Description 2 INTERRUPT MATRIX
PRO_CPU APP_CPU
Peripheral Interrupt
Configuration Register
PRO_MAC_INTR_MAP_REG 0
PRO_MAC_NMI_MAP_REG 1 1 MAC_NMI 1 1 APP_MAC_NMI_MAP_REG
PRO_BB_INT_MAP_REG 2 2 BB_INT 2 2 APP_BB_INT_MAP_REG
PRO_BT_MAC_INT_MAP_REG 3 3 BT_MAC_INT 3 3 APP_BT_MAC_INT_MAP_REG
PRO_BT_BB_INT_MAP_REG 4 4 BT_BB_INT 4 4 APP_BT_BB_INT_MAP_REG
PRO_BT_BB_NMI_MAP_REG 5 5 BT_BB_NMI 5 5 APP_BT_BB_NMI_MAP_REG
PRO_RWBT_IRQ_MAP_REG 6 6 RWBT_IRQ 6 6 APP_RWBT_IRQ_MAP_REG
PRO_BT_BB_NMI_MAP_REG 5 5 BT_BB_NMI 5 5 APP_BT_BB_NMI_MAP_REG
PRO_RWBT_IRQ_MAP_REG 6 6 RWBT_IRQ 6 6 APP_RWBT_IRQ_MAP_REG
PRO_RWBLE_IRQ_MAP_REG 7 7 RWBLE_IRQ 7 7 APP_RWBLE_IRQ_MAP_REG
PRO_RWBT_NMI_MAP_REG 8 8 RWBT_NMI 8 8 APP_RWBT_NMI_MAP_REG
PRO_RWBLE_NMI_MAP_REG 9 9 RWBLE_NMI 9 9 APP_RWBLE_NMI_MAP_REG
PRO_SLC0_INTR_MAP_REG 10 10 SLC0_INTR 10 10 APP_SLC0_INTR_MAP_REG
PRO_SLC1_INTR_MAP_REG 11 11 SLC1_INTR 11 11 APP_SLC1_INTR_MAP_REG
PRO_UHCI0_INTR_MAP_REG 12 12 UHCI0_INTR 12 12 APP_UHCI0_INTR_MAP_REG
PRO_UHCI1_INTR_MAP_REG 13 13 UHCI1_INTR 13 13 APP_UHCI1_INTR_MAP_REG
PRO_TG_T0_LEVEL_INT_MAP_REG 14 14 TG_T0_LEVEL_INT 14 14 APP_TG_T0_LEVEL_INT_MAP_REG
PRO_TG_T1_LEVEL_INT_MAP_REG 15 15 TG_T1_LEVEL_INT 15 15 APP_TG_T1_LEVEL_INT_MAP_REG
PRO_TG_WDT_LEVEL_INT_MAP_REG 16 16 TG_WDT_LEVEL_INT 16 16 APP_TG_WDT_LEVEL_INT_MAP_REG
PRO_TG_LACT_LEVEL_INT_MAP_REG 17 17 TG_LACT_LEVEL_INT 17 17 APP_TG_LACT_LEVEL_INT_MAP_REG
PRO_TG1_T0_LEVEL_INT_MAP_REG 18 18 TG1_T0_LEVEL_INT 18 18 APP_TG1_T0_LEVEL_INT_MAP_REG
PRO_TG1_T1_LEVEL_INT_MAP_REG 19 19 TG1_T1_LEVEL_INT 19 19 APP_TG1_T1_LEVEL_INT_MAP_REG
PRO_TG1_WDT_LEVEL_INT_MAP_REG 20 20 TG1_WDT_LEVEL_INT 20 20 APP_TG1_WDT_LEVEL_INT_MAP_REG
PRO_TG1_LACT_LEVEL_INT_MAP_REG 21 21 TG1_LACT_LEVEL_INT 21 21 APP_TG1_LACT_LEVEL_INT_MAP_REG
PRO_GPIO_INTERRUPT_PRO_MAP_REG
PRO_GPIO_INTERRUPT_PRO_NMI_MAP_REG
PRO_CPU_INTR_FROM_CPU_0_MAP_REG 24 24 CPU_INTR_FROM_CPU_0 24 24 APP_CPU_INTR_FROM_CPU_0_MAP_REG
PRO_CPU_INTR_FROM_CPU_1_MAP_REG 25 25 CPU_INTR_FROM_CPU_1 25 25 APP_CPU_INTR_FROM_CPU_1_MAP_REG
PRO_CPU_INTR_FROM_CPU_2_MAP_REG 26 26 CPU_INTR_FROM_CPU_2 26 26 APP_CPU_INTR_FROM_CPU_2_MAP_REG
PRO_CPU_INTR_FROM_CPU_3_MAP_REG 27 27 CPU_INTR_FROM_CPU_3 27 27 APP_CPU_INTR_FROM_CPU_3_MAP_REG
PRO_SPI_INTR_0_MAP_REG 28 28 SPI_INTR_0 28 28 APP_SPI_INTR_0_MAP_REG
PRO_SPI_INTR_1_MAP_REG 29 29 SPI_INTR_1 29 29 APP_SPI_INTR_1_MAP_REG
PRO_SPI_INTR_2_MAP_REG 30 30 SPI_INTR_2 30 30 APP_SPI_INTR_2_MAP_REG
PRO_SPI_INTR_3_MAP_REG 31 31 SPI_INTR_3 31 31 APP_SPI_INTR_3_MAP_REG
PRO_I2S0_INT_MAP_REG 0
PRO_I2S1_INT_MAP_REG 1 33 I2S1_INT 33 1 APP_I2S1_INT_MAP_REG
PRO_UART_INTR_MAP_REG 2 34 UART_INTR 34 2 APP_UAR T_INTR_MAP_REG
PRO_UART1_INTR_MAP_REG 3 35 UART1_INTR 35 3 APP_UART1_INTR_MAP_REG
PRO_UART2_INTR_MAP_REG 4 36 UART2_INTR 36 4 APP_UART2_INTR_MAP_REG
PRO_SDIO_HOST_INTERRUPT_MAP_REG 5 37 SDIO_HOST_INTERRUPT 37 5 APP_SDIO_HOST_INTERRUPT_MAP_REG
PRO_EMAC_INT_MAP_REG 6 38 EMAC_INT 38 6 APP_EMAC_INT_MAP_REG
PRO_PWM0_INTR_MAP_REG 7 39 PWM0_INTR 39 7 APP_PWM0_INTR_MAP_REG
PRO_PWM1_INTR_MAP_REG 8 40 PWM1_INTR 40 8 APP_PWM1_INTR_MAP_REG
PRO_PWM2_INTR_MAP_REG 9 41 PWM2_INTR 41 9 APP_PWM2_INTR_MAP_REG
PRO_PWM3_INTR_MAP_REG 10 42 PWM3_INTR 42 10 APP_PWM3_INTR_MAP_REG
PRO_LEDC_INT_MAP_REG 11 43 LEDC_INT 43 11 APP_LEDC_INT_MAP_REG
PRO_EFUSE_INT_MAP_REG 12 44 EFUSE_INT 44 12 APP_EFUSE_INT_MAP_REG
PRO_CAN_INT_MAP_REG 13 45 CAN_INT 45 13 APP_CAN_INT_MAP_REG
PRO_RTC_CORE_INTR_MAP_REG 14 46 RTC_CORE_INTR 46 14 APP_R TC_CORE_INTR_MAP_REG
PRO_RMT_INTR_MAP_REG 15 47 RMT_INTR 47 15 APP_RMT_INTR_MAP_REG
PRO_PCNT_INTR_MAP_REG 16 48 PCNT_INTR 48 16 APP_PCNT_INTR_MAP_REG
PRO_I2C_EXT0_INTR_MAP_REG 17 49 I2C_EXT0_INTR 49 17 APP_I2C_EXT0_INTR_MAP_REG
PRO_I2C_EXT1_INTR_MAP_REG 18 50 I2C_EXT1_INTR 50 18 APP_I2C_EXT1_INTR_MAP_REG
PRO_RSA_INTR_MAP_REG 19 51 RSA_INTR 51 19 APP_RSA_INTR_MAP_REG
PRO_SPI1_DMA_INT_MAP_REG 20 52 SPI1_DMA_INT 52 20 APP_SPI1_DMA_INT_MAP_REG
Status Register Status Register
Bit Name
PRO_INTR_STATUS_REG_0
22 22
23 23
PRO_INTR_STATUS_REG_1
No. Name No.
0 MAC_INTR 0
GPIO_INTERRUPT_PRO GPIO_INTERRUPT_APP
GPIO_INTERRUPT_PRO_NMI GPIO_INTERRUPT_APP_NMI
32 I2S0_INT 32
Peripheral Interrupt Source
Name Bit
APP_INTR_STATUS_REG_0
22 22
23 23
APP_INTR_STATUS_REG_1
Peripheral Interrupt
Configuration Register
0 APP_MAC_INTR_MAP_REG
APP_GPIO_INTERRUPT_APP_MAP_REG
APP_GPIO_INTERRUPT_APP_NMI_MAP_REG
0 APP_I2S0_INT_MAP_REG
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PRO_CPU APP_CPU
Peripheral Interrupt
Configuration Register
PRO_SPI2_DMA_INT_MAP_REG 21
PRO_SPI3_DMA_INT_MAP_REG 22 54 SPI3_DMA_INT 54 22 APP_SPI3_DMA_INT_MAP_REG
PRO_WDG_INT_MAP_REG 23 55 WDG_INT 55 23 APP_WDG_INT_MAP_REG
PRO_TIMER_INT1_MAP_REG 24 56 TIMER_INT1 56 24 APP_TIMER_INT1_MAP_REG
PRO_TIMER_INT2_MAP_REG 25 57 TIMER_INT2 57 25 APP_TIMER_INT2_MAP_REG
PRO_TG_T0_EDGE_INT_MAP_REG 26 58 TG_T0_EDGE_INT 58 26 APP_TG_T0_EDGE_INT_MAP_REG
PRO_TG_T1_EDGE_INT_MAP_REG 27 59 TG_T1_EDGE_INT 59 27 APP_TG_T1_EDGE_INT_MAP_REG
PRO_TG_WDT_EDGE_INT_MAP_REG 28 60 TG_WDT_EDGE_INT 60 28 APP_TG_WDT_EDGE_INT_MAP_REG
PRO_TG_LACT_EDGE_INT_MAP_REG 29 61 TG_LACT_EDGE_INT 61 29 APP_TG_LACT_EDGE_INT_MAP_REG
PRO_TG1_T0_EDGE_INT_MAP_REG 30 62 TG1_T0_EDGE_INT 62 30 APP_TG1_T0_EDGE_INT_MAP_REG
PRO_TG1_T1_EDGE_INT_MAP_REG 31 63 TG1_T1_EDGE_INT 63 31 APP_TG1_T1_EDGE_INT_MAP_REG
PRO_TG1_WDT_EDGE_INT_MAP_REG 0
PRO_TG1_LACT_EDGE_INT_MAP_REG 1 65 TG1_LACT_EDGE_INT 65 1 APP_TG1_LACT_EDGE_INT_MAP_REG
PRO_MMU_IA_INT_MAP_REG 2 66 MMU_IA_INT 66 2 APP_MMU_IA_INT_MAP_REG
PRO_MPU_IA_INT_MAP_REG 3 67 MPU_IA_INT 67 3 APP_MPU_IA_INT_MAP_REG
PRO_CACHE_IA_INT_MAP_REG 4 68 CACHE_IA_INT 68 4 APP_CACHE_IA_INT_MAP_REG
Status Register Status Register
Bit Name
PRO_INTR_STATUS_REG_1
PRO_INTR_STATUS_REG_2
No. Name No.
53 SPI2_DMA_INT 53
64 TG1_WDT_EDGE_INT 64
Peripheral Interrupt Source
Name Bit
APP_INTR_STATUS_REG_1
APP_INTR_STATUS_REG_2
Peripheral Interrupt
Configuration Register
21 APP_SPI2_DMA_INT_MAP_REG
0 APP_TG1_WDT_EDGE_INT_MAP_REG
2.3 Functional Description 2 INTERRUPT MATRIX
2.3 Functional Description 2 INTERRUPT MATRIX
2.3.2 CPU Interrupt
Both of the two CPUs (PRO and APP) have 32 interrupts each, of which 26 are peripheral interrupts. All
interrupts in a CPU are listed in Table 7.
Table 7: CPU Interrupts
No. Category Type Priority Level
0 Peripheral Level-Triggered 1
1 Peripheral Level-Triggered 1
2 Peripheral Level-Triggered 1
3 Peripheral Level-Triggered 1
4 Peripheral Level-Triggered 1
5 Peripheral Level-Triggered 1
6 Internal Timer.0 1
7 Internal Software 1
8 Peripheral Level-Triggered 1
9 Peripheral Level-Triggered 1
10 Peripheral Edge-Triggered 1
11 Internal Profiling 3
12 Peripheral Level-Triggered 1
13 Peripheral Level-Triggered 1
14 Peripheral NMI NMI
15 Internal Timer.1 3
16 Internal Timer.2 5
17 Peripheral Level-Triggered 1
18 Peripheral Level-Triggered 1
19 Peripheral Level-Triggered 2
20 Peripheral Level-Triggered 2
21 Peripheral Level-Triggered 2
22 Peripheral Edge-Triggered 3
23 Peripheral Level-Triggered 3
24 Peripheral Level-Triggered 4
25 Peripheral Level-Triggered 4
26 Peripheral Level-Triggered 5
27 Peripheral Level-Triggered 3
28 Peripheral Edge-Triggered 4
29 Internal Software 3
30 Peripheral Edge-Triggered 4
31 Peripheral Level-Triggered 5
2.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU
In this section:
• Source_X stands for any particular peripheral interrupt source.
• PRO_X_MAP_REG (or APP_X_MAP_REG) stands for any particular peripheral interrupt configuration
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2.3 Functional Description 2 INTERRUPT MATRIX
register of the PRO_CPU (or APP_CPU). The peripheral interrupt configuration register corresponds to the
peripheral interrupt source Source_X. Referring to Table 6, the registers listed under “PRO_CPU
(APP_CPU) - Peripheral Interrupt Configuration Register” correspond to the peripheral interrupt sources
listed in “Peripheral Interrupt Source - Name”.
• Interrupt_P stands for CPU peripheral interrupt, numbered as Num_P. Num_P can take the ranges 0 ~ 5, 8
~ 10, 12 ~ 14, 17 ~ 28, 30 ~ 31.
• Interrupt_I stands for CPU internal interrupt numbered as Num_I. Num_I can take values 6, 7, 11, 15, 16,
29.
Using this terminology, the possible operations of the Interrupt Matrix controller can be described as
follows:
• Allocate peripheral interrupt source Source_X to CPU (PRO_CPU or APP_CPU)
Set PRO_X_MAP_REG�or APP_X_MAP_REG�to Num_P. Num_P can be any CPU peripheral interrupt
number. CPU interrupts can be shared between multiple peripherals (see below).
• Disable peripheral interrupt source Source_X for CPU (PRO_CPU or APP_CPU)
Set PRO_X_MAP_REG�or APP_X _MAP_REG�for peripheral interrupt source to any Num_I. The specific
choice of internal interrupt number does not change behaviour, as none of the interrupt numbered as
Num_I are connected to either CPU.
• Allocate multiple peripheral sources Source_Xn ORed to PRO_CPU (APP_CPU) peripheral interrupt
Set multiple PRO_Xn_MAP_REG (APP_Xn_MAP_REG) to the same Num_P. Any of these peripheral
interrupts will trigger CPU Interrupt_P.
2.3.4 CPU NMI Interrupt Mask
The Interrupt Matrix temporarily masks all peripheral interrupt sources allocated to PRO_CPU’s ( or APP_CPU’s )
NMI interrupt if it receives the signal PRO_CPU NMI Interrupt Mask ( or APP_CPU NMI Interrupt Mask ) from the
peripheral PID Controller respectively.
2.3.5 Query Current Interrupt Status of Peripheral Interrupt Source
The current interrupt status of a peripheral interrupt source can be read via the bit value in
PRO_INTR_STATUS_REG_n (APP_INTR_STATUS_REG_n) as shown in the mapping in Table 6.
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3 RESET AND CLOCK
3. Reset and Clock
3.1 System Reset
3.1.1 Introduction
The ESP32 has three reset levels: CPU reset, Core reset, and System reset. None of these reset levels clear the
RAM. Figure 4 shows the subsystems included in each reset level.
Figure 4: System Reset
• CPU reset: Only resets the registers of one or both the CPU cores.
• Core reset: Resets all the digital registers, including CPU cores, external GPIO and digital GPIO. The RTC is
not reset.
• System reset: Resets all the registers on the chip, including those of the RTC.
3.1.2 Reset Source
While most of the time the APP_CPU and PRO_CPU will be reset simultaneously, some reset sources are able to
reset only one of the two cores. The reset reason for each core can be looked up individually: the PRO_CPU
reset reason will be stored in RTC_CNTL_RESET_CAUSE_PROCPU, the reset reason for the APP_CPU in
APP_CNTL_RESET_CAUSE_PROCPU. Table 8 shows the possible reset reason values that can be read from
these registers.
Table 8: PRO_CPU and APP_CPU reset reason values
PRO APP Source Reset Type Note
0x01 0x01 Chip Power On Reset System Reset -
0x10 0x10 RWDT System Reset System Reset Refer to WDT Chapter.
0x0F 0x0F Brown Out Reset System Reset Refer to Power Management Chapter.
0x03 0x03 Software System Reset Core Reset Configure RTC_CNTL_SW_SYS_RST register.
0x05 0x05 Deep Sleep Rest Core Reset Refer to Power Management Chapter.
0x07 0x07 MWDT0 Global Reset Core Reset Refer to WDT Chapter.
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3.2 System Clock 3 RESET AND CLOCK
PRO APP APP Source Reset Type Note
0x08 0x08 MWDT1 Global Reset Core Reset Refer to WDT Chapter.
0x09 0x09 RWDT Core Reset Core Reset Refer to WDT Chapter.
0x0B - MWDT0 CPU Reset CPU Reset Refer to WDT Chapter.
0x0C - Software CPU Reset CPU Reset Configure RTC_CNTL_SW_APPCPU_RST register.
- 0x0B MWDT1 CPU Reset CPU Reset Refer to WDT Chapter.
- 0x0C Software CPU Reset CPU Reset Configure RTC_CNTL_SW_APPCPU_RST register.
0x0D 0x0D RWDT CPU Reset CPU Reset Refer to WDT Chapter.
Indicates that the PRO CPU has indepen-
- 0xE PRO CPU Reset CPU Reset
dently reset the APP CPU by configuring the
DPORT_APPCPU_RESETTING register.
3.2 System Clock
3.2.1 Introduction
The ESP32 integrates multiple clock sources for the CPU cores, the peripherals and the RTC. These clocks can
be configured to meet different requirements. Figure 5 shows the system clock structure.
Figure 5: System Clock
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3.2 System Clock 3 RESET AND CLOCK
3.2.2 Clock Source
The ESP32 can use an external crystal oscillator, an internal PLL or an oscillating circuit as a clock source.
Specifically, the clock sources available are:
• High Speed Clocks
– PLL_CLK is an internal PLL clock with a frequency of 320 MHz.
– XTL_CLK is a clock signal generated using an external crystal with a frequency range of 2 ~ 40 MHz.
• Low Power Clocks
– XTL32K_CLK is a clock generated using an external crystal with a frequency of 32 KHz.
– RTC8M_CLK is an internal clock with a default frequency of 8 MHz. This frequency is adjustable.
– RTC8M_D256_CLK is divided from RTC8M_CLK 256. Its frequency is (RTC8M_CLK / 256). With the
default RTC8M_CLK frequency of 8 MHz, this clock runs at 31.250 KHz.
– RTC_CLK is an internal low power clock with a default frequency of 150 KHz. This frequency is
adjustable.
• Audio Clock
– APLL_CLK is an internal Audio PLL clock with a frequency range of 16 ~ 128 MHz.
3.2.3 CPU Clock
As Figure 5 shows, CPU_CLK is the master clock for both CPU cores. CPU_CLK clock can be as high as 160
MHz when the CPU is in high performance mode. Alternatively, the CPU can run at lower frequencies to reduce
power consumption.
The CPU_CLK clock source is determined by the RTC_CNTL_SOC_CLK_SEL register. PLL_CLK, APLL_CLK,
RTC8M_CLK and XTL_CLK can be set as the CPU_CLK source; see Table 9 and 10.
Table 9: CPU_CLK Source
RTC_CNTL_SOC_CLK_SEL Value Clock Source
0 XTL_CLK
1 PLL_CLK
2 RTC8M_CLK
3 APLL_CLK
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3.2 System Clock 3 RESET AND CLOCK
Table 10: CPU_CLK Derivation
Clock Source SEL* CPU Clock
0 / XTL_CLK -
1 / PLL_CLK 0
1 / PLL_CLK 1
2 / RTC8M_CLK -
3 / APLL_CLK 0 CPU_CLK = APLL_CLK / 4
3 / APLL_CLK 1 CPU_CLK = APLL_CLK / 2
*SEL: DPORT_CPUPERIOD _SEL value
CPU_CLK = XTL_CLK / (APB_CTRL_PRE_DIV_CNT+1)
APB_CTRL_PRE_DIV_CNT range is 0 ~ 1023. Default is 0.
CPU_CLK = PLL_CLK / 4
CPU_CLK frequency is 80 MHz
CPU_CLK = PLL_CLK / 2
CPU_CLK frequency is 160 MHz
CPU_CLK = RTC8M_CLK / (APB_CTRL_PRE_DIV_CNT+1)
APB_CTRL_PRE_DIV_CNT range is 0 ~ 1023. Default is 0.
3.2.4 Peripheral Clock
Peripheral clocks include APB_CLK, REF_TICK, LEDC_SCLK, APLL_CLK and PLL_D2_CLK.
Table 11 shows which clocks can be used by which peripherals.
Table 11: Peripheral Clock Usage
Peripherals APB_CLK REF_TICK LEDC_SCLK APLL_CLK PLL_D2_CLK
EMAC Y N N Y N
TIMG Y N N N N
I2S Y N N Y Y
UART Y Y N N N
RMT Y Y N N N
LED PWM Y Y Y N N
PWM Y N N N N
I2C Y N N N N
SPI Y N N N N
PCNT Y N N N N
Efuse Controller Y N N N N
SDIO Slave Y N N N N
SDMMC Y N N N N
3.2.4.1 APB_CLK Source
The APB_CLK is derived from CPU_CLK as detailed in Table 12. The division factor depends on the CPU_CLK
source.
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3.2 System Clock 3 RESET AND CLOCK
Table 12: APB_CLK Derivation
CPU_CLK Source APB_CLK
PLL_CLK PLL_CLK / 4
APLL_CLK CPU_CLK / 2
XTAL_CLK CPU_CLK
RTC8M_CLK CPU_CLK
3.2.4.2 REF_TICK Source
REF_TICK is derived from APB_CLK via a divider. The divider value used depends on the APB_CLK source,
which in turn depends on the CPU_CLK source.
By configuring correct divider values for each APB_CLK source, the user can ensure that the REF_TICK
frequency does not change when CPU_CLK changes source causing the APB_CLK frequency to change.
Clock divider registers are shown in Table 13.
Table 13: REF_TICK Derivation
CPU_CLK & APB_CLK Source Clock Divider Register
PLL_CLK APB_CTRL_PLL_TICK_NUM
XTAL_CLK APB_CTRL_XTAL_TICK_NUM
APLL_CLK APB_CTRL_APLL_TICK_NUM
RTC8M_CLK APB_CTRL_CK8M_TICK_NUM
3.2.4.3 LEDC_SCLK Source
The LEDC_SCLK clock source is selected by the LEDC_APB_CLK_SEL register, as shown in Table 14.
Table 14: LEDC_SCLK Derivation
LEDC_APB_CLK_SEL Value LEDC_SCLK Source
1 RTC8M_CLK
0 APB_CLK
3.2.4.4 APLL_SCLK Source
The APLL_CLK is sourced from PLL_CLK, with its output frequency configured using the APLL configuration
registers.
3.2.4.5 PLL_D2_CLK Source
PLL_D2_CLK is half the PLL_CLK frequency.
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3.2 System Clock 3 RESET AND CLOCK
3.2.4.6 Clock Source Considerations
Most peripherals will operate using the APB_CLK frequency as a reference. When this frequency changes, the
peripherals will need to update their clock configuration to operate at the same frequency after the change.
Peripherals accessing REF_TICK can continue operating normally when switching clock sources, without
changing clock source. Please refer to Table 11 for details.
The LED PWM module can use RTC8M_CLK as a clock source, meaning that it can be used when APB_CLK is
disabled. In other words, when the system is in low power consumption mode (refer to power manager module),
normal peripherals will be halted (APB_CLK is turned off), but the LED PWM can work normally via
RTC8M_CLK.
3.2.5 Wi-Fi BT Clock
Wi-Fi and BT can only operate if APB_CLK has PLL_CLK as its clock source. Suspending PLL_CLK requires
Wi-Fi and BT to both have entered low power consumption mode first.
For LOW_POWER_CLK, one of RTC_CLK, SLOW_CLK, RTC8M_CLK or XTL_CLK can be selected as the low
power consumption mode clock source for Wi-Fi and BT.
3.2.6 RTC Clock
The clock sources of SLOW_CLK and FAST_CLK are low frequency clocks. The RTC module can operate when
most other clocks are stopped.
SLOW_CLK is used to clock the Power Management module. It can be sourced from RTC_CLK, XTL32K_CLK
or RTC8M_D256_CLK
FAST_CLK is used to clock the On-chip Sensor module. It can be sourced from a divided XTL_CLK or from
RTC8M_CLK.
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4 IO_MUX AND GPIO MATRIX
4. IO_MUX and GPIO Matrix
4.1 Introduction
The ESP32 chip features 40 physical GPIO pads. Some GPIO pads cannot be used or do not have the
corresponding pin on the chip package. Each pad can be used as a general purpose I/O or can be connected to
an internal peripheral signal. The IO_MUX, RTC IO_MUX and the GPIO matrix are responsible for routing signals
from the peripherals to GPIO pads. Together these systems provide highly configurable I/O.
This chapter describes the signal selection and connection between the digital pads (FUNC_SEL, IE, OE, WPU,
WDU, etc), 256 peripheral input/output signals (control signals: SIG_IN_SEL, SIG_OUT_SEL, IE, OE, etc), fast
peripheral input/output signals (control signals: SIG_IN_SEL, SIG_OUT_SEL, IE, OE, etc), and RTC
IO_MUX.
Figure 6: IO_MUX, RTC IO_MUX and GPIO Matrix Overview
1. The IO_MUX contains one register per GPIO pad. Each pad can be configured for ”GPIO” function
(connected to the GPIO Matrix) or configured for a direct function (bypassing the GPIO Matrix. Some high
speed digital functions (Ethernet, SDIO, SPI, JTAG, UART) can bypass the GPIO Matrix for better high
frequency digital performance. In this case, the IO_MUX is used to connect these pads directly to the
peripheral.)
Refer to Section 4.10 for a list of IO_MUX functions for each I/O pad.
2. The GPIO Matrix is a full switching matrix between the peripheral input/output signals and the pads.
• For input to the chip: Each of the 256 internal peripheral inputs can select any GPIO pad as the input
source.
• For output from the chip: The output signal of each of the 40 GPIO pads can be from one of the 256
peripheral output signals.
Refer to Section 4.9 for a list of GPIO Matrix peripheral signals.
3. RTC IO_MUX is used to connect GPIO pads to their low power and analog functions. Only a subset of
GPIO pads have these optional ”RTC” functions.
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4.2 Peripheral Input via GPIO Matrix 4 IO_MUX AND GPIO MATRIX
GPIO_FUNCy_IN_SEL
GPIO0_in
GPIO1_in
GPIO2_in
GPIO3_in
GPIO39_in
0 (FUNC)
1 (FUNC)
2 (GPIO)
3
39
Peripheral Signal Y
I/O Pad X
In GPIO matrix
In IO MUX
GPIO X in
GPIOx_MCU_SEL
2
1
3
X
GPIOX_in
0
Constant 0 input
Constant 1 input
(0x30) 48
(0x38) 56
0
1 (GPIO)
GPIO_SIGxx_IN_SEL
GPIOx_FUN_IE = 1
Refer to Section 4.11 for a list of RTC IO_MUX functions.
4.2 Peripheral Input via GPIO Matrix
4.2.1 Summary
To receive a peripheral input signal via the GPIO Matrix, the GPIO Matrix is configured to source the peripheral
signal’s input index (0-255) from one of the 40 GPIOs (0-39).
The input signal is read from the GPIO pad through the IO_MUX. The IO_MUX must be configured to set the
chosen pad to ”GPIO” function. This causes the GPIO pad input signal to be routed into the GPIO Matrix which
in turn routes it to the selected peripheral input.
4.2.2 Functional Description
Figure 7 shows the logic for input selection via GPIO Matrix.
To read GPIO pad X into peripheral signal Y, follow these steps:
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Figure 7: Peripheral Input via IO_MUX, GPIO Matrix
1. Configure the GPIO_FUNCy_IN_SEL_CFG register for peripheral signal Y in the GPIO Matrix:
• Set the GPIO_FUNCx_IN_SEL field to the number of the GPIO pad X to read from.
2. Configure the GPIO_FUNCx_OUT_SEL_CFG and GPIO_ENABLE_DATA[x] for GPIO pad X in the GPIO
Matrix:
• For input ony signals, the pad output can be disabled by setting the GPIO_FUNCx_OEN_SEL bits to
one and GPIO_ENABLE_DATA[x] to zero. Otherwise, there is no need to disable output.
3. Configure the IO_MUX register for GPIO pad X:
• Set the function field to GPIO.
• Enable the input by setting the xx_FUN_IE bit.
• Set xx_FUN_WPU and xx_FUN_WPD fields as desired to enable internal pull-up/pull-down resistors.
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