Espressif Systems ESP32 Pin List

ESP32 Pin List

Version 2.0!

Copyright © 2016!

Date

Version

Release notes

2016.06

V1.0

First release.

2016.07

V2.0

Updated IO_MUX.!

Added Notes, Ethernet_MAC, GPIO_Matrix, and Strapping.

Release Notes

A Quick Guide to This List

Note 1

In the “IO_MUX” page, the red-filled areas mark the differences from ESP31B. The blue-filled areas mark the new features as compared to the ESP31B.

Note 2

The following pins are input-only. These pins do not feature an output driver or internal pull-up/pull-down circuitry: SENSOR_VP (GPIO36),
SENSOR_CAPP (GPIO37), SENSOR_CAPN (GPIO38), SENSOR_VN (GPIO39), VDET_1 (GPIO36), VDET_2 (GPIO36).

Note 3

The pins are split into 4 power-domains: VANA (analog power supply), VRTC (RTC power supply), VIO (power supply of digital IOs and CPU cores),
VSDIO (power supply of SDIO IOs)."

VSDIO is the output of the internal SDIO-LDO. The voltage of SDIO-LDO is configurable to be 1.8V or to be the same as VRTC. The strapping pin and
efuse bits decide the default voltage of the SDIO-LDO. Software can change the voltage of the SDIO-LDO by configuring register bits.##

Note 4

The functional pins in the VRTC domain are with the analog functions, including 32kHz crystal oscillator, ADC pre-amplifier, ADC, DAC, and capacitive
touch sensor. Please refer to the columns "Analog Function 1~3" in the page "IO_MUX".

Note 5

These VRTC pins support the RTC_GPIO function, and can work during deep-sleep. For example, a RTC-GPIO may be used to wake up the chip from
deep-sleep.

Note 6

The GPIO pins support up to 6 digital functions as shown in the columns "Function 1~6" of the page "IO_MUX". The function select registers shall be set
as "N-1", where N is the function number. "

Below are some definitions:"
SD_* is for the signals of the SDIO slave"
HS1_* is for the signals of the Port 1 of SDIO host"
HS2_* is for the signals of the Port 2 of SDIO host"
MT* is for the signals of the JTAG"
U0* is for the signals of UART0 module."
U1* is for the signals of UART1 module."
U2* is for the signals of UART2 module."
SPI* is for the signals of SPI01 module."
HSPI* is for the signals of SPI2 module."
VSPI* is for the signals of SPI3 module.#"

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Note 7

Each digital "function" column is accompanied by a column of "Type". Please refer to the following to understand the significance of "type" with respect
to each "function" it is associated with.!

For any function "Function-N", type signifies:!
"I": input only. If a function other than "Function-N" is assigned, the input signal of "Function-N" is still from this pin.!
"I1": input only. If a function other than "Function-N" is assigned, the input signal for "Function-N" is always "1". !
"I0": input only. If a function other than "Function-N" is assigned, the input signal for "Function-N" is always "0".!
"O": output only.!
"T": high-impendence.!
"I/O/T": combinations of input, output, and high-impendence according to the function signal.!
"I1/O/T": combinations of input, output, and high-impendence according to the function signal. If a function is not selected, the input signal of the
function is "1". !

For example, pin 30 can act as HS1_CMD or SD_CMD, where HS1_CMD is with the type "I1/O/T".!
If pin 30 is selected as "HS1_CMD", the input and output of this pin are controlled by the SDIO Host. If pin 30 is not selected as "HS1_CMD", the input
signal to SDIO Host is always "1".

Note 8

Each digital output pin is associated with its configurable drive-strength. The column "Drive Strength" in the page "IO_MUX" lists the default values.

Note 9

The column "At reset" in the page "IO_MUX" lists the status of each pin during reset, including input enable (ie=1), internal pull-up (wpu) and internal
pull-down (wpd). During reset, all pins are output disabled.

Note 10

The column "After Reset" in the page "IO_MUX" lists the status of each pin immediately after reset, including input enable (ie=1), internal pull-up (wpu)
and internal pull-down (wpd). After reset, each pin is set to its "Function 1". The output enable are controlled by its digital Function 1.

Note 11

The page “Ethernet_MAC” is for the signal mapping inside Ethernet MAC. The Ethernet MAC supports MII and RMII interfaces, and supports both
internal PLL clock and the external clock source. For MII interface, the Ethernet MAC is with/without the TX_ERR signal. MDC, MDIO, CRS and COL are
slow signals, and can be mapped to any GPIO pins through GPIO-Matrix.

Note 12

The page "GPIO_Matrix" is for the GPIO-Matrix. The signals of the on-chip functional modules can be mapped to any GPIO pins.!
Some signals can be mapped to a pin by both IO-MUX and GPIO-Matrix, as shown in the column of "The same input signal from IO_MUX Core" in the
page "GPIO_Matrix".

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