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ESP32C3
Technical Reference Manual
www.espressif.com
Version 1.0
Espressif Systems
Copyright © 2023
Page 2
About This Document
The ESP32C3 is targeted at developers working on low level software projects that use the ESP32-C3 SoC. It
describes the hardware modules listed below for the ESP32-C3 SoC and other products in ESP32-C3 series.
The modules detailed in this document provide an overview, list of features, hardware architecture details, any
necessary programming procedures, as well as register descriptions.
Navigation in This Document
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Page 3
Release Status at a Glance
No. ESP32C3 Chapters Progress No. ESP32C3 Chapters Progress
1 ESP-RISC-V CPU Published 18 SHA Accelerator (SHA) Published
2 GDMA Controller (GDMA) Published 19 AES Accelerator (AES) Published
3 System and Memory Published 20 RSA Accelerator (RSA) Published
4 eFuse Controller (EFUSE) Published 21 HMAC Accelerator (HMAC) Published
IO MUX and GPIO Matrix (GPIO, IO
5
MUX)
6 Reset and Clock Published 23
7 Chip Boot Control Published 24 Clock Glitch Detection Published
8 Interrupt Matrix (INTERRUPT) Published 25 Random Number Generator (RNG) Published
9 Low-power Management Published 26 UART Controller (UART) Published
10 System Timer (SYSTIMER) Published 27 SPI Controller (SPI) Published
11 Timer Group (TIMG) Published 28 I2C Controller (I2C) Published
12 Watchdog Timers (WDT) Published 29 I2S Controller (I2S) Published
13 XTAL32K Watchdog Timers (XTWDT) Published 30
14 Permission Control (PMS) Published 31
15 World Controller (WCL) Published 32 LED PWM Controller (LEDC) Published
16 System Registers (SYSREG) Published 33 Remote Control Peripheral (RMT) Published
17 Debug Assistant (ASSIST_DEBUG) Published 34
Published 22 Digital Signature (DS) Published
External Memory Encryption and
Decryption (XTS_AES)
USB Serial/JTAG Controller
(USB_SERIAL_JTAG)
Two-wire Automotive Interface
(TWAI)
On-Chip Sensor and Analog Signal
Processing
Published
Published
Published
Published
Note:
Check the link or the QR code to make sure that you use the latest version of this document:
https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_
en.pdf
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Contents
1 ESPRISCV CPU 27
1.1 Overview 27
1.2 Features 27
1.3 Address Map 28
1.4 Configuration and Status Registers (CSRs) 28
1.4.1 Register Summary 28
1.4.2 Register Description 29
1.5 Interrupt Controller 38
1.5.1 Features 38
1.5.2 Functional Description 38
1.5.3 Suggested Operation 40
1.5.3.1 Latency Aspects 40
1.5.3.2 Configuration Procedure 40
1.5.4 Register Summary 41
1.5.5 Register Description 42
1.6 Debug 43
1.6.1 Overview 43
1.6.2 Features 44
1.6.3 Functional Description 44
1.6.4 Register Summary 44
1.6.5 Register Description 44
1.7 Hardware Trigger 47
1.7.1 Features 47
1.7.2 Functional Description 47
1.7.3 Trigger Execution Flow 48
1.7.4 Register Summary 48
1.7.5 Register Description 49
1.8 Memory Protection 53
1.8.1 Overview 53
1.8.2 Features 53
1.8.3 Functional Description 53
1.8.4 Register Summary 54
1.8.5 Register Description 54
2 GDMA Controller (GDMA) 55
2.1 Overview 55
2.2 Features 55
2.3 Architecture 56
2.4 Functional Description 56
2.4.1 Linked List 57
2.4.2 Peripheral-to-Memory and Memory-to-Peripheral Data Transfer 58
2.4.3 Memory-to-Memory Data Transfer 58
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2.4.4 Enabling GDMA 58
2.4.5 Linked List Reading Process 59
2.4.6 EOF 60
2.4.7 Accessing Internal RAM 60
2.4.8 Arbitration 61
2.5 GDMA Interrupts 61
2.6 Programming Procedures 61
2.6.1 Programming Procedure for GDMA Clock and Reset 61
2.6.2 Programming Procedures for GDMA’s Transmit Channel 62
2.6.3 Programming Procedures for GDMA’s Receive Channel 62
2.6.4 Programming Procedures for Memory-to-Memory Transfer 62
2.7 Register Summary 64
2.8 Registers 68
3 System and Memory 85
3.1 Overview 85
3.2 Features 85
3.3 Functional Description 86
3.3.1 Address Mapping 86
3.3.2 Internal Memory 87
3.3.3 External Memory 88
3.3.3.1 External Memory Address Mapping 89
3.3.3.2 Cache 89
3.3.3.3 Cache Operations 90
3.3.4 GDMA Address Space 90
3.3.5 Modules/Peripherals 91
3.3.5.1 Module/Peripheral Address Mapping 92
4 eFuse Controller (EFUSE) 94
4.1 Overview 94
4.2 Features 94
4.3 Functional Description 94
4.3.1 Structure 94
4.3.1.1 EFUSE_WR_DIS 100
4.3.1.2 EFUSE_RD_DIS 100
4.3.1.3 Data Storage 100
4.3.2 Programming of Parameters 101
4.3.3 User Read of Parameters 103
4.3.4 eFuse VDDQ Timing 105
4.3.5 The Use of Parameters by Hardware Modules 105
4.3.6 Interrupts 105
4.4 Register Summary 106
4.5 Registers 110
5 IO MUX and GPIO Matrix (GPIO, IO MUX) 152
5.1 Overview 152
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5.2 Features 152
5.3 Architectural Overview 152
5.4 Peripheral Input via GPIO Matrix 154
5.4.1 Overview 154
5.4.2 Signal Synchronization 155
5.4.3 Functional Description 155
5.4.4 Simple GPIO Input 156
5.5 Peripheral Output via GPIO Matrix 156
5.5.1 Overview 156
5.5.2 Functional Description 157
5.5.3 Simple GPIO Output 158
5.5.4 Sigma Delta Modulated Output (SDM) 158
5.5.4.1 Functional Description 158
5.5.4.2 SDM Configuration 159
5.6 Direct Input and Output via IO MUX 159
5.6.1 Overview 159
5.6.2 Functional Description 159
5.7 Analog Functions of GPIO Pins 159
5.8 Pin Functions in Light-sleep 160
5.9 Pin Hold Feature 160
5.10 Power Supplies and Management of GPIO Pins 160
5.10.1 Power Supplies of GPIO Pins 160
5.10.2 Power Supply Management 161
5.11 Peripheral Signal List 161
5.12 IO MUX Functions List 167
5.13 Analog Functions List 168
5.14 Register Summary 168
5.14.1 GPIO Matrix Register Summary 168
5.14.2 IO MUX Register Summary 170
5.14.3 SDM Register Summary 171
5.15 Registers 171
5.15.1 GPIO Matrix Registers 172
5.15.2 IO MUX Registers 179
5.15.3 SDM Output Registers 181
6 Reset and Clock 183
6.1 Reset 183
6.1.1 Overview 183
6.1.2 Architectural Overview 183
6.1.3 Features 183
6.1.4 Functional Description 184
6.2 Clock 184
6.2.1 Overview 185
6.2.2 Architectural Overview 185
6.2.3 Features 185
6.2.4 Functional Description 186
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6.2.4.1 CPU Clock 186
6.2.4.2 Peripheral Clock 186
6.2.4.3 Wi-Fi and Bluetooth LE Clock 188
6.2.4.4 RTC Clock 188
7 Chip Boot Control 189
7.1 Overview 189
7.2 Boot Mode Control 189
7.3 ROM Code Printing Control 190
8 Interrupt Matrix (INTERRUPT) 192
8.1 Overview 192
8.2 Features 192
8.3 Functional Description 192
8.3.1 Peripheral Interrupt Sources 192
8.3.2 CPU Interrupts 197
8.3.3 Allocate Peripheral Interrupt Source to CPU Interrupt 197
8.3.3.1 Allocate one peripheral interrupt source (Source_X) to CPU 197
8.3.3.2 Allocate multiple peripheral interrupt sources (Source_Xn) to CPU 197
8.3.3.3 Disable CPU peripheral interrupt source (Source_X) 197
8.3.4 Query Current Interrupt Status of Peripheral Interrupt Source 197
8.4 Register Summary 198
8.5 Registers 202
9 Lowpower Management 208
9.1 Introduction 208
9.2 Features 208
9.3 Functional Description 208
9.3.1 Power Management Unit (PMU) 210
9.3.2 Low-Power Clocks 211
9.3.3 Timers 212
9.3.4 Voltage Regulators 213
9.3.4.1 Digital System Voltage Regulator 213
9.3.4.2 Low-power Voltage Regulator 213
9.3.4.3 Brownout Detector 214
9.4 Power Modes Management 214
9.4.1 Power Domain 215
9.4.2 Pre-defined Power Modes 215
9.4.3 Wakeup Source 216
9.4.4 Reject Sleep 216
9.5 Retention DMA 217
9.6 RTC Boot 217
9.7 Register Summary 220
9.8 Registers 222
10 System Timer (SYSTIMER) 259
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10.1 Overview 259
10.2 Features 259
10.3 Clock Source Selection 260
10.4 Functional Description 260
10.4.1 Counter 260
10.4.2 Comparator and Alarm 261
10.4.3 Synchronization Operation 262
10.4.4 Interrupt 262
10.5 Programming Procedure 262
10.5.1 Read Current Count Value 263
10.5.2 Configure One-Time Alarm in Target Mode 263
10.5.3 Configure Periodic Alarms in Period Mode 263
10.5.4 Update After Deep-sleep and Light-sleep 263
10.6 Register Summary 264
10.7 Registers 266
11 Timer Group (TIMG) 277
11.1 Overview 277
11.2 Functional Description 278
11.2.1 16-bit Prescaler and Clock Selection 278
11.2.2 54-bit Time-base Counter 278
11.2.3 Alarm Generation 279
11.2.4 Timer Reload 280
11.2.5 RTC_SLOW_CLK Frequency Calculation 280
11.2.6 Interrupts 280
11.3 Configuration and Usage 281
11.3.1 Timer as a Simple Clock 281
11.3.2 Timer as One-shot Alarm 281
11.3.3 Timer as Periodic Alarm 282
11.3.4 RTC_SLOW_CLK Frequency Calculation 282
11.4 Register Summary 283
11.5 Registers 284
12 Watchdog Timers (WDT) 294
12.1 Overview 294
12.2 Digital Watchdog Timers 295
12.2.1 Features 295
12.2.2 Functional Description 295
12.2.2.1 Clock Source and 32-Bit Counter 296
12.2.2.2 Stages and Timeout Actions 296
12.2.2.3 Write Protection 297
12.2.2.4 Flash Boot Protection 297
12.3 Super Watchdog 297
12.3.1 Features 298
12.3.2 Super Watchdog Controller 298
12.3.2.1 Structure 298
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12.3.2.2 Workflow 298
12.4 Interrupts 299
12.5 Registers 299
13 XTAL32K Watchdog Timers (XTWDT) 300
13.1 Overview 300
13.2 Features 300
13.2.1 Interrupt and Wake-Up 300
13.2.2 BACKUP32K_CLK 300
13.3 Functional Description 300
13.3.1 Workflow 300
13.3.2 BACKUP32K_CLK Working Principle 301
13.3.3 Configuring the Divisor Component of BACKUP32K_CLK 301
14 Permission Control (PMS) 302
14.1 Overview 302
14.2 Features 303
14.3 Privileged Environment and Unprivileged Environment 303
14.4 Internal Memory 304
14.4.1 ROM 304
14.4.2 SRAM 305
14.4.2.1 Internal SRAM0 Access Configuration 305
14.4.2.2 Internal SRAM1 Access Configuration 306
14.4.3 RTC FAST Memory 309
14.5 Peripherals 310
14.5.1 Access Configuration 310
14.5.2 Split Peripheral Regions into Split Regions 311
14.6 External Memory 312
14.6.1 SPI anc Cache’s Access to External Flash 313
14.6.1.1 Address 313
14.6.1.2 Access Configuration 313
14.6.2 CPU’s Access to Cache 313
14.6.2.1 Split Regions 314
14.6.3 Access Configuration 314
14.7 Unauthorized Access and Interrupts 315
14.7.1 Interrupt upon Unauthorized IBUS Access 315
14.7.2 Interrupt upon Unauthorized DBUS Access 316
14.7.3 Interrupt upon Unauthorized Access to External Memory 317
14.7.4 Interrupt upon Unauthorized Access to Internal Memory via GDMA 317
14.7.5 Interrupt upon Unauthorized peripheral bus (PIF) Access 317
14.7.6 Interrupt upon Unauthorized PIF Access Alignment 318
14.8 Register Locks 319
14.9 Register Summary 321
14.10 Registers 324
15 World Controller (WCL) 399
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15.1 Introduction 399
15.2 Features 399
15.3 Functional Description 399
15.4 CPU’s World Switch 401
15.4.1 From Secure World to Non-secure World 401
15.4.2 From Non-secure World to Secure World 402
15.5 World Switch Log 403
15.5.1 Structure of World Switch Log Register 403
15.5.2 How World Switch Log Registers are Updated 403
15.5.3 How to Read World Switch Log Registers 406
15.5.4 Nested Interrupts 406
15.5.4.1 Programming Procedure 406
15.6 Register Summary 408
15.7 Registers 409
16 System Registers (SYSREG) 414
16.1 Overview 414
16.2 Features 414
16.3 Function Description 414
16.3.1 System and Memory Registers 414
16.3.1.1 Internal Memory 414
16.3.1.2 External Memory 415
16.3.1.3 RSA Memory 415
16.3.2 Clock Registers 416
16.3.3 Interrupt Signal Registers 416
16.3.4 Low-power Management Registers 416
16.3.5 Peripheral Clock Gating and Reset Registers 416
16.4 Register Summary 418
16.5 Registers 419
17 Debug Assistant (ASSIST_DEBUG) 432
17.1 Overview 432
17.2 Features 432
17.3 Functional Description 432
17.3.1 Region Read/Write Monitoring 432
17.3.2 SP Monitoring 432
17.3.3 PC Logging 432
17.3.4 CPU/DMA Bus Access Logging 432
17.4 Recommended Operation 433
17.4.1 Region Monitoring and SP Monitoring Configuration Process 433
17.4.2 PC Logging Configuration Process 434
17.4.3 CPU/DMA Bus Access Logging Configuration Process 434
17.5 Register Summary 438
17.6 Registers 440
18 SHA Accelerator (SHA) 457
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18.1 Introduction 457
18.2 Features 457
18.3 Working Modes 457
18.4 Function Description 458
18.4.1 Preprocessing 458
18.4.1.1 Padding the Message 458
18.4.1.2 Parsing the Message 458
18.4.1.3 Setting the Initial Hash Value 459
18.4.2 Hash Operation 459
18.4.2.1 Typical SHA Mode Process 459
18.4.2.2 DMA-SHA Mode Process 460
18.4.3 Message Digest 461
18.4.4 Interrupt 462
18.5 Register Summary 462
18.6 Registers 463
19 AES Accelerator (AES) 467
19.1 Introduction 467
19.2 Features 467
19.3 AES Working Modes 467
19.4 Typical AES Working Mode 469
19.4.1 Key, Plaintext, and Ciphertext 469
19.4.2 Endianness 469
19.4.3 Operation Process 471
19.5 DMA-AES Working Mode 471
19.5.1 Key, Plaintext, and Ciphertext 472
19.5.2 Endianness 472
19.5.3 Standard Incrementing Function 473
19.5.4 Block Number 473
19.5.5 Initialization Vector 473
19.5.6 Block Operation Process 474
19.6 Memory Summary 474
19.7 Register Summary 475
19.8 Registers 476
20 RSA Accelerator (RSA) 480
20.1 Introduction 480
20.2 Features 480
20.3 Functional Description 480
20.3.1 Large Number Modular Exponentiation 480
20.3.2 Large Number Modular Multiplication 482
20.3.3 Large Number Multiplication 482
20.3.4 Options for Acceleration 483
20.4 Memory Summary 484
20.5 Register Summary 485
20.6 Registers 486
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21 HMAC Accelerator (HMAC) 490
21.1 Main Features 490
21.2 Functional Description 490
21.2.1 Upstream Mode 490
21.2.2 Downstream JTAG Enable Mode 491
21.2.3 Downstream Digital Signature Mode 491
21.2.4 HMAC eFuse Configuration 491
21.2.5 HMAC Process (Detailed) 493
21.3 HMAC Algorithm Details 494
21.3.1 Padding Bits 494
21.3.2 HMAC Algorithm Structure 495
21.4 Register Summary 497
21.5 Registers 499
22 Digital Signature (DS) 505
22.1 Overview 505
22.2 Features 505
22.3 Functional Description 505
22.3.1 Overview 505
22.3.2 Private Key Operands 506
22.3.3 Software Prerequisites 506
22.3.4 DS Operation at the Hardware Level 507
22.3.5 DS Operation at the Software Level 508
22.4 Memory Summary 510
22.5 Register Summary 511
22.6 Registers 512
23 External Memory Encryption and Decryption (XTS_AES)514
23.1 Overview 514
23.2 Features 514
23.3 Module Structure 514
23.4 Functional Description 515
23.4.1 XTS Algorithm 515
23.4.2 Key 515
23.4.3 Target Memory Space 516
23.4.4 Data Writing 516
23.4.5 Manual Encryption Block 517
23.4.6 Auto Decryption Block 517
23.5 Software Process 518
23.6 Register Summary 519
23.7 Registers 520
24 Clock Glitch Detection 523
24.1 Overview 523
24.2 Functional Description 523
24.2.1 Clock Glitch Detection 523
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24.2.2 Reset 523
25 Random Number Generator (RNG) 524
25.1 Introduction 524
25.2 Features 524
25.3 Functional Description 524
25.4 Programming Procedure 525
25.5 Register Summary 525
25.6 Register 525
26 UART Controller (UART) 526
26.1 Overview 526
26.2 Features 526
26.3 UART Structure 527
26.4 Functional Description 528
26.4.1 Clock and Reset 528
26.4.2 UART RAM 529
26.4.3 Baud Rate Generation and Detection 531
26.4.3.1 Baud Rate Generation 531
26.4.3.2 Baud Rate Detection 532
26.4.4 UART Data Frame 533
26.4.5 AT_CMD Character Structure 533
26.4.6 RS485 534
26.4.6.1 Driver Control 534
26.4.6.2 Turnaround Delay 534
26.4.6.3 Bus Snooping 535
26.4.7 IrDA 535
26.4.8 Wake-up 536
26.4.9 Flow Control 536
26.4.9.1 Hardware Flow Control 537
26.4.9.2 Software Flow Control 538
26.4.10 GDMA Mode 538
26.4.11 UART Interrupts 539
26.4.12 UHCI Interrupts 540
26.5 Programming Procedures 540
26.5.1 Register Type 540
26.5.1.1 Synchronous Registers 541
26.5.1.2 Static Registers 542
26.5.1.3 Immediate Registers 542
26.5.2 Detailed Steps 542
26.5.2.1 Initializing URATn 543
26.5.2.2 Configuring URATn Communication 544
26.5.2.3 Enabling UARTn 544
26.6 Register Summary 545
26.7 Registers 547
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27 SPI Controller (SPI) 584
27.1 Overview 584
27.2 Glossary 584
27.3 Features 585
27.4 Architectural Overview 586
27.5 Functional Description 586
27.5.1 Data Modes 586
27.5.2 FSPI Bus Signal Mapping 587
27.5.3 Bit Read/Write Order Control 589
27.5.4 Transfer Modes 589
27.5.5 CPU-Controlled Data Transfer 589
27.5.5.1 CPU-Controlled Master Mode 590
27.5.5.2 CPU-Controlled Slave Mode 591
27.5.6 DMA-Controlled Data Transfer 591
27.5.6.1 GDMA Configuration 592
27.5.6.2 GDMA TX/RX Buffer Length Control 593
27.5.7 Data Flow Control in GP-SPI2 Master and Slave Modes 593
27.5.7.1 GP-SPI2 Functional Blocks 593
27.5.7.2 Data Flow Control in Master Mode 594
27.5.7.3 Data Flow Control in Slave Mode 595
27.5.8 GP-SPI2 Works as a Master 596
27.5.8.1 State Machine 596
27.5.8.2 Register Configuration for State and Bit Mode Control 598
27.5.8.3 Full-Duplex Communication (1-bit Mode Only) 601
27.5.8.4 Half-Duplex Communication (1/2/4-bit Mode) 602
27.5.8.5 DMA-Controlled Configurable Segmented Transfer 604
27.5.9 GP-SPI2 Works as a Slave 608
27.5.9.1 Communication Formats 608
27.5.9.2 Supported CMD Values in Half-Duplex Communication 609
27.5.9.3 Slave Single Transfer and Slave Segmented Transfer 612
27.5.9.4 Configuration of Slave Single Transfer 612
27.5.9.5 Configuration of Slave Segmented Transfer in Half-Duplex 613
27.5.9.6 Configuration of Slave Segmented Transfer in Full-Duplex 613
27.6 CS Setup Time and Hold Time Control 613
27.7 GP-SPI2 Clock Control 615
27.7.1 Clock Phase and Polarity 615
27.7.2 Clock Control in Master Mode 617
27.7.3 Clock Control in Slave Mode 617
27.8 GP-SPI2 Timing Compensation 617
27.9 Interrupts 619
27.10 Register Summary 622
27.11 Registers 623
28 I2C Controller (I2C) 650
28.1 Overview 650
28.2 Features 650
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28.3 I2C Architecture 651
28.4 Functional Description 653
28.4.1 Clock Configuration 653
28.4.2 SCL and SDA Noise Filtering 653
28.4.3 SCL Clock Stretching 654
28.4.4 Generating SCL Pulses in Idle State 654
28.4.5 Synchronization 654
28.4.6 Open-Drain Output 655
28.4.7 Timing Parameter Configuration 656
28.4.8 Timeout Control 657
28.4.9 Command Configuration 658
28.4.10 TX/RX RAM Data Storage 659
28.4.11 Data Conversion 660
28.4.12 Addressing Mode 660
28.4.13 R/W Bit Check in 10-bit Addressing Mode 660
28.4.14 To Start the I2C Controller 661
28.5 Programming Example 661
28.5.1 I2C
master
Writes to I2C
with a 7-bit Address in One Command Sequence 661
slave
28.5.1.1 Introduction 661
28.5.1.2 Configuration Example 662
28.5.2 I2C
master
Writes to I2C
with a 10-bit Address in One Command Sequence 663
slave
28.5.2.1 Introduction 663
28.5.2.2 Configuration Example 663
28.5.3 I2C
master
Writes to I2C
with Two 7-bit Addresses in One Command Sequence 665
slave
28.5.3.1 Introduction 665
28.5.3.2 Configuration Example 665
28.5.4 I2C
master
Writes to I2C
with a 7-bit Address in Multiple Command Sequences 667
slave
28.5.4.1 Introduction 667
28.5.4.2 Configuration Example 668
28.5.5 I2C
master
Reads I2C
with a 7-bit Address in One Command Sequence 669
slave
28.5.5.1 Introduction 669
28.5.5.2 Configuration Example 670
28.5.6 I2C
master
Reads I2C
with a 10-bit Address in One Command Sequence 671
slave
28.5.6.1 Introduction 671
28.5.6.2 Configuration Example 671
28.5.7 I2C
master
Reads I2C
with Two 7-bit Addresses in One Command Sequence 673
slave
28.5.7.1 Introduction 673
28.5.7.2 Configuration Example 674
28.5.8 I2C
master
Reads I2C
with a 7-bit Address in Multiple Command Sequences 676
slave
28.5.8.1 Introduction 676
28.5.8.2 Configuration Example 677
28.6 Interrupts 678
28.7 Register Summary 680
28.8 Registers 682
29 I2S Controller (I2S) 702
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29.1 Overview 702
29.2 Terminology 702
29.3 Features 703
29.4 System Architecture 704
29.5 Supported Audio Standards 705
29.5.1 TDM Philips Standard 706
29.5.2 TDM MSB Alignment Standard 706
29.5.3 TDM PCM Standard 707
29.5.4 PDM Standard 707
29.6 I2S TX/RX Clock 708
29.7 I2S Reset 710
29.8 I2S Master/Slave Mode 710
29.8.1 Master/Slave TX Mode 710
29.8.2 Master/Slave RX Mode 711
29.9 Transmitting Data 711
29.9.1 Data Format Control 711
29.9.1.1 Bit Width Control of Channel Valid Data 711
29.9.1.2 Endian Control of Channel Valid Data 712
29.9.1.3 A-law/µ-law Compression and Decompression 712
29.9.1.4 Bit Width Control of Channel TX Data 713
29.9.1.5 Bit Order Control of Channel Data 713
29.9.2 Channel Mode Control 714
29.9.2.1 I2S Channel Control in TDM TX Mode 714
29.9.2.2 I2S Channel Control in PDM TX Mode 715
29.10 Receiving Data 717
29.10.1 Channel Mode Control 717
29.10.1.1 I2S Channel Control in TDM RX Mode 718
29.10.1.2 I2S Channel Control in PDM RX Mode 718
29.10.2 Data Format Control 718
29.10.2.1 Bit Order Control of Channel Data 718
29.10.2.2 Bit Width Control of Channel Storage (Valid) Data 718
29.10.2.3 Bit Width Control of Channel RX Data 719
29.10.2.4 Endian Control of Channel Storage Data 719
29.10.2.5 A-law/µ-law Compression and Decompression 719
29.11 Software Configuration Process 720
29.11.1 Configure I2S as TX Mode 720
29.11.2 Configure I2S as RX Mode 720
29.12 I2S Interrupts 721
29.13 Register Summary 721
29.14 Registers 723
30 USB Serial/JTAG Controller (USB_SERIAL_JTAG) 736
30.1 Overview 736
30.2 Features 736
30.3 Functional Description 737
30.3.1 CDC-ACM USB Interface Functional Description 738
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30.3.2 CDC-ACM Firmware Interface Functional Description 738
30.3.3 USB-to-JTAG Interface 739
30.3.4 JTAG Command Processor 739
30.3.5 USB-to-JTAG Interface: CMD_REP usage example 740
30.3.6 USB-to-JTAG Interface: Response Capture Unit 741
30.3.7 USB-to-JTAG Interface: Control Transfer Requests 741
30.4 Recommended Operation 742
30.5 Register Summary 744
30.6 Registers 745
31 Twowire Automotive Interface (TWAI) 759
31.1 Features 759
31.2 Functional Protocol 759
31.2.1 TWAI Properties 759
31.2.2 TWAI Messages 760
31.2.2.1 Data Frames and Remote Frames 761
31.2.2.2 Error and Overload Frames 763
31.2.2.3 Interframe Space 764
31.2.3 TWAI Errors 765
31.2.3.1 Error Types 765
31.2.3.2 Error States 765
31.2.3.3 Error Counters 766
31.2.4 TWAI Bit Timing 767
31.2.4.1 Nominal Bit 767
31.2.4.2 Hard Synchronization and Resynchronization 768
31.3 Architectural Overview 768
31.3.1 Registers Block 768
31.3.2 Bit Stream Processor 770
31.3.3 Error Management Logic 770
31.3.4 Bit Timing Logic 770
31.3.5 Acceptance Filter 770
31.3.6 Receive FIFO 770
31.4 Functional Description 770
31.4.1 Modes 770
31.4.1.1 Reset Mode 771
31.4.1.2 Operation Mode 771
31.4.2 Bit Timing 771
31.4.3 Interrupt Management 772
31.4.3.1 Receive Interrupt (RXI) 772
31.4.3.2 Transmit Interrupt (TXI) 773
31.4.3.3 Error Warning Interrupt (EWI) 773
31.4.3.4 Data Overrun Interrupt (DOI) 773
31.4.3.5 Error Passive Interrupt (TXI) 773
31.4.3.6 Arbitration Lost Interrupt (ALI) 774
31.4.3.7 Bus Error Interrupt (BEI) 774
31.4.3.8 Bus Status Interrupt (BSI) 774
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31.4.4 Transmit and Receive Buffers 774
31.4.4.1 Overview of Buffers 774
31.4.4.2 Frame Information 775
31.4.4.3 Frame Identifier 775
31.4.4.4 Frame Data 776
31.4.5 Receive FIFO and Data Overruns 777
31.4.6 Acceptance Filter 777
31.4.6.1 Single Filter Mode 778
31.4.6.2 Dual Filter Mode 778
31.4.7 Error Management 779
31.4.7.1 Error Warning Limit 780
31.4.7.2 Error Passive 780
31.4.7.3 Bus-Off and Bus-Off Recovery 780
31.4.8 Error Code Capture 781
31.4.9 Arbitration Lost Capture 782
31.5 Register Summary 784
31.6 Registers 785
32 LED PWM Controller (LEDC) 798
32.1 Overview 798
32.2 Features 798
32.3 Functional Description 798
32.3.1 Architecture 798
32.3.2 Timers 799
32.3.2.1 Clock Source 799
32.3.2.2 Clock Divider Configuration 800
32.3.2.3 14-bit Counter 801
32.3.3 PWM Generators 802
32.3.4 Duty Cycle Fading 803
32.3.5 Interrupts 804
32.4 Register Summary 805
32.5 Registers 807
33 Remote Control Peripheral (RMT) 814
33.1 Overview 814
33.2 Features 814
33.3 Functional Description 814
33.3.1 RMT Architecture 815
33.3.2 RMT RAM 815
33.3.3 Clock 816
33.3.4 Transmitter 817
33.3.4.1 Normal TX Mode 817
33.3.4.2 Wrap TX Mode 817
33.3.4.3 TX Modulation 817
33.3.4.4 Continuous TX Mode 818
33.3.4.5 Simultaneous TX Mode 818
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33.3.5 Receiver 818
33.3.5.1 Normal RX Mode 818
33.3.5.2 Wrap RX Mode 819
33.3.5.3 RX Filtering 819
33.3.5.4 RX Demodulation 820
33.3.6 Configuration Update 820
33.3.7 Interrupts 821
33.4 Register Summary 822
33.5 Registers 823
34 OnChip Sensor and Analog Signal Processing 838
34.1 Overview 838
34.2 SAR ADCs 838
34.2.1 Overview 838
34.2.2 Features 838
34.2.3 Functional Description 839
34.2.3.1 Input Signals 840
34.2.3.2 ADC Conversion and Attenuation 840
34.2.3.3 DIG ADC Controller 840
34.2.3.4 DIG ADC Clock 841
34.2.3.5 DMA Support 841
34.2.3.6 DIG ADC FSM 842
34.2.3.7 ADC Filters 844
34.2.3.8 Threshold Monitoring 845
34.2.3.9 SAR ADC2 Arbiter 845
34.3 Temperature Sensor 846
34.3.1 Overview 846
34.3.2 Features 846
34.3.3 Functional Description 846
34.4 Interrupts 847
34.5 Register Summary 847
34.6 Register 848
35 Related Documentation and Resources 861
Glossary 862
Abbreviations for Peripherals 862
Abbreviations Related to Registers 862
Access Types for Registers 863
Revision History 865
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List of Tables
1-1 CPU Address Map 28
1-3 ID wise map of Interrupt Trap-Vector Addresses 39
1-5 NAPOT encoding for maddress 48
2-1 Selecting Peripherals via Register Configuration 58
2-2 Descriptor Field Alignment Requirements 60
3-1 Internal Memory Address Mapping 87
3-2 External Memory Address Mapping 89
3-3 Module/Peripheral Address Mapping 92
4-1 Parameters in eFuse BLOCK0 95
4-2 Secure Key Purpose Values 98
4-3 Parameters in BLOCK1 to BLOCK10 99
4-4 Registers Information 103
4-5 Configuration of Default VDDQ Timing Parameters 105
5-1 Bits Used to Control IO MUX Functions in Light-sleep Mode 160
5-2 Peripheral Signals via GPIO Matrix 162
5-3 IO MUX Pin Functions 167
5-4 Power-Up Glitches on Pins 168
5-5 Analog Functions of IO MUX Pins 168
6-1 Reset Sources 184
6-2 CPU Clock Source 186
6-3 CPU Clock Frequency 186
6-4 Peripheral Clocks 187
6-5 APB_CLK Clock Frequency 188
6-6 CRYPTO_CLK Frequency 188
7-1 Default Configuration of Strapping Pins 189
7-2 Boot Mode Control 190
7-3 ROM Code Printing Control 191
8-1 CPU Peripheral Interrupt Configuration/Status Registers and Peripheral Interrupt Sources 194
9-1 Low-power Clocks 212
9-2 The Triggering Conditions for the RTC Timer 212
9-3 Predefined Power Modes 215
9-4 Wakeup Source 216
10-1 UNITn Configuration Bits 261
10-2 Trigger Point 262
10-3 Synchronization Operation 262
11-1 Alarm Generation When Up-Down Counter Increments 279
11-2 Alarm Generation When Up-Down Counter Decrements 279
14-1 ROM Address 304
14-2 Access Configuration to ROM (ROM0 and ROM1) 305
14-3 SRAM Address 305
14-4 Access Configuration to Internal SRAM0 306
14-5 Internal SRAM1 Split Regions 307
14-6 Access Configuration to the Instruction Region of Internal SRAM1 309
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14-7 Access Configuration to the Data Region of Internal SRAM1 309
14-8 RTC FAST Memory Address 309
14-9 Split RTC FAST Memory into the Higher Region and the Lower Region 310
14-10 Access Configuration to the RTC FAST Memory 310
14-11 Access Configuration of the Peripherals 310
14-12 Access Configuration of Peri Regions 312
14-13 Split the External Memory into Split Regions 313
14-14 Access Configuration of Flash Regions 313
14-15 Cache Virtual Address Region 314
14-16 Split IBUS Cache Virtual Address into 4 Regions 314
14-17 Split DBUS Cache Virtual Address into 4 Regions 314
14-18 Access Configuration of IBUS to Split Regions 315
14-19 Access Configuration of DBUS to Split Regions 315
14-20 Interrupt Registers for Unauthorized IBUS Access 316
14-21 Interrupt Registers for Unauthorized DBUS Access 316
14-22 Interrupt Registers for Unauthorized Access to External Memory 317
14-23 Interrupt Registers for Unauthorized Access to Internal Memory via GDMA 317
14-24 Interrupt Registers for Unauthorized PIF Access 318
14-25 All Possible Access Alignment and their Results 318
14-26 Interrupt Registers for Unauthorized Access Alignment 319
14-27 Lock Registers and Related Permission Control Registers 319
16-1 Memory Controlling Bit 415
16-2 Clock Gating and Reset Bits 416
17-1 CPU Packet Format 436
17-2 DMA Packet Format 436
17-3 DMA Source 436
17-4 Written Data Format 436
18-1 SHA Accelerator Working Mode 457
18-2 SHA Hash Algorithm Selection 458
18-3 The Storage and Length of Message Digest from Different Algorithms 462
19-1 AES Accelerator Working Mode 468
19-2 Key Length and Encryption/Decryption 468
19-3 Working Status under Typical AES Working Mode 469
19-4 Text Endianness Type for Typical AES 469
19-5 Key Endianness Type for AES-128 Encryption and Decryption 470
19-6 Key Endianness Type for AES-256 Encryption and Decryption 470
19-7 Block Cipher Mode 471
19-8 Working Status under DMA-AES Working mode 472
19-9 TEXT-PADDING 472
19-10 Text Endianness for DMA-AES 473
20-1 Acceleration Performance 484
20-2 RSA Accelerator Memory Blocks 484
21-1 HMAC Purposes and Configuration Value 492
23-1 Key generated based on Key
A
515
23-2 Mapping Between Offsets and Registers 517
26-1 UARTn Synchronous Registers 541
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26-2 UARTn Static Registers 542
27-2 Data Modes Supported by GP-SPI2 586
27-3 Mapping of FSPI Bus Signals 587
27-4 Functional Description of FSPI Bus Signals 587
27-5 Signals Used in Various SPI Modes 588
27-6 Bit Order Control in GP-SPI2 Master and Slave Modes 589
27-7 Supported Transfers in Master and Slave Modes 589
27-8 Registers Used for State Control in 1/2/4-bit Modes 598
27-8 Registers Used for State Control in 1/2/4-bit Modes 599
27-9 GP-SPI2 Master BM Table for CONF State 606
27-10 An Example of CONF bufferi in Segmenti 607
27-11 BM Bit Value v.s. Register to Be Updated in This Example 607
27-12 Supported CMD Values in SPI Mode 610
27-12 Supported CMD Values in SPI Mode 611
27-13 Supported CMD Values in QPI Mode 611
27-14 Clock Phase and Polarity Configuration in Master Mode 617
27-15 Clock Phase and Polarity Configuration in Slave Mode 617
27-16 GP-SPI2 Master Mode Interrupts 620
27-16 GP-SPI2 Master Mode Interrupts 621
27-17 GP-SPI2 Slave Mode Interrupts 621
28-1 I2C Synchronous Registers 654
29-2 I2S Signal Description 705
29-3 Bit Width of Channel Valid Data 712
29-4 Endian of Channel Valid Data 712
29-5 Data-Fetching Control in PDM TX Mode 715
29-6 I2S Channel Control in Normal PDM TX Mode 716
29-7 PCM-to-PDM TX Mode 716
29-8 Channel Storage Data Width 719
29-9 Channel Storage Data Endian 719
30-1 Standard CDC-ACM Control Requests 738
30-2 CDC-ACM Settings with RTS and DTR 738
30-3 Commands of a Nibble 740
30-4 USB-to-JTAG Control Requests 741
30-5 JTAG Capabilities Descriptor 742
30-6 Reset SoC into Download Mode 743
30-7 Reset SoC into Booting 743
31-1 Data Frames and Remote Frames in SFF and EFF 762
31-2 Error Frame 763
31-3 Overload Frame 764
31-4 Interframe Space 765
31-5 Segments of a Nominal Bit Time 767
31-6 Bit Information of TWAI_BUS_TIMING_0_REG (0x18) 771
31-7 Bit Information of TWAI_BUS_TIMING_1_REG (0x1c) 772
31-8 Buffer Layout for Standard Frame Format and Extended Frame Format 774
31-9 TX/RX Frame Information (SFF/EFF)�TWAI Address 0x40 775
31-10 TX/RX Identifier 1 (SFF); TWAI Address 0x44 775
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31-11 TX/RX Identifier 2 (SFF); TWAI Address 0x48 776
31-12 TX/RX Identifier 1 (EFF); TWAI Address 0x44 776
31-13 TX/RX Identifier 2 (EFF); TWAI Address 0x48 776
31-14 TX/RX Identifier 3 (EFF); TWAI Address 0x4c 776
31-15 TX/RX Identifier 4 (EFF); TWAI Address 0x50 776
31-16 Bit Information of TWAI_ERR_CODE_CAP_REG (0x30) 781
31-17 Bit Information of Bits SEG.4 - SEG.0 781
31-18 Bit Information of TWAI_ARB LOST CAP_REG (0x2c) 783
32-1 Commonly-used Frequencies and Resolutions 801
33-1 Configuration Update 820
34-1 SAR ADC Input Signals 840
34-2 Temperature Offset 847
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List of Figures
1-1 CPU Block Diagram 27
1-2 Debug System Overview 43
2-1 Modules with GDMA Feature and GDMA Channels 55
2-2 GDMA Engine Architecture 56
2-3 Structure of a Linked List 57
2-4 Relationship among Linked Lists 59
3-1 System Structure and Address Mapping 86
3-2 Cache Structure 90
3-3 Peripherals/modules that can work with GDMA 91
4-1 Shift Register Circuit (first 32 output) 101
4-2 Shift Register Circuit (last 12 output) 101
5-1 Diagram of IO MUX and GPIO Matrix 153
5-2 Architecture of IO MUX and GPIO Matrix 153
5-3 Internal Structure of a Pad 154
5-4 GPIO Input Synchronized on APB Clock Rising Edge or on Falling Edge 155
5-5 Filter Timing of GPIO Input Signals 155
6-1 Reset Types 183
6-2 System Clock 185
8-1 Interrupt Matrix Structure 192
9-1 Low-power Management Schematics 209
9-2 Power Management Unit Workflow 210
9-3 RTC Clocks 211
9-4 Wireless Clock 211
9-5 Digital System Regulator 213
9-6 Low-power voltage regulator 214
9-7 Brown-out detector 214
9-8 ESP32-C3 Boot Flow 219
10-1 System Timer Structure 259
10-2 System Timer Alarm Generation 260
11-1 Timer Units within Groups 277
11-2 Timer Group Architecture 278
12-1 Watchdog Timers Overview 294
12-2 Watchdog Timers in ESP32-C3 295
12-3 Super Watchdog Controller Structure 298
13-1 XTAL32K Watchdog Timer 300
14-1 Permission Control Overview 303
14-2 Split Lines for Internal SRAM1 306
14-3 An illustration of Configuring the Category fields 308
14-4 Two Ways to Access External Memory 312
15-1 Switching From Secure World to Non-secure World 401
15-2 Switching From Non-secure World to Secure World 402
15-3 World Switch Log Register 403
15-4 Nested Interrupts Handling - Entry 9 404
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15-5 Nested Interrupts Handling - Entry 1 404
15-6 Nested Interrupts Handling - Entry 4 405
21-1 HMAC SHA-256 Padding Diagram 495
21-2 HMAC Structure Schematic Diagram 495
22-1 Software Preparations and Hardware Working Process 506
23-1 Architecture of the External Memory Encryption and Decryption 514
24-1 XTAL_CLK Pulse Width 523
25-1 Noise Source 524
26-1 UART Architecture Overview 527
26-2 UART Structure 527
26-3 UART Controllers Sharing RAM 529
26-4 UART Controllers Division 531
26-5 The Timing Diagram of Weak UART Signals Along Falling Edges 532
26-6 Structure of UART Data Frame 533
26-7 AT_CMD Character Structure 533
26-8 Driver Control Diagram in RS485 Mode 534
26-9 The Timing Diagram of Encoding and Decoding in SIR mode 535
26-10 IrDA Encoding and Decoding Diagram 536
26-11 Hardware Flow Control Diagram 537
26-12 Connection between Hardware Flow Control Signals 537
26-13 Data Transfer in GDMA Mode 539
26-14 UART Programming Procedures 543
27-1 SPI Module Overview 586
27-2 Data Buffer Used in CPU-Controlled Transfer 590
27-3 GP-SPI2 Block Diagram 593
27-4 Data Flow Control in GP-SPI2 Master Mode 594
27-5 Data Flow Control in GP-SPI2 Slave Mode 595
27-6 GP-SPI2 State Machine in Master Mode 597
27-7 Full-Duplex Communication Between GP-SPI2 Master and a Slave 601
27-8 Connection of GP-SPI2 to Flash and External RAM in 4-bit Mode 604
27-9 SPI Quad I/O Read Command Sequence Sent by GP-SPI2 to Flash 604
27-10 Configurable Segmented Transfer in DMA-Controlled Master Mode 605
27-11 Recommended CS Timing and Settings When Accessing External RAM 614
27-12 Recommended CS Timing and Settings When Accessing Flash 615
27-13 SPI Clock Mode 0 or 2 616
27-14 SPI Clock Mode 1 or 3 616
27-15 Timing Compensation Control Diagram in GP-SPI2 Master Mode 618
27-16 Timing Compensation Example in GP-SPI2 Master Mode 619
28-1 I2C Master Architecture 651
28-2 I2C Slave Architecture 651
28-3 I2C Protocol Timing (Cited from Fig.31 in The I2C-bus specification Version 2.1) 652
28-4 I2C Timing Parameters (Cited from Table 5 in The I2C-bus specification Version 2.1) 653
28-5 I2C Timing Diagram 656
28-6 Structure of I2C Command Registers 658
28-7 I2C
28-8 I2C
Writing to I2C
master
Writing to a Slave with a 10-bit Address 663
master
with a 7-bit Address 661
slave
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28-9 I2C
28-10 I2C
28-11 I2C
28-12 I2C
28-13 I2C
28-14 I2C
Writing to I2C
master
Writing to I2C
master
Reading I2C
master
Reading I2C
master
Reading N Bytes of Data from addrM of I2C
master
Reading I2C
master
with Two 7-bit Addresses 665
slave
with a 7-bit Address in Multiple Sequences 667
slave
with a 7-bit Address 669
slave
with a 10-bit Address 671
slave
with a 7-bit Address in Segments 676
slave
with a 7-bit Address 673
slave
29-1 ESP32-C3 I2S System Diagram 704
29-2 TDM Philips Standard Timing Diagram 706
29-3 TDM MSB Alignment Standard Timing Diagram 707
29-4 TDM PCM Standard Timing Diagram 707
29-5 PDM Standard Timing Diagram 708
29-6 I2S Clock 708
29-7 TX Data Format Control 713
29-8 TDM Channel Control 715
29-9 PDM Channel Control Example 717
30-1 USB Serial/JTAG High Level Diagram 737
30-2 USB Serial/JTAG Block Diagram 737
31-1 Bit Fields in Data Frames and Remote Frames 761
31-2 Fields of an Error Frame 763
31-3 Fields of an Overload Frame 764
31-4 The Fields within an Interframe Space 765
31-5 Layout of a Bit 767
31-6 TWAI Overview Diagram 769
31-7 Acceptance Filter 778
31-8 Single Filter Mode 778
31-9 Dual Filter Mode 779
31-10 Error State Transition 780
31-11 Positions of Arbitration Lost Bits 782
32-1 LED PWM Architecture 798
32-2 LED PWM Generator Diagram 799
32-3 Frequency Division When LEDC_CLK_DIV is a Non-Integer Value 800
32-4 LED_PWM Output Signal Diagram 802
32-5 Output Signal Diagram of Fading Duty Cycle 803
33-1 RMT Architecture 815
33-2 Format of Pulse Code in RAM 815
34-1 SAR ADCs Function Overview 839
34-2 Diagram of DIG ADC FSM 842
34-3 APB_SARADC_SAR_PATT_TAB1_REG and Pattern Table Entry 0 - Entry 3 843
34-4 APB_SARADC_SAR_PATT_TAB2_REG and Pattern Table Entry 4 - Entry 7 843
34-5 Pattern Table Entry 843
34-6 cmd0 Configuration 844
34-7 cmd1 configuration 844
34-8 DMA Data Format 844
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1 ESPRISCV CPU
1.1 Overview
ESP-RISC-V CPU is a 32-bit core based upon RISC-V ISA comprising base integer (I), multiplication/division (M)
and compressed (C) standard extensions. The core has 4-stage, in-order, scalar pipeline optimized for area,
power and performance. CPU core complex has an interrupt-controller (INTC), debug module (DM) and system
bus (SYS BUS) interfaces for memory and peripheral access.
Figure 11. CPU Block Diagram
1.2 Features
• Operating clock frequency up to 160 MHz
• Zero wait cycle access to on-chip SRAM and Cache for program and data access over IRAM/DRAM
interface
• Interrupt controller (INTC) with up to 31 vectored interrupts with programmable priority and threshold levels
• Debug module (DM) compliant with RISC-V debug specification v0.13 with external debugger support over
an industry-standard JTAG/USB port
• Debugger direct system bus access (SBA) to memory and peripherals
• Hardware trigger compliant to RISC-V debug specification v0.13 with up to 8 breakpoints/watchpoints
• Physical memory protection (PMP) for up to 16 configurable regions
• 32-bit AHB system bus for peripheral access
• Configurable events for core performance metrics
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1.3 Address Map
Below table shows address map of various regions accessible by CPU for instruction, data, system bus
peripheral and debug.
Table 11. CPU Address Map
Name Description Starting Address Ending Address Access
IRAM Instruction Address Map 0x4000_0000 0x47FF_FFFF R/W
DRAM Data Address Map 0x3800_0000 0x3FFF_FFFF R/W
DM Debug Address Map 0x2000_0000 0x27FF_FFFF R/W
AHB AHB Address Map *default *default R/W
*default : Address not matching any of the specified ranges (IRAM, DRAM, DM) are accessed using AHB
bus.
1.4 Configuration and Status Registers (CSRs)
1.4.1 Register Summary
Below is a list of CSRs available to the CPU. Except for the custom performance counter CSRs, all the
implemented CSRs follow the standard mapping of bit fields as described in the RISC-V Instruction Set Manual,
Volume II: Privileged Architecture, Version 1.10. It must be noted that even among the standard CSRs, not all bit
fields have been implemented, limited by the subset of features implemented in the CPU. Refer to the next
section for detailed description of the subset of fields implemented under each of these CSRs.
The abbreviations given in Column Access are explained in Section Access Types for Registers.
Name Description Address Access
Machine Information CSRs
mvendorid Machine Vendor ID 0xF11 RO
marchid Machine Architecture ID 0xF12 RO
mimpid Machine Implementation ID 0xF13 RO
mhartid Machine Hart ID 0xF14 RO
Machine Trap Setup CSRs
mstatus Machine Mode Status 0x300 R/W
1
misa
2
mtvec
Machine Trap Handling CSRs
mscratch Machine Scratch 0x340 R/W
mepc Machine Trap Program Counter 0x341 R/W
mcause
3
mtval Machine Trap Value 0x343 R/W
Physical Memory Protection (PMP) CSRs
Machine ISA 0x301 R/W
Machine Trap Vector 0x305 R/W
Machine Trap Cause 0x342 R/W
1
Although misa is specified as having both read and write access (R/W), its fields are hardwired and thus write has no effect. This is what
would be termed WARL (Write Any Read Legal) in RISC-V terminology
2
mtvec only provides configuration for trap handling in vectored mode with the base address aligned to 256 bytes
3
External interrupt IDs reflected in mcause include even those IDs which have been reserved by RISC-V standard for core internal sources.
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Name Description Address Access
pmpcfg0 Physical memory protection configuration 0x3A0 R/W
pmpcfg1 Physical memory protection configuration 0x3A1 R/W
pmpcfg2 Physical memory protection configuration 0x3A2 R/W
pmpcfg3 Physical memory protection configuration 0x3A3 R/W
pmpaddr0 Physical memory protection address register 0x3B0 R/W
pmpaddr1 Physical memory protection address register 0x3B1 R/W
....
pmpaddr15 Physical memory protection address register 0x3BF R/W
Trigger Module CSRs (shared with Debug Mode)
tselect Trigger Select Register 0x7A0 R/W
tdata1 Trigger Abstract Data 1 0x7A1 R/W
tdata2 Trigger Abstract Data 2 0x7A2 R/W
tcontrol Global Trigger Control 0x7A5 R/W
Debug Mode CSRs
dcsr Debug Control and Status 0x7B0 R/W
dpc Debug PC 0x7B1 R/W
dscratch0 Debug Scratch Register 0 0x7B2 R/W
dscratch1 Debug Scratch Register 1 0x7B3 R/W
Performance Counter CSRs (Custom)
4
mpcer Machine Performance Counter Event 0x7E0 R/W
mpcmr Machine Performance Counter Mode 0x7E1 R/W
mpccr Machine Performance Counter Count 0x7E2 R/W
GPIO Access CSRs (Custom)
cpu_gpio_oen GPIO Output Enable 0x803 R/W
cpu_gpio_in GPIO Input Value 0x804 RO
cpu_gpio_out GPIO Output Value 0x805 R/W
Note that if write/set/clear operation is attempted on any of the CSRs which are read-only (RO), as indicated in
the above table, the CPU will generate illegal instruction exception.
1.4.2 Register Description
Register 1.1. mvendorid (0xF11)
MVENDORID
31 0
0x00000612
MVENDORID Vendor ID. (RO)
4
These custom CSRs have been implemented in the address space reserved by RISC-V standard for custom use
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Register 1.2. marchid (0xF12)
MARCHID
31 0
0x80000001
Reset
MARCHID Architecture ID. (RO)
Register 1.3. mimpid (0xF13)
MIMPID
31 0
0x00000001
Reset
MIMPID Implementation ID. (RO)
Register 1.4. mhartid (0xF14)
MHARTID
31 0
0x00000000
MHARTID Hart ID. (RO)
Reset
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Register 1.5. mstatus (0x300)
(reserved)
31 22
0x000
TW
21
20 13
0
(reserved)
0x00
MPP
12 11
0x0
(reserved)
10 8
0x0
MPIE
7
6 4
0
(reserved)
0x0
MIE Global machine mode interrupt enable. (R/W)
MPIE Machine previous interrupt enable (before trap). (R/W)
MPP Machine previous privilege mode (before trap). (R/W)
Possible values:
• 0x0: User mode
• 0x3: Machine mode
Note : Only lower bit is writable. Write to the higher bit is ignored as it is directly tied to the lower bit.
TW Timeout wait. (R/W)
If this bit is set, executing WFI (Wait-for-Interrupt) instruction in User mode will cause illegal instruc-
tion exception.
MIE
3
2 0
0
(reserved)
0x0
Reset
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Register 1.6. misa (0x301)
MXL
31 30
0x1
(reserved)
29 26
0x0
U
Z
Y
25
24
0
0
V
X
W
23
22
21
0
0
T
20
19
18
0
1
0
Q
S
R
17
16
0
0
0
MXL Machine XLEN = 1 (32-bit). (RO)
Z Reserved = 0. (RO)
Y Reserved = 0. (RO)
X Non-standard extensions present = 0. (RO)
W Reserved = 0. (RO)
V Reserved = 0. (RO)
U User mode implemented = 1. (RO)
T Reserved = 0. (RO)
S Supervisor mode implemented = 0. (RO)
R Reserved = 0. (RO)
Q Quad-precision floating-point extension = 0. (RO)
O
P
15
14
0
M
N
13
12
11
0
0
1
J
L
K
10
9
0
0
0
G
H
I
8
1
F
7
6
5
0
0
0
C
D
B
E
4
3
0
0
A
2
1
0
1
0
0
Reset
P Reserved = 0. (RO)
O Reserved = 0. (RO)
N User-level interrupts supported = 0. (RO)
M Integer Multiply/Divide extension = 1. (RO)
L Reserved = 0. (RO)
K Reserved = 0. (RO)
J Reserved = 0. (RO)
I RV32I base ISA = 1. (RO)
H Hypervisor extension = 0. (RO)
G Additional standard extensions present = 0. (RO)
F Single-precision floating-point extension = 0. (RO)
E RV32E base ISA = 0. (RO)
D Double-precision floating-point extension = 0. (RO)
C Compressed Extension = 1. (RO)
B Reserved = 0. (RO)
A Atomic Extension = 0. (RO)
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Register 1.7. mtvec (0x305)
BASE
31 8
0x000000
(reserved)
7 2
0x00
MODE
1 0
0x1
MODE Only vectored mode 0x1 is available. (RO)
BASE Higher 24 bits of trap vector base address aligned to 256 bytes. (R/W)
Register 1.8. mscratch (0x340)
MSCRATCH
31 0
0x00000000
MSCRATCH Machine scratch register for custom use. (R/W)
Register 1.9. mepc (0x341)
Reset
Reset
MEPC
31 0
0x00000000
MEPC Machine trap/exception program counter. (R/W)
This is automatically updated with address of the instruction which was about to be executed while
CPU encountered the most recent trap.
Reset
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Register 1.10. mcause (0x342)
Interrupt Flag
31
30 5
0
(reserved)
0x0000000
4 0
Exception Code
0x00
Exception Code This field is automatically updated with unique ID of the most recent exception or
interrupt due to which CPU entered trap. (R/W)
Possible exception IDs are:
• 0x1: PMP Instruction access fault
• 0x2: Illegal Instruction
• 0x3: Hardware Breakpoint/Watchpoint or EBREAK
• 0x5: PMP Load access fault
• 0x7: PMP Store access fault
• 0x8: ECALL from U mode
• 0xb: ECALL from M mode
Note : Exception ID 0x0 (instruction access misaligned) is not present because CPU always masks
the lowest bit of the address during instruction fetch.
Interrupt Flag This flag is automatically updated when CPU enters trap. (R/W)
If this is found to be set, indicates that the latest trap occurred due to interrupt. For exceptions it
remains unset.
Note : The interrupt controller is using up IDs in range 1-31 for all external interrupt sources. This is
different from the RISC-V standard which has reserved IDs in range 0-15 for core internal interrupt
sources.
Reset
Register 1.11. mtval (0x343)
MTVAL
31 0
0x00000000
MTVAL Machine trap value. (R/W)
This is automatically updated with an exception dependent data which may be useful for handling
that exception.
Data is to be interpreted depending upon exception IDs:
• 0x1: Faulting virtual address of instruction
• 0x2: Faulting instruction opcode
• 0x5: Faulting data address of load operation
• 0x7: Faulting data address of store operation
Note : The value of this register is not valid for other exception IDs and interrupts.
Reset
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Register 1.12. mpcer (0x7E0)
(reserved)
31 11
0x000
(BRANCH_TAKEN
INST_COMP
BRANCH
10
9
8
0
0
0
JMP_UNCOND
STORE
7
6
0
0
INST_COMP Count Compressed Instructions. (R/W)
BRANCH_TAKEN Count Branches Taken. (R/W)
BRANCH Count Branches. (R/W)
JMP_UNCOND Count Unconditional Jumps. (R/W)
STORE Count Stores. (R/W)
LOAD Count Loads. (R/W)
IDLE Count IDLE Cycles. (R/W)
JMP_HAZARD Count Jump Hazards. (R/W)
LD_HAZARD Count Load Hazards. (R/W)
INST Count Instructions. (R/W)
CYCLE Count Clock Cycles. Cycle count does not increment during WFI mode. (R/W)
LOAD
5
0
JMP_HAZARD
IDLE
4
3
0
0
LD_HAZARD
INST
CYCLE
2
1
0
0
0
0
Reset
Note: Each bit selects a specic event for counter to increment. If more than one event is selected
and occurs simultaneously, then counter increments by one only.
Register 1.13. mpcmr (0x7E1)
(reserved)
31 2
0
COUNT_SAT Counter Saturation Control. (R/W)
Possible values:
• 0: Overflow on maximum value
• 1: Halt on maximum value
COUNT_EN Counter Enable Control. (R/W)
Possible values:
• 0: Disabled
• 1: Enabled
COUNT_SAT
COUNT_EN
1
0
1
1
Reset
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Register 1.14. mpccr (0x7E2)
MPCCR
31
0x00000000
0
Reset
MPCCR Machine Performance Counter Value. (R/W)
Register 1.15. cpu_gpio_oen (0x803)
(reserved)
31 8
0
CPU_GPIO_OEN[6]
CPU_GPIO_OEN[5]
CPU_GPIO_OEN[7]
7
6
5
0
0
0
CPU_GPIO_OEN[2]
CPU_GPIO_OEN[4]
4
0
CPU_GPIO_OEN[1]
CPU_GPIO_OEN[3]
3
2
1
0
0
0
CPU_GPIO_OEN GPIOn (n=0 ~ 21) Output Enable. CPU_GPIO_OEN[7:0] correspond to out-
put enable signals cpu_gpio_out_oen[7:0] in Table 5-2 Peripheral Signals via GPIO Matrix.
CPU_GPIO_OEN value matches that of cpu_gpio_out_oen.
CPU_GPIO_OEN is the enable signal of CPU_GPIO_OUT. (R/W)
• 0: GPIO output disable
• 1: GPIO output enable
Register 1.16. cpu_gpio_in (0x804)
(reserved)
31 8
0
CPU_GPIO_IN[7]
7
0
CPU_GPIO_IN[4]
CPU_GPIO_IN[6]
6
0
CPU_GPIO_IN[3]
CPU_GPIO_IN[5]
5
4
3
0
0
0
CPU_GPIO_IN[2]
CPU_GPIO_IN[1]
2
1
0
0
CPU_GPIO_OEN[0]
0
0
Reset
CPU_GPIO_IN[0]
0
0
Reset
CPU_GPIO_IN GPIOn (n=0 ~ 21) Input Value. It is a CPU CSR to read input value (1=high, 0=low)
from SoC GPIO pin.
CPU_GPIO_IN[7:0] correspond to input signals cpu_gpio_in[7:0] in Table 5-2 Peripheral Signals via
GPIO Matrix.
CPU_GPIO_IN[7:0] can only be mapped to GPIO pins through GPIO matrix. For details please
refer to Section 5.4 in Chapter IO MUX and GPIO Matrix (GPIO, IO MUX). (RO)
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Register 1.17. cpu_gpio_out (0x805)
(reserved)
31 8
0
CPU_GPIO_OUT[7]
CPU_GPIO_OUT[6]
7
6
0
0
CPU_GPIO_OUT[3]
CPU_GPIO_OUT[2]
CPU_GPIO_OUT[5]
CPU_GPIO_OUT[4]
5
4
0
0
CPU_GPIO_OUT[1]
3
2
1
0
0
0
CPU_GPIO_OUT GPIOn (n=0 ~ 21) Output Value. It is a CPU CSR to write value (1=high, 0=low) to
SoC GPIO pin. The value takes effect only when CPU_GPIO_OEN is set.
CPU_GPIO_OUT[7:0] correspond to output signals cpu_gpio_out[7:0] in Table 5-2 Peripheral Sig-
nals via GPIO Matrix.
CPU_GPIO_OUT[7:0] can only be mapped to GPIO pins through GPIO matrix. For details please
refer to Section 5.5 in Chapter IO MUX and GPIO Matrix (GPIO, IO MUX). (R/W)
CPU_GPIO_OUT[0]
0
0
Reset
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1.5 Interrupt Controller
1.5.1 Features
The interrupt controller allows capturing, masking and dynamic prioritization of interrupt sources routed from
peripherals to the RISC-V CPU. It supports:
• Up to 31 asynchronous interrupts with unique IDs (1-31)
• Configurable via read/write to memory mapped registers
• 15 levels of priority, programmable for each interrupt
• Support for both level and edge type interrupt sources
• Programmable global threshold for masking interrupts with lower priority
• Interrupts IDs mapped to trap-vector address offsets
For the complete list of interrupt registers and detailed configuration information, please refer to Chapter 8
Interrupt Matrix (INTERRUPT), section 8.4, register group ”CPU Interrupt Registers”.
1.5.2 Functional Description
Each interrupt ID has 5 properties associated with it:
1. Enable State (0-1):
• Determines if an interrupt is enabled to be captured and serviced by the CPU.
• Programmed by writing the corresponding bit in INTERRUPT_CORE0_CPU_INT_ENABLE_REG.
2. Type (0-1):
• Enables latching the state of an interrupt signal on its rising edge.
• Programmed by writing the corresponding bit in INTERRUPT_CORE0_CPU_INT_TYPE_REG.
• An interrupt for which type is kept 0 is referred as a ’level’ type interrupt.
• An interrupt for which type is set to 1 is referred as an ’edge’ type interrupt.
3. Priority (1-15):
• Determines which interrupt, among multiple pending interrupts, the CPU will service first.
• Programmed by writing to the INTERRUPT_CORE0_CPU_INT_PRI_n_REG for a particular interrupt ID
n in range (1-31).
• Enabled interrupts with priorities zero or less than the threshold value in
INTERRUPT_CORE0_CPU_INT_THRESH_REG are masked.
• Priority levels increase from 1 (lowest) to 15 (highest).
• Interrupts with same priority are statically prioritized by their IDs, lowest ID having highest priority.
4. Pending State (0-1):
• Reflects the captured state of an enabled and unmasked interrupt signal.
• For each interrupt ID, the corresponding bit in read-only
INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG gives its pending state.
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• A pending interrupt will cause CPU to enter trap if no other pending interrupt has higher priority.
• A pending interrupt is said to be ’claimed’ if it preempts the CPU and causes it to jump to the
corresponding trap vector address.
• All pending interrupts which are yet to be serviced are termed as ’unclaimed’.
5. Clear State (0-1):
• Toggling this will clear the pending state of claimed edge-type interrupts only.
• Toggled by first setting and then clearing the corresponding bit in
INTERRUPT_CORE0_CPU_INT_CLEAR_REG.
• Pending state of a level type interrupt is unaffected by this and must be cleared from source.
• Pending state of an unclaimed edge type interrupt can be flushed, if required, by first clearing the
corresponding bit in INTERRUPT_CORE0_CPU_INT_ENABLE_REG and then toggling same bit in
INTERRUPT_CORE0_CPU_INT_CLEAR_REG.
When CPU services a pending interrupt, it:
• saves the address of the current un-executed instruction in mepc for resuming execution later.
• updates the value of mcause with the ID of the interrupt being serviced.
• copies the state of MIE into MPIE, and subsequently clears MIE, thereby disabling interrupts globally.
• enters trap by jumping to a word-aligned offset of the address stored in mtvec.
Table 1-3 shows the mapping of each interrupt ID with the corresponding trap-vector address. In short, the word
aligned trap address for an interrupt with a certain ID = i can be calculated as (mtvec + 4i).
Note : ID = 0 is unavailable and therefore cannot be used for capturing interrupts. This is because the
corresponding trap vector address (mtvec + 0x00) is reserved for exceptions.
Table 13. ID wise map of Interrupt TrapVector Addresses
ID Address ID Address ID Address ID Address
0 NA 8 mtvec + 0x20 16 mtvec + 0x40 24 mtvec + 0x60
1 mtvec + 0x04 9 mtvec + 0x24 17 mtvec + 0x44 25 mtvec + 0x64
2 mtvec + 0x08 10 mtvec + 0x28 18 mtvec + 0x48 26 mtvec + 0x68
3 mtvec + 0x0c 11 mtvec + 0x2c 19 mtvec + 0x4c 27 mtvec + 0x6c
4 mtvec + 0x10 12 mtvec + 0x30 20 mtvec + 0x50 28 mtvec + 0x70
5 mtvec + 0x14 13 mtvec + 0x34 21 mtvec + 0x54 29 mtvec + 0x74
6 mtvec + 0x18 14 mtvec + 0x38 22 mtvec + 0x58 30 mtvec + 0x78
7 mtvec + 0x1c 15 mtvec + 0x3c 23 mtvec + 0x5c 31 mtvec + 0x7c
After jumping to the trap-vector, the execution flow is dependent on software implementation, although it can be
presumed that the interrupt will get handled (and cleared) in some interrupt service routine (ISR) and later the
normal execution will resume once the CPU encounters MRET instruction.
Upon execution of MRET instruction, the CPU:
• copies the state of MPIE back into MIE, and subsequently clears MPIE. This means that if previously MPIE
was set, then, after MRET, MIE will be set, thereby enabling interrupts globally.
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• jumps to the address stored in mepc and resumes execution.
It is possible to perform software assisted nesting of interrupts inside an ISR as explained in 1.5.3.
The below listed points outline the functional behavior of the controller:
• Only if an interrupt has non-zero priority, higher or equal to the value in the threshold register, will it be
reflected in INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG.
• If an interrupt is visible in INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG and has yet to be serviced,
then it’s possible to mask it (and thereby prevent the CPU from servicing it) by either lowering the value of
its priority or increasing the global threshold.
• If an interrupt, visible in INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG, is to be flushed (and prevented
from being serviced at all), then it must be disabled (and cleared if it is of edge type).
1.5.3 Suggested Operation
1.5.3.1 Latency Aspects
There is latency involved while configuring the Interrupt Controller.
In steady state operation, the Interrupt Controller has a fixed latency of 4 cycles. Steady state means that no
changes have been made to the Interrupt Controller registers recently. This implies that any interrupt that is
asserted to the controller will take exactly 4 cycles before the CPU starts processing the interrupt. This further
implies that CPU may execute up to 5 instructions before the preemption happens.
Whenever any of its registers are modified, the Interrupt Controller enters into transient state, which may take up
to 4 cycles for it to settle down into steady state again. During this transient state, the ordering of interrupts may
not be predictable, and therefore, a few safety measures need to be taken in software to avoid any
synchronization issues.
Also, it must be noted that the Interrupt Controller configuration registers lie in the APB address range, hence any
R/W access to these registers may take multiple cycles to complete.
In consideration of above mentioned characteristics, users are advised to follow the sequence described below,
whenever modifying any of the Interrupt Controller registers:
1. save the state of MIE and clear MIE to 0
2. read-modify-write one or more Interrupt Controller registers
3. execute FENCE instruction to wait for any pending write operations to complete
4. finally, restore the state of MIE
Due to its critical nature, it is recommended to disable interrupts globally (MIE=0) beforehand, whenever
configuring interrupt controller registers, and then restore MIE right after, as shown in the sequence above.
After execution of the sequence above, the Interrupt Controller will resume operation in steady state.
1.5.3.2 Configuration Procedure
By default, interrupts are disabled globally, since the reset value of MIE bit in mstatus is 0. Software must set
MIE=1 after initialization of the interrupt stack (including setting mtvec to the interrupt vector address) is
done.
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During normal execution, if an interrupt n is to be enabled, the below sequence may be followed:
1. save the state of MIE and clear MIE to 0
2. depending upon the type of the interrupt (edge/level), set/unset the nth bit of
INTERRUPT_CORE0_CPU_INT_TYPE_REG
3. set the priority by writing a value to INTERRUPT_CORE0_CPU_INT_PRI_n_REG in range 1(lowest) to 15
(highest)
4. set the nth bit of INTERRUPT_CORE0_CPU_INT_ENABLE_REG
5. execute FENCE instruction
6. restore the state of MIE
When one or more interrupts become pending, the CPU acknowledges (claims) the interrupt with the highest
priority and jumps to the trap vector address corresponding to the interrupt’s ID. Software implementation may
read mcause to infer the type of trap (mcause(31) is 1 for interrupts and 0 for exceptions) and then the ID of the
interrupt (mcause(4-0) gives ID of interrupt or exception). This inference may not be necessary if each entry in the
trap vector are jump instructions to different trap handlers. Ultimately, the trap handler(s) will redirect execution to
the appropriate ISR for this interrupt.
Upon entering into an ISR, software must toggle the nth bit of INTERRUPT_CORE0_CPU_INT_CLEAR_REG if
the interrupt is of edge type, or clear the source of the interrupt if it is of level type.
Software may also update the value of INTERRUPT_CORE0_CPU_INT_THRESH_REG and program MIE=1 for
allowing higher priority interrupts to preempt the current ISR (nesting), however, before doing so, all the state
CSRs must be saved (mepc, mstatus, mcause, etc.) since they will get overwritten due to occurrence of such an
interrupt. Later, when exiting the ISR, the values of these CSRs must be restored.
Finally, after the execution returns from the ISR back to the trap handler, MRET instruction is used to resume
normal execution.
Later, if the n interrupt is no longer needed and needs to be disabled, the following sequence may be
followed:
1. save the state of MIE and clear MIE to 0
2. check if the interrupt is pending in INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG
3. set/unset the nth bit of INTERRUPT_CORE0_CPU_INT_ENABLE_REG
4. if the interrupt is of edge type and was found to be pending in step 2 above, nth bit of
INTERRUPT_CORE0_CPU_INT_CLEAR_REG must be toggled, so that its pending status gets flushed
5. execute FENCE instruction
6. restore the state of MIE
Above is only a suggested scheme of operation. Actual software implementation may vary.
1.5.4 Register Summary
The addresses in this section are relative to Interrupt Controller base address provided in Table 3-3 in Chapter 3
System and Memory.
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For the complete list of interrupt registers and detailed configuration information, please refer to Chapter 8
Interrupt Matrix (INTERRUPT), section 8.4, register group ”CPU Interrupt Registers”.
1.5.5 Register Description
The addresses in this section are relative to Interrupt Controller base address provided in Table 3-3 in Chapter 3
System and Memory.
For the complete list of interrupt registers and detailed configuration information, please refer to Chapter 8
Interrupt Matrix (INTERRUPT), section 8.4, register group ”CPU Interrupt Registers”.
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1.6 Debug
1.6.1 Overview
This section describes how to debug and test software running on CPU core. Debug support is provided through
standard JTAG pins and complies to RISC-V External Debug Support Specification version 0.13.
Figure 1-2 below shows the main components of External Debug Support.
Figure 12. Debug System Overview
The user interacts with the Debug Host (eg. laptop), which is running a debugger (eg. gdb). The debugger
communicates with a Debug Translator (eg. OpenOCD, which may include a hardware driver) to communicate
with Debug Transport Hardware (eg. Olimex USB-JTAG adapter). The Debug Transport Hardware connects the
Debug Host to the ESP-RV Core’s Debug Transport Module (DTM) through standard JTAG interface. The DTM
provides access to the Debug Module (DM) using the Debug Module Interface (DMI).
The DM allows the debugger to halt the core. Abstract commands provide access to its GPRs (general purpose
registers). The Program Buffer allows the debugger to execute arbitrary code on the core, which allows access to
additional CPU core state. Alternatively, additional abstract commands can provide access to additional CPU
core state. ESP-RV core contains Trigger Module supporting 8 triggers. When trigger conditions are met, cores
will halt spontaneously and inform the debug module that they have halted.
System bus access block allows memory and peripheral register access without using RISC-V core.
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1.6.2 Features
Basic debug functionality supports below features.
• Provides necessary information about the implementation to the debugger.
• Allows the CPU core to be halted and resumed.
• CPU core registers (including CSR’s) can be read/written by debugger.
• CPU can be debugged from the first instruction executed after reset.
• CPU core can be reset through debugger.
• CPU can be halted on software breakpoint (planted breakpoint instruction).
• Hardware single-stepping.
• Execute arbitrary instructions in the halted CPU by means of the program buffer. 16-word program buffer is
supported.
• System bus access is supported through word aligned address access.
• Supports eight Hardware Triggers (can be used as breakpoints/watchpoints) as described in Section 1.7.
1.6.3 Functional Description
As mentioned earlier, Debug Scheme conforms to RISC-V External Debug Support Specification version 0.13.
Please refer the specs for functional operation details.
1.6.4 Register Summary
Below is the list of Debug CSR’s supported by ESP-RV core.
The abbreviations given in Column Access are explained in Section Access Types for Registers.
Name Description Address Access
dcsr Debug Control and Status 0x7B0 R/W
dpc Debug PC 0x7B1 R/W
dscratch0 Debug Scratch Register 0 0x7B2 R/W
dscratch1 Debug Scratch Register 1 0x7B3 R/W
All the debug module registers are implemented in conformance to RISC-V External Debug Support Specification
version 0.13. Please refer it for more details.
1.6.5 Register Description
Below are the details of Debug CSR’s supported by ESP-RV core
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Register 1.18. dcsr (0x7B0)
xdebugver
31 28
4
reserved
27 16
0
ebreakm
15
14 13
0
reserved
12
0
ebreaku
11
0
0
stopcount
reserved
10
0
stoptime
9
8 6
0
cause
0
reserved
5 3
0
xdebugver Debug version. (RO)
• 4: External debug support exists
ebreakm When 1, ebreak instructions in Machine Mode enter Debug Mode. (R/W)
ebreaku When 1, ebreak instructions in User/Application Mode enter Debug Mode. (R/W)
stopcount This bit is not implemented. Debugger will always read this bit as 0. (RO)
stoptime This feature is not implemented. Debugger will always read this bit as 0. (RO)
cause Explains why Debug Mode was entered. When there are multiple reasons to enter Debug
Mode in a single cycle, the cause with the highest priority number is the one written.
1. An ebreak instruction was executed. (priority 3)
2. The Trigger Module caused a halt. (priority 4)
3. haltreq was set. (priority 2)
4. The CPU core single stepped because step was set. (priority 1)
step
2
0
prv
1 0
0
Reset
Other values are reserved for future use. (RO)
step When set and not in Debug Mode, the core will only execute a single instruction and then enter
Debug Mode. Interrupts are enabled* when this bit is set. If the instruction does not complete due
to an exception, the core will immediately enter Debug Mode before executing the trap handler,
with appropriate exception registers set. (R/W)
prv Contains the privilege level the core was operating in when Debug Mode was entered. A debugger
can change this value to change the core’s privilege level when exiting Debug Mode. Only 0x3
(machine mode) and 0x0(user mode) are supported.
*Note: Different from RISC-V Debug specification 0.13
Register 1.19. dpc (0x7B1)
dpc
31 0
0
dpc Upon entry to debug mode, dpc is written with the virtual address of the instruction that encoun-
tered the exception. When resuming, the CPU core’s PC is updated to the virtual address stored
in dpc. A debugger may write dpc to change where the CPU resumes. (R/W)
Reset
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Register 1.20. dscratch0 (0x7B2)
dscratch0
31 0
0
Reset
dscratch0 Used by Debug Module internally. (R/W)
Register 1.21. dscratch1 (0x7B3)
dscratch1
31 0
0
Reset
dscratch1 Used by Debug Module internally. (R/W)
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1.7 Hardware Trigger
1.7.1 Features
Hardware Trigger module provides breakpoint and watchpoint capability for debugging. It includes the following
features:
• 8 independent trigger units
• each unit can be configured for matching the address of program counter or load-store accesses
• can preempt execution by causing breakpoint exception
• can halt execution and transfer control to debugger
• support NAPOT (naturally aligned power of two) address encoding
1.7.2 Functional Description
The Hardware Trigger module provides four CSRs, which are listed under register summary section. Among
these, tdata1 and tdata2 are abstract CSRs, which means they are shadow registers for accessing internal
registers for each of the eight trigger units, one at a time.
To choose a particular trigger unit write the index (0-7) of that unit into tselect CSR. When tselect is written with a
valid index, the abstract CSRs tdata1 and tdata2 are automatically mapped to reflect internal registers of that
trigger unit. Each trigger unit has two internal registers, namely mcontrol and maddress, which are mapped to
tdata1 and tdata2, respectively.
Writing larger than allowed indexes to tselect will clip the written value to the largest valid index, which can be
read back. This property may be used for enumerating the number of available triggers during initialization or
when using a debugger.
Since software or debugger may need to know the type of the selected trigger to correctly interpret tdata1 and
tdata2, the 4 bits (31-28) of tdata1 encodes the type of the selected trigger. This type field is read-only and always
provides a value of 0x2 for every trigger, which stands for match type trigger, hence, it is inferred that tdata1 and
tdata2 are to be interpreted as mcontrol and maddress. The information regarding other possible values can be
found in the RISC-V Debug Specification v0.13, but this trigger module only supports type 0x2.
Once a trigger unit has been chosen by writing its index to tselect, it will become possible to configure it by setting
the appropriate bits in mcontrol CSR (tdata1) and writing the target address to maddress CSR (tdata2).
Each trigger unit can be configured to either cause breakpoint exception or enter debug mode, by writing to the
action bit of mcontrol. This bit can only be written from debugger, thus by default a trigger, if enabled, will cause
breakpoint exception.
mcontrol for each trigger unit has a hit bit which may be read, after CPU halts or enters exception, to find out if
this was the trigger unit that fired. This bit is set as soon as the corresponding trigger fires, but it has to be
manually cleared before resuming operation. Although, failing to clear it doesn’t affect normal execution in any
way.
Each trigger unit only supports match on address, although this address could either be that of a load/store
access or the virtual address of an instruction. The address and size of a region are specified by writing to
maddress (tdata2) CSR for the selected trigger unit. Larger than 1 byte region sizes are specified through NAPOT
(naturally aligned power of two) encoding (see Table 1-5) and enabled by setting match bit in mcontrol. Note that
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for NAPOT encoded addresses, by definition, the start address is constrained to be aligned to (i.e. an integer
multiple of) the region size.
Table 15. NAPOT encoding for maddress
maddress(31-0) Start Address Size (bytes)
aaa...aaaaaaaaa0 aaa...aaaaaaaaa0 2
aaa...aaaaaaaa01 aaa...aaaaaaaa00 4
aaa...aaaaaaa011 aaa...aaaaaaa000 8
aaa...aaaaaa0111 aaa...aaaaaa0000 16
....
a01...1111111111 a00...0000000000 2
tcontrol CSR is common to all trigger units. It is used for preventing triggers from causing repeated exceptions in
machine-mode while execution is happening inside a trap handler. This also disables breakpoint exceptions
inside ISRs by default, although, it is possible to manually enable this right before entering an ISR, for debugging
purposes. This CSR is not relevant if a trigger is configured to enter debug mode.
31
1.7.3 Trigger Execution Flow
When hart is halted and enters debug mode due to the firing of a trigger (action = 1):
• dpc is set to current PC (in decode stage)
• cause field in dcsr is set to 2, which means halt due to trigger
• hit bit is set to 1, corresponding to the trigger(s) which fired
When hart goes into trap due to the firing of a trigger (action = 0) :
• mepc is set to current PC (in decode stage)
• mcause is set to 3, which means breakpoint exception
• mpte is set to the value in mte right before trap
• mte is set to 0
• hit bit is set to 1, corresponding to the trigger(s) which fired
Note : If two different triggers re at the same time, one with action = 0 and another with action = 1, then hart is
halted and enters debug mode.
1.7.4 Register Summary
Below is a list of Trigger Module CSRs supported by the CPU. These are only accessible from
machine-mode.
The abbreviations given in Column Access are explained in Section Access Types for Registers.
Name Description Address Access
tselect Trigger Select Register 0x7A0 R/W
tdata1 Trigger Abstract Data 1 0x7A1 R/W
tdata2 Trigger Abstract Data 2 0x7A2 R/W
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Name Description Address Access
tcontrol Global Trigger Control 0x7A5 R/W
1.7.5 Register Description
Register 1.22. tselect (0x7A0)
(reserved)
31 3
0x00000000
tselect Index (0-7) of the selected trigger unit. (R/W)
Register 1.23. tdata1 (0x7A1)
type
31 28
0x2
dmode
27
26 0
0
data
0x3e00000
type Type of trigger. (RO)
This field is reserved since only match type (0x2) triggers are supported.
dmode This is set to 1 if a trigger is being used by the debugger. (R/W *)
• 0: Both Debug and M-mode can write the tdata1 and tdata2 registers at the selected tselect.
• 1: Only Debug Mode can write the tdata1 and tdata2 registers at the selected tselect. Writes
from other modes are ignored.
tselect
2 0
0x0
Reset
Reset
* Note : Only writable from debug mode.
data Abstract tdata1 content. (R/W)
This will always be interpreted as fields of mcontrol since only match type (0x2) triggers are sup-
ported.
Register 1.24. tdata2 (0x7A2)
tdata2
31 0
0x00000000
tdata2 Abstract tdata2 content. (R/W)
This will always be interpreted as maddress since only match type (0x2) triggers are supported.
Reset
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Register 1.25. tcontrol (0x7A5)
(reserved)
31 8
0x000000
mpte Machine mode previous trigger enable bit. (R/W)
• When CPU is taking a machine mode trap, the value of mte is automatically pushed into this.
• When CPU is executing MRET, its value is popped back into mte, so this becomes 0.
mte Machine mode trigger enable bit. (R/W)
• When CPU is taking a machine mode trap, its value is automatically pushed into mpte, so this
becomes 0 and triggers with action=0 are disabled globally.
• When CPU is executing MRET, the value of mpte is automatically popped back into this.
mpte
7
6 1
0
(reserved)
0x00
mte
0
0
Reset
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Register 1.26. mcontrol (0x7A1)
(reserved)
31 28
0x2
dmode
27
26 21
0
(reserved)
0x1f
hit
20
19 16
0
(reserved)
0
action
15 12
0
(reserved)
11
10 7
0
match
0
m
6
0
(reserved)
5 4
0
u
3
0
execute
store
2
1
0
0
dmode Same as dmode in tdata1.
hit This is found to be 1 if the selected trigger had fired previously. (R/W)
This bit is to be cleared manually.
action Write this for configuring the selected trigger to perform one of the available actions when firing.
(R/W)
Valid options are:
• 0x0: cause breakpoint exception.
• 0x1: enter debug mode (only valid when dmode = 1)
Note : Writing an invalid value will set this to the default value 0x0.
match Write this for configuring the selected trigger to perform one of the available matching opera-
tions on a data/instruction address. (R/W) Valid options are:
• 0x0: exact byte match, i.e. address corresponding to one of the bytes in an access must
match the value of maddress exactly.
• 0x1: NAPOT match, i.e. at least one of the bytes of an access must lie in the NAPOT region
specified in maddress.
load
0
0
Reset
Note : Writing a larger value will clip it to the largest possible value 0x1.
m Set this for enabling selected trigger to operate in machine mode. (R/W)
u Set this for enabling selected trigger to operate in user mode. (R/W)
execute Set this for configuring the selected trigger to fire right before an instruction with matching
virtual address is executed by the CPU. (R/W)
store Set this for configuring the selected trigger to fire right before a store operation with matching
data address is executed by the CPU. (R/W)
load Set this for configuring the selected trigger to fire right before a load operation with matching
data address is executed by the CPU. (R/W)
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Register 1.27. maddress (0x7A2)
maddress
31 0
0x00000000
Reset
maddress Address used by the selected trigger when performing match operation. (R/W)
This is decoded as NAPOT when match=1 in mcontrol.
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1.8 Memory Protection
1.8.1 Overview
The CPU core includes a physical memory protection unit, which can be used by software to set memory access
privileges (read, write and execute permissions) for required memory regions. However it is not fully compliant to
the Physical Memory Protection (PMP) description specified in RISCV Instruction Set Manual, Volume II:
Privileged Architecture, Version 1.10. Details of existing non-conformance are provided in next section.
For detailed understanding of the RISC-V PMP concept, please refer to RISC-V Instruction Set Manual, Volume II:
Privileged Architecture, Version 1.10.
1.8.2 Features
The PMP unit can be used to restrict access to physical memory. It supports 16 regions and a minimum
granularity of 4 bytes. Below are the current non-conformance with PMP description from RISC-V Privilege
specifications:
• Static priority i.e. overlapping regions are not supported
• Maximum supported NAPOT range is 1 GB
As per RISC-V Privilege specifications, PMP entries should be statically prioritized and the lowest-numbered PMP
entry that matches any address byte of an access will determine whether that access succeeds or fails. This
means, when any address matches more than one PMP entry i.e. overlapping regions among different PMP
entries, lowest number PMP entry will decide whether such address access will succeed or fail.
However, RISC-V CPU PMP unit in ESP32-C3 does not implement static priority. So, software should make sure
that all enabled PMP entries are programmed with unique regions i.e. without any region overlap among them. If
software still tries to program multiple PMP entries with overlapping region having contradicting permissions, then
access will succeed if it matches at least one of enabled PMP entries. An exception will be generated, if access
matches none of the enabled PMP entries.
1.8.3 Functional Description
Software can program the PMP unit’s configuration and address registers in order to contain faults and support
secure execution. PMP CSR’s can only be programmed in machine-mode. Once enabled, write, read and
execute permission checks are applied to all the accesses in user-mode as per programmed values of enabled
16 pmpcfgX and pmpaddrX registers (refer Register Summary).
By default, PMP grants permission to all accesses in machine-mode and revokes permission of all access in
user-mode. This implies that it is mandatory to program address range and valid permissions in pmpcfg and
pmpaddr registers (refer Register Summary) for any valid access to pass through in user-mode. However, it is not
required for machine-mode as PMP permits all accesses to go through by deafult. In cases where PMP checks
are also required in machine-mode, software can set the lock bit of required PMP entry to enable permission
checks on it. Once lock bit is set, it can only be cleared through CPU reset.
When any instruction is being fetched from memory region without execute permissions, exception is generated
at processor level and exception cause is set as instruction access fault in mcause CSR. Similarly, any load/store
access without valid read/write permissions, will result in exception generation with mcause updated as load
access and store access fault respectively. In case of load/store access faults, violating address is captured in
mtval CSR.
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1.8.4 Register Summary
Below is a list of PMP CSRs supported by the CPU. These are only accessible from machine-mode.
The abbreviations given in Column Access are explained in Section Access Types for Registers.
Name Description Address Access
pmpcfg0 Physical memory protection configuration. 0x3A0 R/W
pmpcfg1 Physical memory protection configuration. 0x3A1 R/W
pmpcfg2 Physical memory protection configuration. 0x3A2 R/W
pmpcfg3 Physical memory protection configuration. 0x3A3 R/W
pmpaddr0 Physical memory protection address register. 0x3B0 R/W
pmpaddr1 Physical memory protection address register. 0x3B1 R/W
pmpaddr2 Physical memory protection address register. 0x3B2 R/W
pmpaddr3 Physical memory protection address register. 0x3B3 R/W
pmpaddr4 Physical memory protection address register. 0x3B4 R/W
pmpaddr5 Physical memory protection address register. 0x3B5 R/W
pmpaddr6 Physical memory protection address register. 0x3B6 R/W
pmpaddr7 Physical memory protection address register. 0x3B7 R/W
pmpaddr8 Physical memory protection address register. 0x3B8 R/W
pmpaddr9 Physical memory protection address register. 0x3B9 R/W
pmpaddr10 Physical memory protection address register. 0x3BA R/W
pmpaddr11 Physical memory protection address register. 0x3BB R/W
pmpaddr12 Physical memory protection address register. 0x3BC R/W
pmpaddr13 Physical memory protection address register. 0x3BD R/W
pmpaddr14 Physical memory protection address register. 0x3BE R/W
pmpaddr15 Physical memory protection address register. 0x3BF R/W
1.8.5 Register Description
PMP unit implements all pmpcfg0-3 and pmpaddr0-15 CSRs as defined in RISCV Instruction Set Manual
Volume II: Privileged Architecture, Version 1.10.
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2 GDMA Controller (GDMA)
2.1 Overview
General Direct Memory Access (GDMA) is a feature that allows peripheral-to-memory, memory-to-peripheral, and
memory-to-memory data transfer at a high speed. The CPU is not involved in the GDMA transfer, and therefore it
becomes more efficient with less workload.
The GDMA controller in ESP32-C3 has six independent channels, i.e. three transmit channels and three receive
channels. These six channels are shared by peripherals with GDMA feature, namely SPI2, UHCI0
(UART0/UART1), I2S, AES, SHA, and ADC. Users can assign the six channels to any of these peripherals.
UART0 and UART1 use UHCI0 together.
The GDMA controller uses fixed-priority and round-robin channel arbitration schemes to manage peripherals’
needs for bandwidth.
Figure 21. Modules with GDMA Feature and GDMA Channels
2.2 Features
The GDMA controller has the following features:
• AHB bus architecture
• Programmable length of data to be transferred in bytes
• Linked list of descriptors
• INCR burst transfer when accessing internal RAM
• Access to an address space of 384 KB at most in internal RAM
• Three transmit channels and three receive channels
• Software-configurable selection of peripheral requesting its service
• Fixed channel priority and round-robin channel arbitration
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2.3 Architecture
In ESP32-C3, all modules that need high-speed data transfer support GDMA. The GDMA controller and CPU
data bus have access to the same address space in internal RAM. Figure 2-2 shows the basic architecture of the
GDMA engine.
Figure 22. GDMA Engine Architecture
The GDMA controller has six independent channels, i.e. three transmit channels and three receive channels.
Every channel can be connected to different peripherals. In other words, channels are general-purpose, shared
by peripherals.
The GDMA engine reads data from or writes data to internal RAM via the AHB_BUS. Before this, the GDMA
controller uses fixed-priority arbitration scheme for channels requesting read or write access. For available
address range of Internal RAM, please see Chapter 3 System and Memory.
Software can use the GDMA engine through linked lists. These linked lists, stored in internal RAM, consist of
outlinkn and inlinkn, where n indicates the channel number (ranging from 0 to 2). The GDMA controller reads an
outlinkn (i.e. a linked list of transmit descriptors) from internal RAM and transmits data in corresponding RAM
according to the outlinkn, or reads an inlinkn (i.e. a linked list of receive descriptors) and stores received data into
specific address space in RAM according to the inlinkn.
2.4 Functional Description
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2.4.1 Linked List
Figure 23. Structure of a Linked List
Figure 2-3 shows the structure of a linked list. An outlink and an inlink have the same structure. A linked list is
formed by one or more descriptors, and each descriptor consists of three words. Linked lists should be in
internal RAM for the GDMA engine to be able to use them. The meaning of each field is as follows:
• Owner (DW0) [31]: Specifies who is allowed to access the buffer that this descriptor points to.
1’b0: CPU can access the buffer;
1’b1: The GDMA controller can access the buffer.
When the GDMA controller stops using the buffer, this bit in a receive descriptor is automatically cleared by
hardware, and this bit in a transmit descriptor is automatically cleared by hardware only if
GDMA_OUT_AUTO_WRBACK_CHn is set to 1. Software can disable automatic clearing by hardware by
setting GDMA_OUT_LOOP_TEST_CHn or GDMA_IN_LOOP_TEST_CHn bit. When software loads a linked
list, this bit should be set to 1.
Note: GDMA_OUT is the prefix of transmit channel registers, and GDMA_IN is the prefix of receive channel
registers.
• suc_eof (DW0) [30]: Specifies whether this descriptor is the last descriptor in the list.
1’b0: This descriptor is not the last one;
1’b1: This descriptor is the last one.
Software clears suc_eof bit in receive descriptors. When a frame or packet has been received, this bit in
the last receive descriptor is set by hardware, and this bit in the last transmit descriptor is set by software.
• Reserved (DW0) [29]: Reserved. Value of this bit does not matter.
• err_eof (DW0) [28]: Specifies whether the received data has errors.
This bit is used only when UHCI0 uses GDMA to receive data. When an error is detected in the received
frame or packet, this bit in the receive descriptor is set to 1 by hardware.
• Reserved (DW0) [27:24]: Reserved.
• Length (DW0) [23:12]: Specifies the number of valid bytes in the buffer that this descriptor points to. This
field in a transmit descriptor is written by software and indicates how many bytes can be read from the
buffer; this field in a receive descriptor is written by hardware automatically and indicates how many valid
bytes have been stored into the buffer.
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• Size (DW0) [11:0]: Specifies the size of the buffer that this descriptor points to.
• Buffer address pointer (DW1): Address of the buffer. This field can only point to internal RAM.
• Next descriptor address (DW2): Address of the next descriptor. If the current descriptor is the last one
(suc_eof = 1), this value is 0. This field can only point to internal RAM.
If the length of data received is smaller than the size of the buffer, the GDMA controller will not use available
space of the buffer in the next transaction.
2.4.2 PeripheraltoMemory and MemorytoPeripheral Data Transfer
The GDMA controller can transfer data from memory to peripheral (transmit) and from peripheral to memory
(receive). A transmit channel transfers data in the specified memory location to a peripheral’s transmitter via an
outlinkn, whereas a receive channel transfers data received by a peripheral to the specified memory location via
an inlinkn.
Every transmit and receive channel can be connected to any peripheral with GDMA feature. Table 2-1 illustrates
how to select the peripheral to be connected via registers. When a channel is connected to a peripheral, the rest
channels can not be connected to that peripheral.
Table 21. Selecting Peripherals via Register Configuration
GDMA_PERI_IN_SEL_CHn
GDMA_PERI_OUT_SEL_CHn
0 SPI2
1 Reserved
2 UHCI0
3 I2S
4 Reserved
5 Reserved
6 AES
7 SHA
8 ADC
9 ~ 63 Invalid
Peripheral
2.4.3 MemorytoMemory Data Transfer
The GDMA controller also allows memory-to-memory data transfer. Such data transfer can be enabled by setting
GDMA_MEM_TRANS_EN_CHn, which connects the output of transmit channel n to the input of receive channel
n. Note that a transmit channel is only connected to the receive channel with the same number (n).
2.4.4 Enabling GDMA
Software uses the GDMA controller through linked lists. When the GDMA controller receives data, software loads
an inlink, configures GDMA_INLINK_ADDR_CHn field with address of the first receive descriptor, and sets
GDMA_INLINK_START_CHn bit to enable GDMA. When the GDMA controller transmits data, software loads an
outlink, prepares data to be transmitted, configures GDMA_OUTLINK_ADDR_CHn field with address of the first
transmit descriptor, and sets GDMA_OUTLINK_START_CHn bit to enable GDMA. GDMA_INLINK_START_CHn
bit and GDMA_OUTLINK_START_CHn bit are cleared automatically by hardware.
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In some cases, you may want to append more descriptors to a DMA transfer that is already started. Naively, it
would seem to be possible to do this by clearing the EOF bit of the final descriptor in the existing list and setting
its next descriptor address pointer field (DW2) to the first descriptor of the to-be-added list. However, this
strategy fails if the existing DMA transfer is almost or entirely finished. Instead, the GDMA engine has specialized
logic to make sure a DMA transfer can be continued or restarted: if it is still ongoing, it will make sure to take the
appended descriptors into account; if the transfer has already finished, it will restart with the new descriptors.
This is implemented in the Restart function.
When using the Restart function, software needs to rewrite address of the first descriptor in the new list to DW2
of the last descriptor in the loaded list, and set GDMA_INLINK_RESTART_CHn bit or
GDMA_OUTLINK_RESTART_CHn bit (these two bits are cleared automatically by hardware). As shown in Figure
2-4, by doing so hardware can obtain the address of the first descriptor in the new list when reading the last
descriptor in the loaded list, and then read the new list.
Figure 24. Relationship among Linked Lists
2.4.5 Linked List Reading Process
Once configured and enabled by software, the GDMA controller starts to read the linked list from internal RAM.
The GDMA performs checks on descriptors in the linked list. Only if descriptors pass the checks, will the
corresponding GDMA channel transfer data. If the descriptors fail any of the checks, hardware will trigger
descriptor error interrupt (either GDMA_IN_DSCR_ERR_CHn_INT or GDMA_OUT_DSCR_ERR_CHn_INT), and
the channel will halt.
The checks performed on descriptors are:
• Owner bit check when GDMA_IN_CHECK_OWNER_CHn or GDMA_OUT_CHECK_OWNER_CHn is set to
1. If the owner bit is 0, the buffer is accessed by the CPU. In this case, the owner bit fails the check. The
owner bit will not be checked if GDMA_IN_CHECK_OWNER_CHn or GDMA_OUT_CHECK_OWNER_CHn
is 0;
• Buffer address pointer (DW1) check. If the buffer address pointer points to 0x3FC80000 ~ 0x3FCDFFFF
(please refer to Section 2.4.7), it passes the check.
After software detects a descriptor error interrupt, it must reset the corresponding channel, and enable GDMA by
setting GDMA_OUTLINK_START_CHn or GDMA_INLINK_START_CHn bit.
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Note: The third word (DW2) in a descriptor can only point to a location in internal RAM, given that the third word
points to the next descriptor to use and that all descriptors must be in internal memory.
2.4.6 EOF
The GDMA controller uses EOF (end of frame) flags to indicate the end of data frame or packet
transmission.
Before the GDMA controller transmits data, GDMA_OUT_TOTAL_EOF_CHn_INT_ENA bit should be set to enable
GDMA_OUT_TOTAL_EOF_CHn_INT interrupt. If data in the buffer pointed by the last descriptor (with EOF) has
been transmitted, a GDMA_OUT_TOTAL_EOF_CHn_INT interrupt is generated.
Before the GDMA controller receives data, GDMA_IN_SUC_EOF_CHn_INT_ENA bit should be set to enable
GDMA_IN_SUC_EOF_CHn_INT interrupt. If a data frame or packet has been received successfully, a
GDMA_IN_SUC_EOF_CHn_INT interrupt is generated. In addition, when GDMA channel is connected to UHCI0,
the GDMA controller also supports GDMA_IN_ERR_CHn_EOF_INT interrupt. This interrupt is enabled by setting
GDMA_IN_ERR_EOF_CHn_INT_ENA bit, and it indicates that a data frame or packet has been received with
errors.
When detecting a GDMA_OUT_TOTAL_EOF_CHn_INT or a GDMA_IN_SUC_EOF_CHn_INT interrupt, software
can record the value of GDMA_OUT_EOF_DES_ADDR_CHn or GDMA_IN_SUC_EOF_DES_ADDR_CHn field, i.e.
address of the last descriptor. Therefore, software can tell which descriptors have been used and reclaim
them.
Note: In this chapter, EOF of transmit descriptors refers to suc_eof, while EOF of receive descriptors refers to
both suc_eof and err_eof.
2.4.7 Accessing Internal RAM
Any transmit and receive channels of GDMA can access 0x3FC80000 ~ 0x3FCDFFFF in internal RAM. To
improve data transfer efficiency, GDMA can send data in burst mode, which is disabled by default. This mode is
enabled for receive channels by setting GDMA_IN_DATA_BURST_EN_CHn, and enabled for transmit channels
by setting GDMA_OUT_DATA_BURST_EN_CHn.
Table 22. Descriptor Field Alignment Requirements
Inlink/Outlink Burst Mode Size Length Buffer Address Pointer
Inlink
Outlink
0 — — —
1 Word-aligned — Word-aligned
0 — — —
1 — — —
Table 2-2 lists the requirements for descriptor field alignment when accessing internal RAM.
When burst mode is disabled, size, length, and buffer address pointer in both transmit and receive descriptors do
not need to be word-aligned. That is to say, GDMA can read data of specified length (1 ~ 4095 bytes) from any
start addresses in the accessible address range, or write received data of the specified length (1 ~ 4095 bytes) to
any contiguous addresses in the accessible address range.
When burst mode is enabled, size, length, and buffer address pointer in transmit descriptors are also not
necessarily word-aligned. However, size and buffer address pointer in receive descriptors except length should
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be word-aligned.
2.4.8 Arbitration
To ensure timely response to peripherals running at a high speed with low latency (such as SPI), the GDMA
controller implements a fixed-priority channel arbitration scheme. That is to say, each channel can be assigned a
priority from 0 ~ 9. The larger the number, the higher the priority, and the more timely the response. When several
channels are assigned the same priority, the GDMA controller adopts a round-robin arbitration scheme.
Please note that the overall throughput of peripherals with GDMA feature cannot exceed the maximum
bandwidth of the GDMA, so that requests from low-priority peripherals can be responded to.
2.5 GDMA Interrupts
• GDMA_OUT_TOTAL_EOF_CHn_INT: Triggered when all data corresponding to a linked list (including
multiple descriptors) has been sent via transmit channel n.
• GDMA_IN_DSCR_EMPTY_CHn_INT: Triggered when the size of the buffer pointed by receive descriptors is
smaller than the length of data to be received via receive channel n.
• GDMA_OUT_DSCR_ERR_CHn_INT: Triggered when an error is detected in a transmit descriptor on
transmit channel n.
• GDMA_IN_DSCR_ERR_CHn_INT: Triggered when an error is detected in a receive descriptor on receive
channel n.
• GDMA_OUT_EOF_CHn_INT: Triggered when EOF in a transmit descriptor is 1 and data corresponding to
this descriptor has been sent via transmit channel n. If GDMA_OUT_EOF_MODE_CHn is 0, this interrupt
will be triggered when the last byte of data corresponding to this descriptor enters GDMA’s transmit
channel; if GDMA_OUT_EOF_MODE_CHn is 1, this interrupt is triggered when the last byte of data is taken
from GDMA’s transmit channel.
• GDMA_OUT_DONE_CHn_INT: Triggered when all data corresponding to a transmit descriptor has been
sent via transmit channel n.
• GDMA_IN_ERR_EOF_CHn_INT: Triggered when an error is detected in the data frame or packet received
via receive channel n. This interrupt is used only for UHCI0 peripheral (UART0 or UART1).
• GDMA_IN_SUC_EOF_CHn_INT: Triggered when the suc_eof bit in a receive descriptor is 1 and the data
corresponding to this receive descriptor has been received (i.e. when the data frame or packet
corresponding to an inlink has beeen received) via receive channel n.
• GDMA_IN_DONE_CHn_INT: Triggered when all data corresponding to a receive descriptor has been
received via receive channel n.
2.6 Programming Procedures
2.6.1 Programming Procedure for GDMA Clock and Reset
GDMA’s clock and reset should be configured as follows:
1. Set SYSTEM_DMA_CLK_EN to enable GDMA’s clock;
2. Clear SYSTEM_DMA_RST to reset GDMA.
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2.6.2 Programming Procedures for GDMA’s Transmit Channel
To transmit data, GDMA’s transmit channel should be configured by software as follows:
1. Set GDMA_OUT_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s transmit channel
and FIFO pointer;
2. Load an outlink, and configure GDMA_OUTLINK_ADDR_CHn with address of the first transmit descriptor;
3. Configure GDMA_PERI_OUT_SEL_CHn with the value corresponding to the peripheral to be connected, as
shown in Table 2-1;
4. Set GDMA_OUTLINK_START_CHn to enable GDMA’s transmit channel for data transfer;
5. Configure and enable the corresponding peripheral (SPI2, UHCI0 (UART0 or UART1), I2S, AES, SHA, and
ADC). See details in individual chapters of these peripherals;
6. Wait for GDMA_OUT_EOF_CHn_INT interrupt, which indicates the completion of data transfer.
2.6.3 Programming Procedures for GDMA’s Receive Channel
To receive data, GDMA’s receive channel should be configured by software as follows:
1. Set GDMA_IN_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s receive channel and
FIFO pointer;
2. Load an inlink, and configure GDMA_INLINK_ADDR_CHn with address of the first receive descriptor;
3. Configure GDMA_PERI_IN_SEL_CHn with the value corresponding to the peripheral to be connected, as
shown in Table 2-1;
4. Set GDMA_INLINK_START_CHn to enable GDMA’s receive channel for data transfer;
5. Configure and enable the corresponding peripheral (SPI2, UHCI0 (UART0 or UART1), I2S, AES, SHA, and
ADC). See details in individual chapters of these peripherals;
6. Wait for GDMA_IN_SUC_EOF_CHn_INT interrupt, which indicates that a data frame or packet has been
received.
2.6.4 Programming Procedures for MemorytoMemory Transfer
To transfer data from one memory location to another, GDMA should be configured by software as follows:
1. Set GDMA_OUT_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s transmit channel
and FIFO pointer;
2. Set GDMA_IN_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s receive channel and
FIFO pointer;
3. Load an outlink, and configure GDMA_OUTLINK_ADDR_CHn with address of the first transmit descriptor;
4. Load an inlink, and configure GDMA_INLINK_ADDR_CHn with address of the first receive descriptor;
5. Set GDMA_MEM_TRANS_EN_CHn to enable memory-to-memory transfer;
6. Set GDMA_OUTLINK_START_CHn to enable GDMA’s transmit channel for data transfer;
7. Set GDMA_INLINK_START_CHn to enable GDMA’s receive channel for data transfer;
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8. Wait for GDMA_IN_SUC_EOF_CHn_INT interrupt, which indicates that a data transaction has been
completed.
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2.7 Register Summary
The addresses in this section are relative to GDMA base address provided in Table 3-3 in Chapter 3 System and
Memory.
The abbreviations given in Column Access are explained in Section Access Types for Registers.
Name Description Address Access
Interrupt Registers
GDMA_INT_RAW_CH0_REG Raw status interrupt of RX channel 0 0x0000 R/WTC/SS
GDMA_INT_ST_CH0_REG Masked interrupt of RX channel 0 0x0004 RO
GDMA_INT_ENA_CH0_REG Interrupt enable bits of RX channel 0 0x0008 R/W
GDMA_INT_CLR_CH0_REG Interrupt clear bits of RX channel 0 0x000C WT
GDMA_INT_RAW_CH1_REG Raw status interrupt of RX channel 1 0x0010 R/WTC/SS
GDMA_INT_ST_CH1_REG Masked interrupt of RX channel 1 0x0014 RO
GDMA_INT_ENA_CH1_REG Interrupt enable bits of RX channel 1 0x0018 R/W
GDMA_INT_CLR_CH1_REG Interrupt clear bits of RX channel 1 0x001C WT
GDMA_INT_RAW_CH2_REG Raw status interrupt of RX channel 2 0x0020 R/WTC/SS
GDMA_INT_ST_CH2_REG Masked interrupt of RX channel 2 0x0024 RO
GDMA_INT_ENA_CH2_REG Interrupt enable bits of RX channel 2 0x0028 R/W
GDMA_INT_CLR_CH2_REG Interrupt clear bits of RX channel 2 0x002C WT
Configuration Register
GDMA_MISC_CONF_REG Miscellaneous register 0x0044 R/W
Version Registers
GDMA_DATE_REG Version control register 0x0048 R/W
Configuration Registers
GDMA_IN_CONF0_CH0_REG Configuration register 0 of RX channel 0 0x0070 R/W
GDMA_IN_CONF1_CH0_REG Configuration register 1 of RX channel 0 0x0074 R/W
GDMA_IN_POP_CH0_REG Pop control register of RX channel 0 0x007C varies
GDMA_IN_LINK_CH0_REG
GDMA_OUT_CONF0_CH0_REG Configuration register 0 of TX channel 0 0x00D0 R/W
GDMA_OUT_CONF1_CH0_REG Configuration register 1 of TX channel 0 0x00D4 R/W
GDMA_OUT_PUSH_CH0_REG Push control register of TX channel 0 0x00DC varies
GDMA_OUT_LINK_CH0_REG
GDMA_IN_CONF0_CH1_REG Configuration register 0 of RX channel 1 0x0130 R/W
GDMA_IN_CONF1_CH1_REG Configuration register 1 of RX channel 1 0x0134 R/W
GDMA_IN_POP_CH1_REG Pop control register of RX channel 1 0x013C varies
GDMA_IN_LINK_CH1_REG
GDMA_OUT_CONF0_CH1_REG Configuration register 0 of TX channel 1 0x0190 R/W
GDMA_OUT_CONF1_CH1_REG Configuration register 1 of TX channel 1 0x0194 R/W
GDMA_OUT_PUSH_CH1_REG Push control register of TX channel 1 0x019C varies
GDMA_OUT_LINK_CH1_REG
Link descriptor configuration and control
register of RX channel 0
Link descriptor configuration and control
register of TX channel 0
Link descriptor configuration and control
register of RX channel 1
Link descriptor configuration and control
register of TX channel 1
0x0080 varies
0x00E0 varies
0x0140 varies
0x01A0 varies
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Name Description Address Access
GDMA_IN_CONF0_CH2_REG Configuration register 0 of RX channel 2 0x01F0 R/W
GDMA_IN_CONF1_CH2_REG Configuration register 1 of RX channel 2 0x01F4 R/W
GDMA_IN_POP_CH2_REG Pop control register of RX channel 2 0x01FC varies
GDMA_IN_LINK_CH2_REG
Link descriptor configuration and control
register of RX channel 2
0x0200 varies
GDMA_OUT_CONF0_CH2_REG Configuration register 0 of TX channel 2 0x0250 R/W
GDMA_OUT_CONF1_CH2_REG Configuration register 1 of TX channel 2 0x0254 R/W
GDMA_OUT_PUSH_CH2_REG Push control register of TX channel 2 0x025C varies
GDMA_OUT_LINK_CH2_REG
Link descriptor configuration and control
register of TX channel 2
0x0260 varies
Status Registers
GDMA_INFIFO_STATUS_CH0_REG RX FIFO status of RX channel 0 0x0078 RO
GDMA_IN_STATE_CH0_REG Receive status of RX channel 0 0x0084 RO
GDMA_IN_SUC_EOF_DES_ADDR_CH0
_REG
GDMA_IN_ERR_EOF_DES_ADDR_CH0
_REG
GDMA_IN_DSCR_CH0_REG
GDMA_IN_DSCR_BF0_CH0_REG
GDMA_IN_DSCR_BF1_CH0_REG
Inlink descriptor address when EOF
occurs of RX channel 0
Inlink descriptor address when errors
occur of RX channel 0
Current inlink descriptor address of RX
channel 0
The last inlink descriptor address of RX
channel 0
The second-to-last inlink descriptor
address of RX channel 0
0x0088 RO
0x008C RO
0x0090 RO
0x0094 RO
0x0098 RO
GDMA_OUTFIFO_STATUS_CH0_REG TX FIFO status of TX channel 0 0x00D8 RO
GDMA_OUT_STATE_CH0_REG Transmit status of TX channel 0 0x00E4 RO
GDMA_OUT_EOF_DES_ADDR_CH0_REG
GDMA_OUT_EOF_BFR_DES_ADDR_CH0
_REG
GDMA_OUT_DSCR_CH0_REG
GDMA_OUT_DSCR_BF0_CH0_REG
GDMA_OUT_DSCR_BF1_CH0_REG
Outlink descriptor address when EOF
occurs of TX channel 0
The last outlink descriptor address when
EOF occurs of TX channel 0
Current inlink descriptor address of TX
channel 0
The last inlink descriptor address of TX
channel 0
The second-to-last inlink descriptor
address of TX channel 0
0x00E8 RO
0x00EC RO
0x00F0 RO
0x00F4 RO
0x00F8 RO
GDMA_INFIFO_STATUS_CH1_REG RX FIFO status of RX channel 1 0x0138 RO
GDMA_IN_STATE_CH1_REG Receive status of RX channel 1 0x0144 RO
GDMA_IN_SUC_EOF_DES_ADDR_CH1
_REG
GDMA_IN_ERR_EOF_DES_ADDR_CH1
_REG
GDMA_IN_DSCR_CH1_REG
Inlink descriptor address when EOF
occurs of RX channel 1
Inlink descriptor address when errors
occur of RX channel 1
Current inlink descriptor address of RX
channel 1
0x0148 RO
0x014C RO
0x0150 RO
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Name Description Address Access
GDMA_IN_DSCR_BF0_CH1_REG
GDMA_IN_DSCR_BF1_CH1_REG
The last inlink descriptor address of RX
channel 1
The second-to-last inlink descriptor
address of RX channel 1
0x0154 RO
0x0158 RO
GDMA_OUTFIFO_STATUS_CH1_REG TX FIFO status of TX channel 1 0x0198 RO
GDMA_OUT_STATE_CH1_REG Transmit status of TX channel 1 0x01A4 RO
GDMA_OUT_EOF_DES_ADDR_CH1_REG
GDMA_OUT_EOF_BFR_DES_ADDR_CH1
_REG
GDMA_OUT_DSCR_CH1_REG
GDMA_OUT_DSCR_BF0_CH1_REG
GDMA_OUT_DSCR_BF1_CH1_REG
Outlink descriptor address when EOF
occurs of TX channel 1
The last outlink descriptor address when
EOF occurs of TX channel 1
Current inlink descriptor address of TX
channel 1
The last inlink descriptor address of TX
channel 1
The second-to-last inlink descriptor
address of TX channel 1
0x01A8 RO
0x01AC RO
0x01B0 RO
0x01B4 RO
0x01B8 RO
GDMA_INFIFO_STATUS_CH2_REG RX FIFO status of RX channel 2 0x01F8 RO
GDMA_IN_STATE_CH2_REG Receive status of RX channel 2 0x0204 RO
GDMA_IN_SUC_EOF_DES_ADDR_CH2
_REG
GDMA_IN_ERR_EOF_DES_ADDR_CH2
_REG
GDMA_IN_DSCR_CH2_REG
GDMA_IN_DSCR_BF0_CH2_REG
GDMA_IN_DSCR_BF1_CH2_REG
Inlink descriptor address when EOF
occurs of RX channel 2
Inlink descriptor address when errors
occur of RX channel 2
Current inlink descriptor address of RX
channel 2
The last inlink descriptor address of RX
channel 2
The second-to-last inlink descriptor
address of RX channel 2
0x0208 RO
0x020C RO
0x0210 RO
0x0214 RO
0x0218 RO
GDMA_OUTFIFO_STATUS_CH2_REG TX FIFO status of TX channel 2 0x0258 RO
GDMA_OUT_STATE_CH2_REG Transmit status of TX channel 2 0x0264 RO
GDMA_OUT_EOF_DES_ADDR_CH2_REG
GDMA_OUT_EOF_BFR_DES_ADDR_CH2
_REG
GDMA_OUT_DSCR_CH2_REG
GDMA_OUT_DSCR_BF0_CH2_REG
GDMA_OUT_DSCR_BF1_CH2_REG
Outlink descriptor address when EOF
occurs of TX channel 2
The last outlink descriptor address when
EOF occurs of TX channel 2
Current inlink descriptor address of TX
channel 2
The last inlink descriptor address of TX
channel 2
The second-to-last inlink descriptor
address of TX channel 2
0x0268 RO
0x026C RO
0x0270 RO
0x0274 RO
0x0278 RO
Priority Registers
GDMA_IN_PRI_CH0_REG Priority register of RX channel 0 0x009C R/W
GDMA_OUT_PRI_CH0_REG Priority register of TX channel 0 0x00FC R/W
GDMA_IN_PRI_CH1_REG Priority register of RX channel 1 0x015C R/W
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Name Description Address Access
GDMA_OUT_PRI_CH1_REG Priority register of TX channel 1 0x01BC R/W
GDMA_IN_PRI_CH2_REG Priority register of RX channel 2 0x021C R/W
GDMA_OUT_PRI_CH2_REG Priority register of TX channel 2 0x027C R/W
Peripheral Select Registers
GDMA_IN_PERI_SEL_CH0_REG Peripheral selection of RX channel 0 0x00A0 R/W
GDMA_OUT_PERI_SEL_CH0_REG Peripheral selection of TX channel 0 0x0100 R/W
GDMA_IN_PERI_SEL_CH1_REG Peripheral selection of RX channel 1 0x0160 R/W
GDMA_OUT_PERI_SEL_CH1_REG Peripheral selection of TX channel 1 0x01C0 R/W
GDMA_IN_PERI_SEL_CH2_REG Peripheral selection of RX channel 2 0x0220 R/W
GDMA_OUT_PERI_SEL_CH2_REG Peripheral selection of TX channel 2 0x0280 R/W
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2.8 Registers
The addresses in this section are relative to GDMA base address provided in Table 3-3 in Chapter 3 System and
Memory.
Register 2.1. GDMA_INT_RAW_CHn_REG (n: 02) (0x0000+16*n)
(reserved)
31 13
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GDMA_OUTFIFO_OVF_CH0_INT_RAW
GDMA_INFIFO_UDF_CH0_INT_RAW
GDMA_OUTFIFO_UDF_CH0_INT_RAW
12
11
0
GDMA_INFIFO_OVF_CH0_INT_RAW
10
9
0
0
0
GDMA_OUT_DSCR_ERR_CH0_INT_RAW
GDMA_OUT_TOTAL_EOF_CH0_INT_RAW
8
0
GDMA_IN_DSCR_ERR_CH0_INT_RAW
GDMA_IN_DSCR_EMPTY_CH0_INT_RAW
7
6
5
0
0
0
GDMA_IN_ERR_EOF_CH0_INT_RAW
GDMA_OUT_EOF_CH0_INT_RAW
GDMA_OUT_DONE_CH0_INT_RAW
4
3
2
0
0
0
GDMA_IN_SUC_EOF_CH0_INT_RAW
1
0
GDMA_IN_DONE_CHn_INT_RAW The raw interrupt bit turns to high level when the last data pointed
by one receive descriptor has been received for RX channel 0. (R/WTC/SS)
GDMA_IN_SUC_EOF_CHn_INT_RAW The raw interrupt bit turns to high level for RX channel 0 when
the last data pointed by one receive descriptor has been received and the suc_eof bit in this de-
scriptor is 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one
receive descriptor has been received and no data error is detected for RX channel 0. (R/WTC/SS)
GDMA_IN_ERR_EOF_CHn_INT_RAW The raw interrupt bit turns to high level when data error is
detected only in the case that the peripheral is UHCI0 for RX channel 0. For other peripherals, this
raw interrupt is reserved. (R/WTC/SS)
GDMA_OUT_DONE_CHn_INT_RAW The raw interrupt bit turns to high level when the last data
pointed by one transmit descriptor has been transmitted to peripherals for TX channel 0.
(R/WTC/SS)
GDMA_OUT_EOF_CHn_INT_RAW The raw interrupt bit turns to high level when the last data pointed
by one transmit descriptor has been read from memory for TX channel 0. (R/WTC/SS)
GDMA_IN_DONE_CH0_INT_RAW
0
0
Reset
GDMA_IN_DSCR_ERR_CHn_INT_RAW The raw interrupt bit turns to high level when detecting re-
ceive descriptor error, including owner error, the second and third word error of receive descriptor
for RX channel 0. (R/WTC/SS)
GDMA_OUT_DSCR_ERR_CHn_INT_RAW The raw interrupt bit turns to high level when detecting
transmit descriptor error, including owner error, the second and third word error of transmit de-
scriptor for TX channel 0. (R/WTC/SS)
Continued on the next page...
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Register 2.1. GDMA_INT_RAW_CHn_REG (n: 02) (0x0000+16*n)
Continued from the previous page...
GDMA_IN_DSCR_EMPTY_CHn_INT_RAW The raw interrupt bit turns to high level when RX buffer
pointed by inlink is full and receiving data is not completed, but there is no more inlink for RX
channel 0. (R/WTC/SS)
GDMA_OUT_TOTAL_EOF_CHn_INT_RAW The raw interrupt bit turns to high level when data cor-
responding a outlink (includes one descriptor or few descriptors) is transmitted out for TX channel
0. (R/WTC/SS)
GDMA_INFIFO_OVF_CHn_INT_RAW This raw interrupt bit turns to high level when level 1 FIFO of
RX channel 0 is overflow. (R/WTC/SS)
GDMA_INFIFO_UDF_CHn_INT_RAW This raw interrupt bit turns to high level when level 1 FIFO of
RX channel 0 is underflow. (R/WTC/SS)
GDMA_OUTFIFO_OVF_CHn_INT_RAW This raw interrupt bit turns to high level when level 1 FIFO
of TX channel 0 is overflow. (R/WTC/SS)
GDMA_OUTFIFO_UDF_CHn_INT_RAW This raw interrupt bit turns to high level when level 1 FIFO
of TX channel 0 is underflow. (R/WTC/SS)
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Register 2.2. GDMA_INT_ST_CHn_REG (n: 02) (0x0004+16*n)
(reserved)
31 13
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GDMA_OUTFIFO_UDF_CH0_INT_ST
12
11
0
GDMA_INFIFO_OVF_CH0_INT_ST
GDMA_OUTFIFO_OVF_CH0_INT_ST
10
0
GDMA_OUT_TOTAL_EOF_CH0_INT_ST
GDMA_INFIFO_UDF_CH0_INT_ST
9
8
0
0
0
GDMA_IN_DSCR_ERR_CH0_INT_ST
GDMA_IN_DSCR_EMPTY_CH0_INT_ST
7
0
GDMA_OUT_EOF_CH0_INT_ST
GDMA_OUT_DSCR_ERR_CH0_INT_ST
6
0
GDMA_OUT_DONE_CH0_INT_ST
5
4
3
0
0
0
GDMA_IN_ERR_EOF_CH0_INT_ST
GDMA_IN_SUC_EOF_CH0_INT_ST
2
1
0
0
GDMA_IN_DONE_CHn_INT_ST The raw interrupt status bit for the GDMA_IN_DONE_CH_INT inter-
rupt. (RO)
GDMA_IN_SUC_EOF_CHn_INT_ST The raw interrupt status bit for the
GDMA_IN_SUC_EOF_CH_INT interrupt. (RO)
GDMA_IN_ERR_EOF_CHn_INT_ST The raw interrupt status bit for the
GDMA_IN_ERR_EOF_CH_INT interrupt. (RO)
GDMA_OUT_DONE_CHn_INT_ST The raw interrupt status bit for the GDMA_OUT_DONE_CH_INT
interrupt. (RO)
GDMA_OUT_EOF_CHn_INT_ST The raw interrupt status bit for the GDMA_OUT_EOF_CH_INT in-
terrupt. (RO)
GDMA_IN_DSCR_ERR_CHn_INT_ST The raw interrupt status bit for the
GDMA_IN_DSCR_ERR_CH_INT interrupt. (RO)
GDMA_OUT_DSCR_ERR_CHn_INT_ST The raw interrupt status bit for the
GDMA_OUT_DSCR_ERR_CH_INT interrupt. (RO)
GDMA_IN_DONE_CH0_INT_ST
0
0
Reset
GDMA_IN_DSCR_EMPTY_CHn_INT_ST The raw interrupt status bit for the
GDMA_IN_DSCR_EMPTY_CH_INT interrupt. (RO)
GDMA_OUT_TOTAL_EOF_CHn_INT_ST The raw interrupt status bit for the
GDMA_OUT_TOTAL_EOF_CH_INT interrupt. (RO)
GDMA_INFIFO_OVF_CHn_INT_ST The raw interrupt status bit for the
GDMA_INFIFO_OVF_L1_CH_INT interrupt. (RO)
GDMA_INFIFO_UDF_CHn_INT_ST The raw interrupt status bit for the
GDMA_INFIFO_UDF_L1_CH_INT interrupt. (RO)
GDMA_OUTFIFO_OVF_CHn_INT_ST The raw interrupt status bit for the
GDMA_OUTFIFO_OVF_L1_CH_INT interrupt. (RO)
GDMA_OUTFIFO_UDF_CHn_INT_ST The raw interrupt status bit for the
GDMA_OUTFIFO_UDF_L1_CH_INT interrupt. (RO)
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Register 2.3. GDMA_INT_ENA_CHn_REG (n: 02) (0x0008+16*n)
(reserved)
31 13
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GDMA_OUTFIFO_UDF_CH0_INT_ENA
12
11
0
GDMA_INFIFO_OVF_CH0_INT_ENA
GDMA_OUT_TOTAL_EOF_CH0_INT_ENA
GDMA_OUTFIFO_OVF_CH0_INT_ENA
GDMA_INFIFO_UDF_CH0_INT_ENA
10
0
0
GDMA_IN_DSCR_EMPTY_CH0_INT_ENA
9
8
7
0
0
0
GDMA_OUT_EOF_CH0_INT_ENA
GDMA_OUT_DSCR_ERR_CH0_INT_ENA
6
0
GDMA_OUT_DONE_CH0_INT_ENA
GDMA_IN_DSCR_ERR_CH0_INT_ENA
5
4
3
0
0
0
GDMA_IN_ERR_EOF_CH0_INT_ENA
GDMA_IN_SUC_EOF_CH0_INT_ENA
2
1
0
0
GDMA_IN_DONE_CHn_INT_ENA The interrupt enable bit for the GDMA_IN_DONE_CH_INT inter-
rupt. (R/W)
GDMA_IN_SUC_EOF_CHn_INT_ENA The interrupt enable bit for the GDMA_IN_SUC_EOF_CH_INT
interrupt. (R/W)
GDMA_IN_ERR_EOF_CHn_INT_ENA The interrupt enable bit for the GDMA_IN_ERR_EOF_CH_INT
interrupt. (R/W)
GDMA_OUT_DONE_CHn_INT_ENA The interrupt enable bit for the GDMA_OUT_DONE_CH_INT in-
terrupt. (R/W)
GDMA_OUT_EOF_CHn_INT_ENA The interrupt enable bit for the GDMA_OUT_EOF_CH_INT inter-
rupt. (R/W)
GDMA_IN_DSCR_ERR_CHn_INT_ENA The interrupt enable bit for the
GDMA_IN_DSCR_ERR_CH_INT interrupt. (R/W)
GDMA_OUT_DSCR_ERR_CHn_INT_ENA The interrupt enable bit for the
GDMA_OUT_DSCR_ERR_CH_INT interrupt. (R/W)
GDMA_IN_DONE_CH0_INT_ENA
0
0
Reset
GDMA_IN_DSCR_EMPTY_CHn_INT_ENA The interrupt enable bit for the
GDMA_IN_DSCR_EMPTY_CH_INT interrupt. (R/W)
GDMA_OUT_TOTAL_EOF_CHn_INT_ENA The interrupt enable bit for the
GDMA_OUT_TOTAL_EOF_CH_INT interrupt. (R/W)
GDMA_INFIFO_OVF_CHn_INT_ENA The interrupt enable bit for the
GDMA_INFIFO_OVF_L1_CH_INT interrupt. (R/W)
GDMA_INFIFO_UDF_CHn_INT_ENA The interrupt enable bit for the
GDMA_INFIFO_UDF_L1_CH_INT interrupt. (R/W)
GDMA_OUTFIFO_OVF_CHn_INT_ENA The interrupt enable bit for the
GDMA_OUTFIFO_OVF_L1_CH_INT interrupt. (R/W)
GDMA_OUTFIFO_UDF_CHn_INT_ENA The interrupt enable bit for the
GDMA_OUTFIFO_UDF_L1_CH_INT interrupt. (R/W)
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Register 2.4. GDMA_INT_CLR_CHn_REG (n: 02) (0x000C+16*n)
(reserved)
31 13
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GDMA_INFIFO_UDF_CH0_INT_CLR
GDMA_OUTFIFO_UDF_CH0_INT_CLR
12
11
0
GDMA_INFIFO_OVF_CH0_INT_CLR
GDMA_OUTFIFO_OVF_CH0_INT_CLR
10
9
0
0
0
GDMA_OUT_DSCR_ERR_CH0_INT_CLR
GDMA_OUT_TOTAL_EOF_CH0_INT_CLR
8
0
GDMA_IN_DSCR_ERR_CH0_INT_CLR
GDMA_IN_DSCR_EMPTY_CH0_INT_CLR
7
0
GDMA_OUT_EOF_CH0_INT_CLR
6
5
4
0
0
0
GDMA_IN_SUC_EOF_CH0_INT_CLR
GDMA_OUT_DONE_CH0_INT_CLR
GDMA_IN_ERR_EOF_CH0_INT_CLR
3
2
1
0
0
0
GDMA_IN_DONE_CHn_INT_CLR Set this bit to clear the GDMA_IN_DONE_CH_INT interrupt. (WT)
GDMA_IN_SUC_EOF_CHn_INT_CLR Set this bit to clear the GDMA_IN_SUC_EOF_CH_INT inter-
rupt. (WT)
GDMA_IN_ERR_EOF_CHn_INT_CLR Set this bit to clear the GDMA_IN_ERR_EOF_CH_INT inter-
rupt. (WT)
GDMA_OUT_DONE_CHn_INT_CLR Set this bit to clear the GDMA_OUT_DONE_CH_INT interrupt.
(WT)
GDMA_OUT_EOF_CHn_INT_CLR Set this bit to clear the GDMA_OUT_EOF_CH_INT interrupt. (WT)
GDMA_IN_DSCR_ERR_CHn_INT_CLR Set this bit to clear the GDMA_IN_DSCR_ERR_CH_INT in-
terrupt. (WT)
GDMA_OUT_DSCR_ERR_CHn_INT_CLR Set this bit to clear the GDMA_OUT_DSCR_ERR_CH_INT
interrupt. (WT)
GDMA_IN_DONE_CH0_INT_CLR
0
0
Reset
GDMA_IN_DSCR_EMPTY_CHn_INT_CLR Set this bit to clear the
GDMA_IN_DSCR_EMPTY_CH_INT interrupt. (WT)
GDMA_OUT_TOTAL_EOF_CHn_INT_CLR Set this bit to clear the
GDMA_OUT_TOTAL_EOF_CH_INT interrupt. (WT)
GDMA_INFIFO_OVF_CHn_INT_CLR Set this bit to clear the GDMA_INFIFO_OVF_L1_CH_INT inter-
rupt. (WT)
GDMA_INFIFO_UDF_CHn_INT_CLR Set this bit to clear the GDMA_INFIFO_UDF_L1_CH_INT inter-
rupt. (WT)
GDMA_OUTFIFO_OVF_CHn_INT_CLR Set this bit to clear the GDMA_OUTFIFO_OVF_L1_CH_INT
interrupt. (WT)
GDMA_OUTFIFO_UDF_CHn_INT_CLR Set this bit to clear the GDMA_OUTFIFO_UDF_L1_CH_INT
interrupt. (WT)
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Register 2.5. GDMA_MISC_CONF_REG (0x0044)
(reserved)
31 4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
GDMA_CLK_EN
GDMA_ARB_PRI_DIS
3
2
1
0
0
0
GDMA_AHBM_RST_INTER Set this bit, then clear this bit to reset the internal ahb FSM. (R/W)
GDMA_ARB_PRI_DIS Set this bit to disable priority arbitration function. (R/W)
GDMA_CLK_EN 0: Enable the clock only when application writes registers. 1: Force the clock on
for registers. (R/W)
Register 2.6. GDMA_DATE_REG (0x0048)
GDMA_DATE
31 0
0x2008250
GDMA_DATE This is the version control register. (R/W)
GDMA_AHBM_RST_INTER
0
0
Reset
Reset
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Register 2.7. GDMA_IN_CONF0_CHn_REG (n: 02) (0x0070+192*n)
(reserved)
31 5
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GDMA_MEM_TRANS_EN_CH0
GDMA_IN_DATA_BURST_EN_CH0
GDMA_INDSCR_BURST_EN_CH0
GDMA_IN_LOOP_TEST_CH0
4
3
2
1
0
0
0
0
GDMA_IN_RST_CHn This bit is used to reset GDMA channel 0 RX FSM and RX FIFO pointer. (R/W)
GDMA_IN_LOOP_TEST_CHn This bit is used to fill the owner bit of receive descriptor by hardware
of receive descriptor. (R/W)
GDMA_INDSCR_BURST_EN_CHn Set this bit to 1 to enable INCR burst transfer for RX channel 0
reading descriptor when accessing internal RAM. (R/W)
GDMA_IN_DATA_BURST_EN_CHn Set this bit to 1 to enable INCR burst transfer for RX channel 0
receiving data when accessing internal RAM. (R/W)
GDMA_MEM_TRANS_EN_CHn Set this bit 1 to enable automatic transmitting data from memory to
memory via GDMA. (R/W)
Register 2.8. GDMA_IN_CONF1_CHn_REG (n: 02) (0x0074+192*n)
GDMA_IN_RST_CH0
0
0
Reset
(reserved)
31 13
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GDMA_IN_CHECK_OWNER_CH0
12
11 0
0
0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
GDMA_IN_CHECK_OWNER_CHn Set this bit to enable checking the owner attribute of the descrip-
tor. (R/W)
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Register 2.9. GDMA_IN_POP_CHn_REG (n: 02) (0x007C+192*n)
(reserved)
31 13
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GDMA_INFIFO_POP_CH0
12
11 0
0
GDMA_INFIFO_RDATA_CH0
0x800
GDMA_INFIFO_RDATA_CHn This register stores the data popping from GDMA FIFO (intended for
debugging). (RO)
GDMA_INFIFO_POP_CHn Set this bit to pop data from GDMA FIFO (intended for debugging).
(R/W/SC)
Register 2.10. GDMA_IN_LINK_CHn_REG (n: 02) (0x0080+192*n)
(reserved)
31 25
0 0 0 0 0 0 0
GDMA_INLINK_RESTART_CH0
GDMA_INLINK_START_CH0
GDMA_INLINK_PARK_CH0
24
1
GDMA_INLINK_STOP_CH0
GDMA_INLINK_AUTO_RET_CH0
23
22
21
20
0
0
0
1
19 0
GDMA_INLINK_ADDR_CH0
0x000
Reset
Reset
GDMA_INLINK_ADDR_CHn This register stores the 20 least significant bits of the first receive de-
scriptor’s address. (R/W)
GDMA_INLINK_AUTO_RET_CHn Set this bit to return to current receive descriptor’s address, when
there are some errors in current receiving data. (R/W)
GDMA_INLINK_STOP_CHn Set this bit to stop GDMA’s receive channel from receiving data.
(R/W/SC)
GDMA_INLINK_START_CHn Set this bit to enable GDMA’s receive channel from receiving data.
(R/W/SC)
GDMA_INLINK_RESTART_CHn Set this bit to mount a new receive descriptor. (R/W/SC)
GDMA_INLINK_PARK_CHn 1: the receive descriptor’s FSM is in idle state; 0: the receive descriptor’s
FSM is working. (RO)
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Register 2.11. GDMA_OUT_CONF0_CHn_REG (n: 02) (0x00D0+192*n)
(reserved)
31 6
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GDMA_OUTDSCR_BURST_EN_CH0
GDMA_OUT_EOF_MODE_CH0
GDMA_OUT_AUTO_WRBACK_CH0
GDMA_OUT_DATA_BURST_EN_CH0
5
4
0
0
GDMA_OUT_LOOP_TEST_CH0
3
2
1
1
0
0
GDMA_OUT_RST_CHn This bit is used to reset GDMA channel 0 TX FSM and TX FIFO pointer. (R/W)
GDMA_OUT_LOOP_TEST_CHn Reserved. (R/W)
GDMA_OUT_AUTO_WRBACK_CHn Set this bit to enable automatic outlink-writeback when all the
data in TX buffer has been transmitted. (R/W)
GDMA_OUT_EOF_MODE_CHn EOF flag generation mode when transmitting data. 1: EOF flag for
TX channel 0 is generated when data need to transmit has been popped from FIFO in GDMA.
(R/W)
GDMA_OUTDSCR_BURST_EN_CHn Set this bit to 1 to enable INCR burst transfer for TX channel
0 reading descriptor when accessing internal RAM. (R/W)
GDMA_OUT_DATA_BURST_EN_CHn Set this bit to 1 to enable INCR burst transfer for TX channel
0 transmitting data when accessing internal RAM. (R/W)
GDMA_OUT_RST_CH0
0
0
Reset
Register 2.12. GDMA_OUT_CONF1_CHn_REG (n: 02) (0x00D4+192*n)
(reserved)
31 13
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GDMA_OUT_CHECK_OWNER_CH0
12
11 0
0
0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
GDMA_OUT_CHECK_OWNER_CHn Set this bit to enable checking the owner attribute of the de-
scriptor. (R/W)
Reset
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Register 2.13. GDMA_OUT_PUSH_CHn_REG (n: 02) (0x00DC+192*n)
(reserved)
31 10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GDMA_OUTFIFO_PUSH_CH0
9
8 0
0
GDMA_OUTFIFO_WDATA_CH0
0x0
GDMA_OUTFIFO_WDATA_CHn This register stores the data that need to be pushed into GDMA
FIFO. (R/W)
GDMA_OUTFIFO_PUSH_CHn Set this bit to push data into GDMA FIFO. (R/W/SC)
Register 2.14. GDMA_OUT_LINK_CHn_REG (n: 02) (0x00E0+192*n)
(reserved)
31 24
0 0 0 0 0 0 0 0
GDMA_OUTLINK_PARK_CH0
23
1
GDMA_OUTLINK_STOP_CH0
GDMA_OUTLINK_RESTART_CH0
GDMA_OUTLINK_START_CH0
22
21
20
19 0
0
0
0
GDMA_OUTLINK_ADDR_CH0
0x000
Reset
Reset
GDMA_OUTLINK_ADDR_CHn This register stores the 20 least significant bits of the first transmit
descriptor’s address. (R/W)
GDMA_OUTLINK_STOP_CHn Set this bit to stop GDMA’s transmit channel from transferring data.
(R/W/SC)
GDMA_OUTLINK_START_CHn Set this bit to enable GDMA’s transmit channel for data transfer.
(R/W/SC)
GDMA_OUTLINK_RESTART_CHn Set this bit to restart a new outlink from the last address.
(R/W/SC)
GDMA_OUTLINK_PARK_CHn 1: the transmit descriptor’s FSM is in idle state; 0: the transmit de-
scriptor’s FSM is working. (RO)
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Register 2.15. GDMA_INFIFO_STATUS_CHn_REG (n: 02) (0x0078+192*n)
(reserved)
31 28
0 0 0 0
GDMA_IN_REMAIN_UNDER_4B_CH0
GDMA_IN_REMAIN_UNDER_3B_CH0
GDMA_IN_REMAIN_UNDER_2B_CH0
GDMA_IN_BUF_HUNGRY_CH0
27
26
25
0
1
GDMA_IN_REMAIN_UNDER_1B_CH0
24
23
22 8
1
1
1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
GDMA_INFIFO_CNT_CH0
7 2
0
GDMA_INFIFO_EMPTY_CH0
1
1
GDMA_INFIFO_FULL_CHn L1 RX FIFO full signal for RX channel 0. (RO)
GDMA_INFIFO_EMPTY_CHn L1 RX FIFO empty signal for RX channel 0. (RO)
GDMA_INFIFO_CNT_CHn The register stores the byte number of the data in L1 RX FIFO for RX
channel 0. (RO)
GDMA_IN_REMAIN_UNDER_1B_CHn Reserved. (RO)
GDMA_IN_REMAIN_UNDER_2B_CHn Reserved. (RO)
GDMA_IN_REMAIN_UNDER_3B_CHn Reserved. (RO)
GDMA_IN_REMAIN_UNDER_4B_CHn Reserved. (RO)
GDMA_IN_BUF_HUNGRY_CHn Reserved. (RO)
Register 2.16. GDMA_IN_STATE_CHn_REG (n: 02) (0x0084+192*n)
GDMA_INFIFO_FULL_CH0
0
1
Reset
(reserved)
31 23
0 0 0 0 0 0 0 0 0
GDMA_IN_STATE_CH0
22 20
0
GDMA_IN_DSCR_STATE_CH0
19 18
17 0
0
GDMA_INLINK_DSCR_ADDR_CH0
0
GDMA_INLINK_DSCR_ADDR_CHn This register stores the lower 18 bits of the current receive de-
scriptor’s address. (RO)
GDMA_IN_DSCR_STATE_CHn Reserved. (RO)
GDMA_IN_STATE_CHn Reserved. (RO)
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Register 2.17. GDMA_IN_SUC_EOF_DES_ADDR_CHn_REG (n: 02) (0x0088+192*n)
GDMA_IN_SUC_EOF_DES_ADDR_CH0
31 0
0x000000
Reset
GDMA_IN_SUC_EOF_DES_ADDR_CHn This register stores the address of the receive descriptor
when the EOF bit in this descriptor is 1. (RO)
Register 2.18. GDMA_IN_ERR_EOF_DES_ADDR_CHn_REG (n: 02) (0x008C+192*n)
GDMA_IN_ERR_EOF_DES_ADDR_CH0
31 0
0x000000
GDMA_IN_ERR_EOF_DES_ADDR_CHn This register stores the address of the receive descriptor
when there are some errors in current receiving data. Only used when peripheral is UHCI0. (RO)
Register 2.19. GDMA_IN_DSCR_CHn_REG (n: 02) (0x0090+192*n)
GDMA_INLINK_DSCR_CH0
31 0
0
GDMA_INLINK_DSCR_CHn The address of the current receive descriptor x. (RO)
Reset
Reset
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Register 2.20. GDMA_IN_DSCR_BF0_CHn_REG (n: 02) (0x0094+192*n)
GDMA_INLINK_DSCR_BF0_CH0
31 0
0
Reset
GDMA_INLINK_DSCR_BF0_CHn The address of the last receive descriptor x-1. (RO)
Register 2.21. GDMA_IN_DSCR_BF1_CHn_REG (n: 02) (0x0098+192*n)
GDMA_INLINK_DSCR_BF1_CH0
31 0
0
GDMA_INLINK_DSCR_BF1_CHn The address of the second-to-last receive descriptor x-2. (RO)
Reset
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Register 2.22. GDMA_OUTFIFO_STATUS_CHn_REG (n: 02) (0x00D8+192*n)
(reserved)
31 27
0 0 0 0 0
GDMA_OUT_REMAIN_UNDER_4B_CH0
GDMA_OUT_REMAIN_UNDER_3B_CH0
GDMA_OUT_REMAIN_UNDER_2B_CH0
GDMA_OUT_REMAIN_UNDER_1B_CH0
26
25
24
23
22 8
1
1
1
1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(reserved)
GDMA_OUTFIFO_CNT_CH0
7 2
0
GDMA_OUTFIFO_EMPTY_CH0
1
1
GDMA_OUTFIFO_FULL_CHn L1 TX FIFO full signal for TX channel 0. (RO)
GDMA_OUTFIFO_EMPTY_CHn L1 TX FIFO empty signal for TX channel 0. (RO)
GDMA_OUTFIFO_CNT_CHn The register stores the byte number of the data in L1 TX FIFO for TX
channel 0. (RO)
GDMA_OUT_REMAIN_UNDER_1B_CHn Reserved. (RO)
GDMA_OUT_REMAIN_UNDER_2B_CHn Reserved. (RO)
GDMA_OUT_REMAIN_UNDER_3B_CHn Reserved. (RO)
GDMA_OUT_REMAIN_UNDER_4B_CHn Reserved. (RO)
Register 2.23. GDMA_OUT_STATE_CHn_REG (n: 02) (0x00E4+192*n)
GDMA_OUTFIFO_FULL_CH0
0
0
Reset
(reserved)
31 23
0 0 0 0 0 0 0 0 0
GDMA_OUT_STATE_CH0
22 20
19 18
0
GDMA_OUT_DSCR_STATE_CH0
17 0
0
GDMA_OUTLINK_DSCR_ADDR_CH0
0
GDMA_OUTLINK_DSCR_ADDR_CHn This register stores the lower 18 bits of the current transmit
descriptor’s address. (RO)
GDMA_OUT_DSCR_STATE_CHn Reserved. (RO)
GDMA_OUT_STATE_CHn Reserved. (RO)
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Register 2.24. GDMA_OUT_EOF_DES_ADDR_CHn_REG (n: 02) (0x00E8+192*n)
GDMA_OUT_EOF_DES_ADDR_CH0
31 0
0x000000
Reset
GDMA_OUT_EOF_DES_ADDR_CHn This register stores the address of the transmit descriptor when
the EOF bit in this descriptor is 1. (RO)
Register 2.25. GDMA_OUT_EOF_BFR_DES_ADDR_CHn_REG (n: 02) (0x00EC+192*n)
GDMA_OUT_EOF_BFR_DES_ADDR_CH0
31 0
0x000000
GDMA_OUT_EOF_BFR_DES_ADDR_CHn This register stores the address of the transmit descriptor
before the last transmit descriptor. (RO)
Register 2.26. GDMA_OUT_DSCR_CHn_REG (n: 02) (0x00F0+192*n)
GDMA_OUTLINK_DSCR_CH0
31 0
0
GDMA_OUTLINK_DSCR_CHn The address of the current transmit descriptor y. (RO)
Reset
Reset
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Register 2.27. GDMA_OUT_DSCR_BF0_CHn_REG (n: 02) (0x00F4+192*n)
GDMA_OUTLINK_DSCR_BF0_CH0
31 0
0
Reset
GDMA_OUTLINK_DSCR_BF0_CHn The address of the last transmit descriptor y-1. (RO)
Register 2.28. GDMA_OUT_DSCR_BF1_CHn_REG (n: 02) (0x00F8+192*n)
GDMA_OUTLINK_DSCR_BF1_CH0
31 0
0
GDMA_OUTLINK_DSCR_BF1_CHn The address of the second-to-last receive descriptor x-2. (RO)
Register 2.29. GDMA_IN_PRI_CHn_REG (n: 02) (0x009C+192*n)
(reserved)
31 4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GDMA_RX_PRI_CH0
3 0
0
GDMA_RX_PRI_CHn The priority of RX channel 0. The larger the value, the higher the priority. (R/W)
Reset
Reset
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Register 2.30. GDMA_OUT_PRI_CHn_REG (n: 02) (0x00FC+192*n)
(reserved)
31 4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GDMA_TX_PRI_CH0
3 0
0
GDMA_TX_PRI_CHn The priority of TX channel 0. The larger the value, the higher the priority. (R/W)
Register 2.31. GDMA_IN_PERI_SEL_CHn_REG (n: 02) (0x00A0+192*n)
(reserved)
31 6
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 0
GDMA_PERI_IN_SEL_CH0
0x3f
GDMA_PERI_IN_SEL_CHn This register is used to select peripheral for RX channel 0. 0: SPI2. 1:
reserved. 2: UHCI0. 3: I2S. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC; 9 ~ 63: Invalid.
(R/W)
Reset
Reset
Register 2.32. GDMA_OUT_PERI_SEL_CHn_REG (n: 02) (0x0100+192*n)
(reserved)
31 6
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 0
GDMA_PERI_OUT_SEL_CH0
0x3f
GDMA_PERI_OUT_SEL_CHn This register is used to select peripheral for TX channel 0. 0: SPI2. 1:
reserved. 2: UHCI0. 3: I2S. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC; 9 ~ 63: Invalid.
(R/W)
Reset
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3 System and Memory
3.1 Overview
The ESP32-C3 is an ultra-low-power and highly-integrated system with a 32-bit RISC-V single-core processor
with a four-stage pipeline that operates at up to 160 MHz. All internal memory, external memory, and peripherals
are located on the CPU buses.
3.2 Features
• Address Space
– 792 KB of internal memory address space accessed from the instruction bus
– 552 KB of internal memory address space accessed from the data bus
– 836 KB of peripheral address space
– 8 MB of external memory virtual address space accessed from the instruction bus
– 8 MB of external memory virtual address space accessed from the data bus
– 384 KB of internal DMA address space
• Internal Memory
– 384 KB of Internal ROM
– 400 KB of Internal SRAM
– 8 KB of RTC Memory
• External Memory
– Supports up to 16 MB external flash
• Peripheral Space
– 35 modules/peripherals in total
• GDMA
– 7 GDMA-supported modules/peripherals
Figure 3-1 illustrates the system structure and address mapping.
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0x0000_0000
0x3BFF_FFFF
0x3C00_0000
0x3C7F_FFFF
0x3C80_0000
0x3FC7_FFFF
0x3FC8_0000
0x3FCD_FFFF
0x3FCE_0000
0x3FEF_FFFF
0x3FF0_0000
0x3FF1_FFFF
0x3FF2_0000
0x3FFF_FFFF
0x4000_0000
0x4005_FFFF
0x4006_0000
0x4037_BFFF
0x4037_C000
0x403D_FFFF
0x403E_0000
0x41FF_FFFF
0x4200_0000
0x427F_FFFF
0x4280_0000
0x4FFF_FFFF
0x5000_0000
0x5000_1FFF
0x5000_2000
0x5FFF_FFFF
0x6000_0000
0x600D_0FFF
0x600D_1000
0xFFFF_FFFF
Cache
MMU
External
memory
Reserved
8 MB
External memory
Reserved
384 KB
Internal memory
Reserved
128 KB
Internal memory
Reserved
384 KB
Internal memory
Reserved
400 KB
Internal memory
Reserved
8 MB
External memory
Reserved
8 KB
Internal memory
Reserved
836 KB
Peripherals
Reserved
ROM
RTC FAST Memory
GDMA
Peripheral
SRAM
Data bus
Instruction bus
Data bus
Data bus
Instruction bus
Instruction bus
Data/Instruction
bus
Data/Instruction
bus
Figure 31. System Structure and Address Mapping
Note:
• The address space with gray background is not available to users.
• The range of addresses available in the address space may be larger than the actual available memory of a particular
type.
3.3 Functional Description
3.3.1 Address Mapping
Addresses below 0x4000_0000 are accessed using the data bus. Addresses in the range of 0x4000_0000 ~
0x4FFF_FFFF are accessed using the instruction bus. Addresses over and including 0x5000_0000 are shared by
the data bus and the instruction bus.
Both data bus and instruction bus are little-endian. The CPU can access data via the data bus using single-byte,
double-byte, 4-byte alignment. The CPU can also access data via the instruction bus, but only in 4-byte aligned
manner.
The CPU can:
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• directly access the internal memory via both data bus and instruction bus;
• access the external memory which is mapped into the virtual address space via cache;
• directly access modules/peripherals via data bus.
Figure 3-1 lists the address ranges on the data bus and instruction bus and their corresponding target
memory.
Some internal and external memory can be accessed via both data bus and instruction bus. In such cases, the
CPU can access the same memory using multiple addresses.
3.3.2 Internal Memory
The ESP32-C3 consists of the following three types of internal memory:
• Internal ROM (384 KB): The Internal ROM of the ESP32-C3 is a Mask ROM, meaning it is strictly read-only
and cannot be reprogrammed. Internal ROM contains the ROM code (software instructions and some
software read-only data) of some low level system software.
• Internal SRAM (400 KB): The Internal Static RAM (SRAM) is a volatile memory that can be quickly accessed
by the CPU (generally within a single CPU clock cycle).
– A part of the SRAM can be configured to operate as a cache for external memory access.
– Some parts of the SRAM can only be accessed via the CPU’s instruction bus.
– Some parts of the SRAM can be accessed via both the CPU’s instruction bus and the CPU’s data bus.
• RTC Memory (8 KB): The RTC (Real Time Clock) memory implemented as Static RAM (SRAM) thus is
volatile. However, RTC memory has the added feature of being persistent in deep sleep (i.e., the RTC
memory retains its values throughout deep sleep).
– RTC FAST Memory (8 KB): RTC FAST memory can only be accessed by the CPU and can be
generally used to store instructions and data that needs to persist across a deep sleep.
Based on the three different types of internal memory described above, the internal memory of the ESP32-C3 is
split into three segments: Internal ROM (384 KB), Internal SRAM (400 KB), RTC FAST Memory (8 KB).
However, within each segment, there may be different bus access restrictions (e.g., some parts of the segment
may only be accessible by the CPU’s Data bus). Therefore, each some segments are also further divided into
parts. Table 3-1 describes each part of internal memory and their address ranges on the data bus and/or
instruction bus.
Table 31. Internal Memory Address Mapping
Bus Type
Data bus
Instruction bus
Boundary Address
Low Address High Address
0x3FF0_0000 0x3FF1_FFFF 128 Internal ROM 1
0x3FC8_0000 0x3FCD_FFFF 384 Internal SRAM 1
0x4000_0000 0x4003_FFFF 256 Internal ROM 0
0x4004_0000 0x4005_FFFF 128 Internal ROM 1
0x4037_C000 0x4037_FFFF 16 Internal SRAM 0
0x4038_0000 0x403D_FFFF 384 Internal SRAM 1
Size (KB) Target
Cont’d on next page
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Table 31 – cont’d from previous page
Bus Type
Boundary Address
Low Address High Address
Size (KB) Target
Data/Instruction bus 0x5000_0000 0x5000_1FFF 8 RTC FAST Memory
Note:
All of the internal memories are managed by Permission Control module. An internal memory can only be accessed
when it is allowed by Permission Control, then the internal memory can be available to the CPU. For more information
about Permission Control, please refer to Chapter 14 Permission Control (PMS).
1. Internal ROM 0
Internal ROM 0 is a 256 KB, read-only memory space, addressed by the CPU only through the instruction bus via
0x4000_0000 ~ 0x4003_FFFF, as shown in Table 3-1.
2. Internal ROM 1
Internal ROM 1 is a 128 KB, read-only memory space, addressed by the CPU through the instruction bus via
0x4004_0000 ~ 0x4005_FFFF or through the data bus via 0x3FF0_0000 ~ 0x3FF1_FFFF in the same order, as
shown in Table 3-1.
This means, for example, address 04004_0000 and 0x3FF0_0000 correspond to the same word, 0x4004_0004
and 0x3FF0_0004 correspond to the same word, 0x4004_0008 and 0x3FF0_0008 correspond to the same
word, etc (the same ordering applies for Internal SRAM 1).
3. Internal SRAM 0
Internal SRAM 0 is a 16 KB, read-and-write memory space, addressed by the CPU through the instruction bus
via the range described in Table 3-1.
This memory managed by Permission Control, can be configured as instruction cache to store cache instructions
or read-only data of the external memory. In this case, the memory cannot be accessed by the CPU. For more
information about Permission Control, please refer to Chapter 14 Permission Control (PMS).
4. Internal SRAM 1
Internal SRAM 1 is a 384 KB, read-and-write memory space, addressed by the CPU through the data bus or
instruction bus, in the same order, via the ranges described in Table 3-1.
5. RTC FAST Memory
RTC FAST Memory is a 8 KB, read-and-write SRAM, addressed by the CPU through the data/instruction bus via
the shared address 0x5000_0000 ~ 0x5000_1FFF, as described in Table 3-1.
3.3.3 External Memory
ESP32-C3 supports SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to multiple external flash.
It supports hardware manual encryption and automatic decryption based on XTS_AES to protect user programs
and data in the external flash.
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3.3.3.1 External Memory Address Mapping
The CPU accesses the external memory via the cache. According to the MMU (Memory Management Unit)
settings, the cache maps the CPU’s address to the external memory’s physical address. Due to this address
mapping, the ESP32-C3 can address up to 16 MB external flash.
Using the cache, ESP32-C3 is able to support the following address space mappings. Note that the instruction
bus address space (8MB) and the data bus address space (8 MB) is always shared.
• Up to 8 MB instruction bus address space can be mapped into the external flash. The mapped address
space is organized as individual 64-KB blocks.
• Up to 8 MB data bus (read-only) address space can be mapped into the external flash. The mapped
address space is organized as individual 64-KB blocks.
Table 3-2 lists the mapping between the cache and the corresponding address ranges on the data bus and
instruction bus.
Table 32. External Memory Address Mapping
Bus Type
Data bus (read-only) 0x3C00_0000 0x3C7F_FFFF 8 Uniform Cache
Instruction bus 0x4200_0000 0x427F_FFFF 8 Uniform Cache
Note:
Only if the CPU obtains permission for accessing the external memory, can it be responded for memory access.
For more detailed information about permission control, please refer to Chapter 14 Permission Control (PMS).
Boundary Address
Low Address High Address
Size (MB) Target
3.3.3.2 Cache
As shown in Figure 3-2, ESP32-C3 has a read-only uniform cache which is eight-way set-associative, its size is
16 KB and its block size is 32 bytes. When cache is active, some internal memory space will be occupied by
cache (see Internal SRAM 0 in Section 3.3.2).
The uniform cache is accessible by the instruction bus and the data bus at the same time, but can only respond
to one of them at a time. When a cache miss occurs, the cache controller will initiate a request to the external
memory.
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Figure 32. Cache Structure
3.3.3.3 Cache Operations
ESP32-C3 cache support the following operations:
1. Invalidate: This operation is used to clear valid data in the cache. After this operation is completed, the
data will only be stored in the external memory. The CPU needs to access the external memory in order to
read this data. There are two types of invalidate-operation: automatic invalidation (Auto-Invalidate) and
manual invalidation (Manual-Invalidate). Manual-Invalidate is performed only on data in the specified area in
the cache, while Auto-Invalidate is performed on all data in the cache.
2. Preload: This operation is used to load instructions and data into the cache in advance. The minimum unit
of preload-operation is one block. There are two types of preload-operation: manual preload
(Manual-Preload) and automatic preload (Auto-Preload). Manual-Preload means that the hardware
prefetches a piece of continuous data according to the virtual address specified by the software.
Auto-Preload means the hardware prefetches a piece of continuous data according to the current address
where the cache hits or misses (depending on configuration).
3. Lock/Unlock: The lock operation is used to prevent the data in the cache from being easily replaced.
There are two types of lock: prelock and manual lock. When prelock is enabled, the cache locks the data
in the specified area when filling the missing data to cache memory, while the data outside the specified
area will not be locked. When manual lock is enabled, the cache checks the data that is already in the
cache memory and only locks the data in the specified area, and leaves the data outside the specified area
unlocked. When there are missing data, the cache will replace the data in the unlocked way first, so the
data in the locked way is always stored in the cache and will not be replaced. But when all ways within the
cache are locked, the cache will replace data, as if it was not locked. Unlocking is the reverse of locking,
except that it only can be done manually.
Please note that the Manual-Invalidate operations will only work on the unlocked data. If you expect to
perform such operation on the locked data, please unlock them first.
3.3.4 GDMA Address Space
The GDMA (General Direct Memory Access) peripheral in ESP32-C3 can provide DMA (Direct Memory Access)
services including:
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• Data transfers between different locations of internal memory;
• Data transfers between modules/peripherals and internal memory.
GDMA uses the same addresses as the data bus to read and write Internal SRAM 1. Specifically, GDMA uses
address range 0x3FC8_0000 ~ 0x3FCD_FFFF to access Internal SRAM 1. Note that GDMA cannot access the
internal memory occupied by the cache.
There are 7 peripherals/modules that can work together with GDMA.
As shown in Figure 3-3, these 7 vertical lines in turn correspond to these 7 peripherals/modules with GDMA
function, the horizontal line represents a certain channel of GDMA (can be any channel), and the intersection of
the vertical line and the horizontal line indicates that a peripheral/module has the ability to access the
corresponding channel of GDMA. If there are multiple intersections on the same line, it means that these
peripherals/modules cannot enable the GDMA function at the same time.
Figure 33. Peripherals/modules that can work with GDMA
These peripherals/modules can access any memory available to GDMA. For more information, please refer to
Chapter 2 GDMA Controller (GDMA).
Note:
When accessing a memory via GDMA, a corresponding access permission is needed, otherwise this access may
fail. For more information about permission control, please refer to Chapter 14 Permission Control (PMS).
3.3.5 Modules/Peripherals
The CPU can access modules/peripherals via 0x6000_0000 ~ 0x600D_0FFF shared by the data/instruction
bus.
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3.3.5.1 Module/Peripheral Address Mapping
Table 3-3 lists all the modules/peripherals and their respective address ranges. Note that the address space of
specific modules/peripherals is defined by ”Boundary Address” (including both Low Address and High
Address).
Table 33. Module/Peripheral Address Mapping
Target
UART Controller 0 0x6000_0000 0x6000_0FFF 4
Reserved 0x6000_1000 0x6000_1FFF
SPI Controller 1 0x6000_2000 0x6000_2FFF 4
SPI Controller 0 0x6000_3000 0x6000_3FFF 4
GPIO 0x6000_4000 0x6000_4FFF 4
Reserved 0x6000_5000 0x6000_6FFF
TIMER 0x6000_7000 0x6000_7FFF 4
Low-Power Management 0x6000_8000 0x6000_8FFF 4
IO MUX 0x6000_9000 0x6000_9FFF 4
Reserved 0x6000_A000 0x6000_FFFF
UART Controller 1 0x6001_0000 0x6001_0FFF 4
Reserved 0x6001_1000 0x6001_2FFF
I2C Controller 0x6001_3000 0x6001_3FFF 4
UHCI0 0x6001_4000 0x6001_4FFF 4
Reserved 0x6001_5000 0x6001_5FFF
Remote Control Peripheral 0x6001_6000 0x6001_6FFF 4
Reserved 0x6001_7000 0x6001_8FFF
LED PWM Controller 0x6001_9000 0x6001_9FFF 4
eFuse Controller 0x6001_A000 0x6001_AFFF 4
Reserved 0x6001_B000 0x6001_EFFF
Timer Group 0 0x6001_F000 0x6001_FFFF 4
Timer Group 1 0x6002_0000 0x6002_0FFF 4
Reserved 0x6002_1000 0x6002_2FFF
System Timer 0x6002_3000 0x6002_3FFF 4
SPI Controller 2 0x6002_4000 0x6002_4FFF 4
Reserved 0x6002_5000 0x6002_5FFF
APB Controller 0x6002_6000 0x6002_6FFF 4
Reserved 0x6002_7000 0x6002_AFFF
Two-wire Automotive Interface 0x6002_B000 0x6002_BFFF 4
Reserved 0x6002_C000 0x6002_CFFF
I2S Controller 0x6002_D000 0x6002_DFFF 4
Reserved 0x6002_E000 0x6003_9FFF
AES Accelerator 0x6003_A000 0x6003_AFFF 4
SHA Accelerator 0x6003_B000 0x6003_BFFF 4
RSA Accelerator 0x6003_C000 0x6003_CFFF 4
Boundary Address
Low Address High Address
Size (KB) Notes
Cont’d on next page
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Table 33 – cont’d from previous page
Target
Boundary Address
Low Address High Address
Size (KB) Notes
Digital Signature 0x6003_D000 0x6003_DFFF 4
HMAC Accelerator 0x6003_E000 0x6003_EFFF 4
GDMA Controller 0x6003_F000 0x6003_FFFF 4
ADC Controller 0x6004_0000 0x6004_0FFF 4
Reserved 0x6004_1000 0x6002_FFFF
USB Serial/JTAG Controller 0x6004_3000 0x6004_3FFF 4
Reserved 0x6004_4000 0x600B_FFFF
System Registers 0x600C_0000 0x600C_0FFF 4
Sensitive Register 0x600C_1000 0x600C_1FFF 4
Interrupt Matrix 0x600C_2000 0x600C_2FFF 4
Reserved 0x600C_3000 0x600C_3FFF
Configure Cache 0x600C_4000 0x600C_BFFF 32
External Memory Encryption and
0x600C_C000 0x600C_CFFF 4
Decryption
Reserved 0x600C_D000 0x600C_DFFF
Assist Debug 0x600C_E000 0x600C_EFFF 4
Reserved 0x600C_F000 0x600C_FFFF
World Controller 0x600D_0000 0x600D_0FFF 4
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4 eFuse Controller (EFUSE)
4.1 Overview
ESP32-C3 contains a 4096-bit eFuse controller to store parameters. Once an eFuse bit is programmed to 1, it
can never be reverted to 0. The eFuse controller programs individual bits of parameters in eFuse according to
user configurations. From outside the chip, eFuse data can only be read via the eFuse Controller. If
read-protection for some data is not enabled, that data is readable from outside the chip. If read-protection is
enabled, that data can not be read from outside the chip. In all cases, however, some keys stored in eFuse can
still be used internally by hardware cryptography modules such as Digital Signature, HMAC, etc., without
exposing this data to the outside world.
4.2 Features
• 4096-bit One-time programmable storage
• Configurable write protection
• Configurable read protection
• Various hardware encoding schemes against data corruption
4.3 Functional Description
4.3.1 Structure
eFuse data is organized in 11 blocks (BLOCK0 ~ BLOCK10).
BLOCK0, which holds most parameters, has 9 bits that are readable but useless to users, and 60 further bits are
reserved for future use.
Table 4-1 lists all the parameters accessible (readable and usable) to users in BLOCK0 and their offsets, bit
widths, as well as information on whether their configuration is directly accessible by hardware, and whether they
are protected from programming.
The EFUSE_WR_DIS parameter is used to disable the writing of other parameters, while EFUSE_RD_DIS is
used to disable users from reading BLOCK4 ~ BLOCK10. For more information on these two parameters, please
see Section 4.3.1.1 and Section 4.3.1.2.
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Table 41. Parameters in eFuse BLOCK0
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ProgrammingProtection
by EFUSE_WR_DIS
Bit Number
Description
Parameters
Bit
Width
Accessible
by Hardware
EFUSE_WR_DIS 32 Y N/A Represents whether writing of individual eFuses is disabled.
EFUSE_RD_DIS 7 Y 0
Represents whether users’ reading from BLOCK4 ~ 10 is
disabled.
EFUSE_DIS_ICACHE 1 Y 2 Represents whether iCache is disabled.
EFUSE_DIS_USB_JTAG 1 Y 2 Represents whether the USB-to-JTAG function is disabled.
EFUSE_DIS_DOWNLOAD_ICACHE 1 Y 2 Represents whether iCache is disabled in Download mode.
EFUSE_DIS_USB_SERIAL_JTAG 1 Y 2
EFUSE_DIS_FORCE_DOWNLOAD 1 Y 2
Represents whether the usb_serial_jtag peripheral is dis-
abled.
Represents whether the function to force the chip into Down-
load mode is disabled.
EFUSE_DIS_TWAI 1 Y 2 Represents whether the TWAI controller is disabled.
EFUSE_JTAG_SEL_ENABLE 1 Y 2 Represents whether to use JTAG directly.
EFUSE_SOFT_DIS_JTAG 3 Y 31 Represents whether JTAG is disabled in the soft way.
EFUSE_DIS_PAD_JTAG 1 Y 2
EFUSE_DIS_DOWNLOAD_ MANUAL_ENCRYPT 1 Y 2
Represents whether JTAG is disabled in the hard way (per-
manently).
Represents whether flash encryption is disabled in Download
boot mode.
EFUSE_USB_EXCHG_PINS 1 Y 30 Represents whether the D+ and D- pins are exchanged.
EFUSE_VDD_SPI_AS_GPIO 1 N 30
EFUSE_WDT_DELAY_SEL 2 Y 3
EFUSE_SPI_BOOT_CRYPT_CNT 3 Y 4
Represents whether the VDD_SPI pin is used as a regular
GPIO.
Represents whether RTC watchdog timeout threshold is se-
lected.
Represents whether SPI boot encryption/decryption is en-
abled.
Cont’d on next page
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Parameters
Table 41 – cont’d from previous page
Bit
Width
Accessible
by Hardware
ProgrammingProtection
by EFUSE_WR_DIS
Bit Number
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EFUSE_SECURE_BOOT_KEY_ REVOKE0 1 N 5
EFUSE_SECURE_BOOT_KEY_ REVOKE1 1 N 6
EFUSE_SECURE_BOOT_KEY_ REVOKE2 1 N 7
Represents whether revoking the first Secure Boot key is en-
abled.
Represents whether revoking the second Secure Boot key is
enabled..
Represents whether revoking the third Secure Boot key is
enabled.
EFUSE_KEY_PURPOSE_0 4 Y 8 Represents Key0 purpose, see Table 4-2.
EFUSE_KEY_PURPOSE_1 4 Y 9 Represents Key1 purpose, see Table 4-2.
EFUSE_KEY_PURPOSE_2 4 Y 10 Represents Key2 purpose, see Table 4-2.
EFUSE_KEY_PURPOSE_3 4 Y 11 Represents Key3 purpose, see Table 4-2.
EFUSE_KEY_PURPOSE_4 4 Y 12 Represents Key4 purpose, see Table 4-2.
EFUSE_KEY_PURPOSE_5 4 Y 13 Represents Key5 purpose, see Table 4-2.
EFUSE_SECURE_BOOT_EN 1 N 15 Represents whether Secure Boot is enabled.
EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE 1 N 16
Represents whether aggressive revocation of Secure Boot is
enabled.
EFUSE_FLASH_TPUW 4 N 18 Represents the flash waiting time after power-up.
EFUSE_DIS_DOWNLOAD_MODE 1 N 18 Represents whether all download modes are disabled.
EFUSE_USB_PRINT_CHANNEL 1 N 18 Represents whether USB printing is disabled.
EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE 1 N 18
EFUSE_ENABLE_SECURITY_DOWNLOAD 1 N 18
Represents whether the USB-Serial-JTAG download func-
tion is disabled.
Represents whether UART secure download mode is en-
abled.
EFUSE_UART_PRINT_CONTROL 2 N 18 Represents the UART boot message output mode.
EFUSE_FORCE_SEND_RESUME 1 N 18
Represents whether ROM code is forced to send a resume
command during SPI boot.
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Parameters
Table 41 – cont’d from previous page
Bit
Width
Accessible
by Hardware
ProgrammingProtection
by EFUSE_WR_DIS
Bit Number
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EFUSE_SECURE_VERSION 16 N 18
EFUSE_ERR_RST_ENABLE 1 N 19
Represents the version used by ESP-IDF anti-rollback fea-
ture.
Represents whether to use BLOCK0 to check error record
registers.
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Table 4-2 lists all key purpose and their values. Setting the eFuse parameter EFUSE_KEY_PURPOSE_n declares
the purpose of KEYn (n: 0 ~ 5).
Table 42. Secure Key Purpose Values
Key
Purpose
Purposes
Values
0 User purposes
1 Reserved
2 Reserved
3 Reserved
4 XTS_AES_128_KEY (flash/SRAM encryption and decryption)
5 HMAC Downstream mode (both JTAG and DS)
6 JTAG in HMAC Downstream mode
7 Digital Signature peripheral in HMAC Downstream mode
8 HMAC Upstream mode
9 SECURE_BOOT_DIGEST0 (secure boot key digest)
10 SECURE_BOOT_DIGEST1 (secure boot key digest)
11 SECURE_BOOT_DIGEST2 (secure boot key digest)
Table 4-3 provides the details of parameters in BLOCK1 ~ BLOCK10.
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Table 43. Parameters in BLOCK1 to BLOCK10
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BLOCK Parameters Bit Width
Accessible
by Hardware
Write Protection by
EFUSE_WR_DIS
Bit Number
Read Protection
byEFUSE_RD_DIS
Bit Number
Description
BLOCK1 EFUSE_MAC 48 N 20 N/A MAC address
EFUSE_SPI_PAD_ [0:5] N 20 N/A CLK
CONFIGURE [6:11] N 20 N/A Q (D1)
[12:17] N 20 N/A D (D0)
[18:23] N 20 N/A CS
[24:29] N 20 N/A HD (D3)
[30:35] N 20 N/A WP (D2)
[36:41] N 20 N/A DQS
[42:47] N 20 N/A D4
[48:53] N 20 N/A D5
[54:59] N 20 N/A D6
[60:65] N 20 N/A D7
EFUSE_SYS_DATA_PART0 78 N 20 N/A System data
BLOCK2 EFUSE_SYS_DATA_PART1 256 N 21 N/A System data
BLOCK3 EFUSE_USR_DATA 256 N 22 N/A User data
BLOCK4 EFUSE_KEY0_DATA 256 Y 23 0 KEY0 or user data
BLOCK5 EFUSE_KEY1_DATA 256 Y 24 1 KEY1 or user data
BLOCK6 EFUSE_KEY2_DATA 256 Y 25 2 KEY2 or user data
BLOCK7 EFUSE_KEY3_DATA 256 Y 26 3 KEY3 or user data
BLOCK8 EFUSE_KEY4_DATA 256 Y 27 4 KEY4 or user data
BLOCK9 EFUSE_KEY5_DATA 256 Y 28 5 KEY5 or user data
BLOCK10 EFUSE_SYS_DATA_PART2 256 N 29 6 System data
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Among these blocks, BLOCK4 ~ 9 stores KEY0 ~ 5, respectively. Up to six 256-bit keys can be written into
eFuse. Whenever a key is written, its purpose value should also be written (see table 4-2). For example, when a
key for the JTAG function in HMAC Downstream mode is written to KEY3 (i.e., BLOCK7), its key purpose value 6
should also be written to EFUSE_KEY_PURPOSE_3.
Note:
Do not program the XTS-AES key into the KEY5 block, i.e., BLOCK9. Otherwise, the key may be unreadable. Instead,
program it into the preceding blocks, i.e., BLOCK4 ~ BLOCK8. The last block, BLOCK9, is used to program other keys.
BLOCK1 ~ BLOCK10 use the RS coding scheme, so there are some restrictions on writing to these parameters.
For more detailed information, please refer to Section 4.3.1.3 and Section 4.3.2.
4.3.1.1 EFUSE_WR_DIS
Parameter EFUSE_WR_DIS determines whether individual eFuse parameters are write-protected. After
EFUSE_WR_DIS has been programmed, execute an eFuse read operation so the new values would take
effect.
Column “Write Protection by EFUSE_WR_DIS Bit Number” in Table 4-1 and Table 4-3 list the specific bits in
EFUSE_WR_DIS that disable writing.
When the write protection bit of a parameter is set to 0, it means that this parameter is not write-protected and
can be programmed, unless it has been programmed before.
When the write protection bit of a parameter is set to 1, it means that this parameter is write-protected and none
of its bits can be modified, with non-programmed bits always remaining 0 while programmed bits always remain
1.
4.3.1.2 EFUSE_RD_DIS
Only the eFuse blocks in BLOCK4 ~ BLOCK10 can be individually read protected to prevent any access from
outside the chip, as shown in column “Read Protection by EFUSE_RD_DIS Bit Number” of Table 4-3. After
EFUSE_RD_DIS has been programmed, execute an eFuse read operation so the new values would take
effect.
If the corresponding EFUSE_RD_DIS bit is 0, then the eFuse block can be read by users; if the corresponding
EFUSE_RD_DIS bit is 1, then the parameter controlled by this bit is user protected.
Other parameters that are not in BLOCK4 ~ BLOCK10 can always be read by users.
When BLOCK4 ~ BLOCK10 are set to be read-protected, the data in these blocks are not readable by users, but
they can still be read by hardware cryptography modules, if the EFUSE_KEY_PURPOSE_n bit is set
accordingly.
4.3.1.3 Data Storage
Internally, eFuses use hardware encoding schemes to protect data from corruption, which are invisible for
users.
All BLOCK0 parameters except for EFUSE_WR_DIS are stored with four backups, meaning each bit is stored
four times. This backup scheme is not visible to users.
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