Epson S-7600A Datasheet
S-7600A TCP/IP NETWORK STACK LSI - Revision 1.3
Hardware Specification
S-7600A
TCP/IP Network Stack LSI
Components Marketing Dept.
Marketing Section 2
Phone +81-43-211-1028
Fax +81-43-211-8035
8, Nakase 1-chome, Mihama-ku
Chiba-shi, Chiba 261-8507, Japan
Seiko Instruments Inc.
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
TABLE OF CONTE NTS
1. INTRODUCTION........................................................................................................................... 1-1
1.1. P
1.2. F
1.3. B
1.4. T
1.5. D
1.6. A
1.7. C
RODUCT OVERVIEW
EATURES
ENEFITS
RADEMARKS
EFINITIONS
PPLICABLE DOCUMENTS
AUTIONS
............................................................................................................................... 1-1
................................................................................................................................. 1-1
........................................................................................................................... 1-2
............................................................................................................................ 1-2
................................................................................................................................1-2
............................................................................................................... 1-1
......................................................................................................... 1-2
2. FUNCTIONAL BLOCK DIAGRAM ............................................................................................... 2-1
3. TERMINALS.................................................................................................................................. 3-1
3.1. P
3.2. P
3.3. P
3.4. P
IN ASSIGNMENT
ACKAGE DIMENSIONS
IN DESCRIPTION
IN CONFIGURATION
...................................................................................................................... 3-1
............................................................................................................. 3-2
..................................................................................................................... 3-3
................................................................................................................ 3-4
4. ELECTRICAL CHARACTERISTICS............................................................................................. 4-1
4.1. A
4.2. R
BSOLUTE MAXIMUM RATINGS
ECOMMENDED OPERATING CONDITIONS
4.3. DC C
4.4. P
OWER CURRENT CONSUMPTION
HARACTERISTICS
............................................................................................................. 4-2
.................................................................................................. 4-1
................................................................................. 4-1
............................................................................................. 4-2
5. MPU INTERFACE......................................................................................................................... 5-1
5.1. O
5.2. P
VERVIEW
ARALLEL INTERFACE
............................................................................................................................... 5-1
............................................................................................................... 5-1
5.2.1. 68k Family MPU Mode.................................................................................................... 5-2
5.2.1.1. Write Cycle Timing ................................................................................................................5-2
5.2.1.2. Read Cycle Timing................................................................................................................5-3
5.2.2. x80 Family MPU Mode.................................................................................................... 5-4
5.2.2.1. Write Cycle Timing ................................................................................................................5-4
5.2.2.2. Read Cycle Timing................................................................................................................5-5
5.3. S
ERIAL INTERFACE
................................................................................................................... 5-6
5.3.1. Write Cycle Timing.......................................................................................................... 5-6
5.3.2. Read Cycle Timing.......................................................................................................... 5-7
5.4. I
NTERRUPT
............................................................................................................................... 5-8
6. MEMORY REQUIREMENTS........................................................................................................ 6-1
6.1. O
6.2. M
6.3. M
VERVIEW
EMORY INTERFACE ARCHITECTURE
EMORY MAP
............................................................................................................................... 6-1
........................................................................................ 6-1
.......................................................................................................................... 6-2
7. S-7600A REGISTER DEFINITIONS............................................................................................. 7-1
7.1. O
7.2.
7.3. R
VERVIEW
API R
I
EGISTER DEFINITIONS
............................................................................................................................... 7-1
EGISTER MAP
................................................................................................................. 7-1
............................................................................................................ 7-4
7.3.1. Revision Register (0x00)................................................................................................ 7-4
7.3.2. General Control Register (0x01).................................................................................... 7-4
7.3.3. Generic Socket Location Register (0x02)...................................................................... 7-5
7.3.4. Master Interrupt (0x04) ..................................................................................................7-5
7.3.5. Serial Port Configuration / Status Register (0x08)......................................................... 7-6
7.3.6. Serial Port Interrupt Register (0x09).............................................................................. 7-8
7.3.7. Serial Port Interrupt Mask Register (0x0A) .................................................................... 7-8
7.3.8. Serial Port Data Register (0x0B).................................................................................... 7-9
7.3.9. BAUD Rate Divider Registers (0x0C-0x0D)................................................................... 7-9
Seiko Instruments Inc.
i
TCP/IP Network Stack LSI
S-7600A
7.3.10. Our IP Address Registers (0x10-0x13) ...................................................................... 7-9
7.3.11. Clock Divider Registers (0x1C-0x1D) ...................................................................... 7-10
7.3.12. Index Register (0x20)............................................................................................... 7-10
7.3.13. Type of Service Register (TOS) (0x21).................................................................... 7-10
7.3.14. Socket Config Status Low Register (0x22)............................................................... 7-11
7.3.15. Socket Status Mid Register (0x23)........................................................................... 7-13
7.3.16. Socket Activate Register (0x24)............................................................................... 7-14
7.3.17. Socket Interrupt Register (0x26) .............................................................................. 7-14
7.3.18. Socket Data Available Register (0x28)..................................................................... 7-15
7.3.19. Socket Interrupt Mask Low Register (0x2A).............................................................7-16
7.3.20. Socket Interrupt Mask High Register (0x2B)............................................................ 7-16
7.3.21. Socket Interrupt Low Register (0x2C)...................................................................... 7-17
7.3.22. Socket Interrupt High Register (0x2D) ..................................................................... 7-17
7.3.23. Socket Data Register (0x2E).................................................................................... 7-18
7.3.24. TCP Data Send and Buffer Out Length Registers (0x30-0x31)............................... 7-18
7.3.25. Buffer In Length Registers (0x32-0x33) ................................................................... 7-18
7.3.26. Urgent Data Pointer Registers (0x34-0x35)............................................................. 7-18
7.3.27. Their Port Registers (0x36-0x37)............................................................................. 7-19
7.3.28. Our Port Registers (0x38-0x39) ............................................................................... 7-19
7.3.29. Socket Status High Register (0x3A)......................................................................... 7-19
7.3.30. Their IP Address Registers (0x3C-0x3F) ................................................................. 7-20
7.3.31. PPP Control and Status Register (0x60).................................................................. 7-21
7.3.32. PPP Interrupt Code (0x61)....................................................................................... 7-22
7.3.33. PPP Max Retry, (0x62).............................................................................................. 7-22
7.3.34. PAP String (0x64)..................................................................................................... 7-23
Hardware Specification Revision 1.3
8. DATA COMMUNICATIONS.......................................................................................................... 8-1
8.1. O
8.2. S
VERVIEW
ERIAL PORT REGISTER MAP
............................................................................................................................... 8-1
................................................................................................... 8-1
8.2.1. Hardware Flow Control (RTS/CTS Handshaking) .......................................................... 8-2
8.2.2. Serial Port Control........................................................................................................... 8-2
8.3. TCP/UDP D
ATA COMMUNICATIONS
.......................................................................................... 8-3
8.3.1. TCP Data Communications............................................................................................ 8-3
8.3.2. UDP Data Communications............................................................................................ 8-4
9. RESET FUNCTIONS .................................................................................................................... 9-1
9.1. O
VERVIEW
............................................................................................................................... 9-1
9.1.1. Hardware Reset Function............................................................................................... 9-1
9.1.2. Software Reset Function................................................................................................. 9-1
10. APPLICATION EXAMPLES........................................................................................................ 10-1
10.1.1. In Case of x80 Family MPU with LCD Controller.......................................................... 10-1
10.1.2. In Case of 68k Family MPU with LCD Controller.......................................................... 10-2
10.1.3. In Case of Serial Interface with LCD Controller ............................................................ 10-3
ii
Seiko Instruments Inc.
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
LIST OF FIGURES
F
IGURE
F
IGURE
F
IGURE
F
IGURE
F
IGURE
IGURE
F
F
IGURE
F
IGURE
F
IGURE
F
IGURE
IGURE
F
F
IGURE
F
IGURE
F
IGURE
F
IGURE
IGURE
F
F
IGURE
F
IGURE
2-1 B
3-1 P
3-2 P
3-3 C
LOCK DIAGRAM
IN ASSIGNMENT
ACKAGE DIMENSIONS
ONFIGURATION OF EACH PIN
5-1 68K F
5-2 68K F
5-3X80 F
5-4X80 F
5-5 S
5-6 S
ERIAL INTERFACE WRITE TIMING
ERIAL INTERFACE READ TIMING
5-7 INT1 I
6-1 M
8-1 S
9-1 H
9-2 S
10-1 E
10-2 E
10-3 E
EMORY INTERFACE ARCHITECTURE
ERIAL DATA FORMAT
ARDWARE RESET TIMING
OFTWARE RESET TIMING
XAMPLE FOR X
XAMPLE FOR 68K FAMILY
XAMPLE FOR SERIAL INTERFACE
............................................................................................................... 2-1
.............................................................................................................. 3-1
MPU W
AMILY
MPU R
AMILY
MPU W
AMILY
MPU R
AMILY
NTERRUPT TIMING
RITE TIMING
EAD TIMING
RITE CYCLE TIMING
EAD CYCLE TIMING
80 F
AMILY
...................................................................................................... 3-2
........................................................................................... 3-4
....................................................................................... 5-2
......................................................................................... 5-3
............................................................................ 5-4
.............................................................................. 5-5
..................................................................................... 5-6
....................................................................................... 5-7
................................................................................................... 5-8
................................................................................. 6-1
....................................................................................................... 8-1
................................................................................................ 9-1
................................................................................................. 9-1
MPU...................................................................................... 10-1
MPU...................................................................................... 10-2
.................................................................................... 10-3
Seiko Instruments Inc.
iii
TCP/IP Network Stack LSI
S-7600A
T
3-1 P
ABLE
3-2 P
T
ABLE
4-1 A
T
ABLE
4-2 R
T
ABLE
4-3 DC C
T
ABLE
4-4 P
T
ABLE
5-1 I
T
ABLE
5-2 C
T
ABLE
5-3 68K F
T
ABLE
5-4 68K F
ABLE
T
5-5 X80 F
T
ABLE
5-6 X80 F
T
ABLE
5-7 S
T
ABLE
5-8 S
T
ABLE
5-9 I
ABLE
T
6-1 S-7600A M
T
ABLE
6-2 S-7600A M
T
ABLE
7-1 IAPI R
T
ABLE
7-2 IAPI R
T
ABLE
7-3 R
T
ABLE
7-4 R
T
ABLE
7-5 G
T
ABLE
7-6 G
T
ABLE
7-7 G
T
ABLE
7-8 G
T
ABLE
7-9 M
ABLE
T
7-10 M
T
ABLE
7-11 C
T
ABLE
7-12 C
T
ABLE
7-13 S
ABLE
T
7-14 S
ABLE
T
7-15 S
T
ABLE
7-16 S
T
ABLE
7-17 O
T
ABLE
7-18 O
ABLE
T
7-19 O
ABLE
T
7-20 O
T
ABLE
7-21 I
T
ABLE
7-22 I
T
ABLE
7-23 S
ABLE
T
7-24 S
ABLE
T
7-25 S
T
ABLE
7-26 S
ABLE
T
7-27 S
T
ABLE
7-28 S
T
ABLE
7-29 S
ABLE
T
7-30 S
T
ABLE
7-31 S
ABLE
T
7-32 S
T
ABLE
7-33 S
T
ABLE
7-34 S
ABLE
T
7-35 S
T
ABLE
7-36 S
T
ABLE
7-37 S
T
ABLE
7-38 S
T
ABLE
7-39 S
ABLE
T
IN ASSIGNMENT
IN DESCRIPTION
BSOLUTE MAXIMUM RATINGS
ECOMMENDED OPERATING CONDITIONS
HARACTERISTICS
OWER CURRENT CONSUMPTION
NTERFACE SELECTION
ONNECTION RELATIONSHIP BETWEEN
AMILY
AMILY
AMILY
AMILY
ERIAL INTERFACE WRITE CYCLE TIMING
ERIAL INTERFACE READ CYCLE TIMING
NTERRUPT SELECTION TABLE
EGISTER MAP
EGISTER MAP (CONTINUED
EVISION REGISTER BIT DEFINITIONS
EVISION REGISTER DESCRIPTION
ENERAL CONTROL REGISTER BIT DEFINITIONS
ENERAL CONTROL REGISTER DESCRIPTION
ENERIC SOCKET LOCATION REGISTER BIT DEFINITIONS
ENERIC SOCKET LOCATION REGISTER DESCRIPTION
ASTER INTERRUPT REGISTER BIT DEFINITIONS
ASTER INTERRUPT REGISTER DESCRIPTIONS (CONTINUED
ONF STATUS REGISTER BIT DEFINITIONS
ONF STATUS REGISTER DESCRIPTION
ERIAL PORT INTERRUPT REGISTER BIT DEFINITIONS
ERIAL PORT INTERRUPT REGISTER DESCRIPTION
ERIAL PORT INTERRUPT MASK REGISTER BIT DEFINITIONS
ERIAL PORT INTERRUPT MASK REGISTER DESCRIPTION
IP A
UR
IP A
UR
IP A
UR
IP A
UR
NDEX REGISTER BIT DEFINITION
NDEX REGISTER DESCRIPTION
OCKET CONFIG STATUS LOW REGISTER BIT DEFINITIONS
OCKET CONFIG STATUS LOW REGISTER DESCRIPTION
OCKET STATUS MID REGISTER BIT DEFINITIONS
OCKET STATUS MID REGISTER DESCRIPTION
OCKET ACTIVATE REGISTER BIT DEFINITIONS
OCKET ACTIVATE REGISTER DESCRIPTION
OCKET INTERRUPT REGISTER BIT DEFINITIONS
OCKET INTERRUPT REGISTER DESCRIPTION
OCKET DATA AVAIL REGISTER BIT DEFINITIONS
OCKET DATA AVAIL REGISTER DESCRIPTION
OCKET INTERRUPT MASK LOW REGISTER BIT DEFINITIONS
OCKET INTERRUPT MASK LOW REGISTER DESCRIPTION
OCKET INTERRUPT MASK HIGH REGISTER BIT DEFINITIONS
OCKET INTERRUPT MASK HIGH REGISTER DESCRIPTION
OCKET INTERRUPT LOW REGISTER BIT DEFINITIONS
OCKET INTERRUPT LOW REGISTER DESCRIPTION
OCKET INTERRUPT HIGH REGISTER BIT DEFINITIONS
.................................................................................................................. 3-1
.................................................................................................................. 3-3
MPU W
MPU R
MPU W
MPU R
EMORY MAP (BANK
EMORY MAP (BANK
DDRESS REGISTER BIT DEFINITIONS (0X
DDRESS REGISTER BIT DEFINITIONS (0X
DDRESS REGISTER BIT DEFINITIONS (0X
DDRESS REGISTER BIT DEFINITIONS (0X
Hardware Specification Revision 1.3
LIST OF TABLES
.............................................................................................. 4-1
.............................................................................. 4-1
.......................................................................................................... 4-2
.......................................................................................... 4-2
.......................................................................................................... 5-1
MPU
AND PINS
RITE CYCLE TIMING
EAD CYCLE TIMING
RITE CYCLE TIMING
EAD CYCLE TIMING
................................................................................ 5-2
................................................................................. 5-3
................................................................................ 5-4
................................................................................. 5-5
.............................................................................. 5-6
................................................................................ 5-7
............................................................................................... 5-8
0)......................................................................................... 6-2
1)......................................................................................... 6-2
............................................................................................................. 7-2
)........................................................................................ 7-3
.................................................................................... 7-4
........................................................................................ 7-4
......................................................................... 7-4
........................................................................... 7-6
............................................................................... 7-7
....................................................................................... 7-10
.......................................................................................... 7-10
................................................................... 7-13
....................................................................... 7-14
.................................................................... 7-15
................................................................... 7-15
.......................................................... 5-1
.................................................................... 7-4
....................................................... 7-5
........................................................... 7-5
.................................................................... 7-5
)............................................... 7-6
.......................................................... 7-8
............................................................... 7-8
................................................. 7-8
..................................................... 7-8
10) .......................................................... 7-9
11) .......................................................... 7-9
12) ........................................................ 7-10
13) ........................................................ 7-10
................................................ 7-11
..................................................... 7-12
.............................................................. 7-13
.................................................................. 7-14
................................................................ 7-14
............................................................... 7-15
.............................................. 7-16
................................................... 7-16
.............................................. 7-16
.................................................. 7-16
........................................................ 7-17
............................................................. 7-17
....................................................... 7-17
iv
Seiko Instruments Inc.
TCP/IP Network Stack LSI
S-7600A
T
7-40 S
ABLE
ABLE
T
T
ABLE
T
ABLE
T
ABLE
T
ABLE
ABLE
T
T
ABLE
T
ABLE
T
ABLE
T
ABLE
ABLE
T
T
ABLE
T
ABLE
T
ABLE
T
ABLE
ABLE
T
T
ABLE
T
ABLE
T
ABLE
7-41 T
7-42 T
7-43 O
7-44 O
7-45 S
7-46 S
7-47 T
7-48 T
7-49 T
7-50 T
7-51 PPP C
7-52 PPP C
7-53 PPP I
7-54 PPP I
7-55 PPP M
7-56 PAP S
7-57 PAP S
8-1 S
8-12 H
OCKET INTERRUPT HIGH REGISTER DESCRIPTION
HEIR PORT REGISTER BIT DEFINITIONS (0X
HEIR PORT REGISTER BIT DEFINITIONS (0X
UR PORT REGISTER BIT DEFINITIONS (0X
UR PORT REGISTER BIT DEFINITIONS (0X
OCKET STATUS HIGH REGISTER BIT DEFINITIONS
OCKET STATUS HIGH REGISTER DESCRIPTION
IP A
HEIR
HEIR
HEIR
HEIR
ERIAL PORT REGISTER MAP
EADER STRUCTURE
DDRESS REGISTER BIT DEFINITIONS (0X
IP A
DDRESS REGISTER BIT DEFINITIONS (0X
IP A
DDRESS REGISTER BIT DEFINITIONS (0X
IP A
DDRESS REGISTER BIT DEFINITIONS (0X
ONTROL AND STATUS REGISTER BIT DEFINITIONS (0X
ONTROL STATUS REGISTER DESCRIPTION
NTERRUPT CODE REGISTER BIT DEFINITIONS
NTERRUPT ERROR CODES
AX RETRY REGISTER
TRING FORMAT
TRING EXAMPLE
Hardware Specification Revision 1.3
............................................................ 7-18
36) ................................................................ 7-19
37) ................................................................ 7-19
38)................................................................... 7-19
39)................................................................... 7-19
............................................................. 7-19
................................................................. 7-20
3C) ..................................................... 7-20
3D) ..................................................... 7-20
3E)...................................................... 7-20
3F)...................................................... 7-20
60) ........................................ 7-21
............................................................... 7-21
........................................................... 7-22
........................................................................................ 7-22
.............................................................................................. 7-22
....................................................................................................... 7-23
...................................................................................................... 7-23
................................................................................................ 8-1
.......................................................................................................... 8-5
Seiko Instruments Inc.
v
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
1. Introduction
1.1. Product Overview
The S-7600A is a LSI that integrates TCP/IP network stack. It offers your devices a quicker and easier
connectivity to a network with its on-chip serial interface and a static RAM that operates as a buffer.
Implementing this LSI into your system can significantly reduce y our software development cost. Also its
low operating frequency gives benefits to the power consumption.
The S-7600A also supports a microprocessor interface via the iReady iAPI
to Physical Transport Layer Interface. iAPI consists of a set of register and operating definitions that allow
any micro controller system to interface with the internal modules.
1.2. Features
z Industry standard protocols support :
TCP/IP (Ver. 4.0)
PPP (STD-51-compliant)
UDP
z General purpose sockets :
Configured for two sockets
z MPU interface :
68k/x80(MOTO/Intel) bus interface or Synchronous serial interface
z Physical Transport Layer Interface :
Universal Asynchronous Receiver/Transmitter (UART)
z Low clock rate :
Multiplied four by the bit-rate
z Operating frequency :
256kHz typical
z Low power consumption :
Full-transmitting Operating current consumption : 0.9mA typ.
Non-transmitting Operating current consumption : 150µA typ.
Standby current consumption : 1.0µA typ.
z Stand-by mode :
held by RESET signal
z Wide operating voltage range :
2. 4V to 3.6V
z Easier application development :
portable iAPI
TM
support
TM
register set, and connection
1.3. Benefits
z Off-loads MIPS allowing system to operate with low end and low cost processors.
z Consumes minimal power-up to 1/100 of competing solution.
Seiko Instruments Inc.
1-1
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
1.4. Trademarks
iReady iAPITM and iAPITM is a trademark of iReady Corporation. All other products and brand names are
trademarks and registered trademarks of their respective companies.
1.5. Definitions
z IP Internet Protocol
z PPP Point-to-Point Protocol
z TCP Transmission Control Protocol
z UDP User Datagram Protocol
z API Application Programming Interface
1.6. Applicable Documents
z S-7600A Functional Specification
z S-7600A API Application Manual
1.7. Cautions
1. DO NOT apply a voltage or current that exceeds the absolute maximum ratings to terminals. If
applied, the IC may malfunction or be destroyed.
The standard values are set with sufficient margins, but use the IC within the recommended
operating conditions to optimize device quality.
2. Measures against static electricity
2.1 When transporting or storing ICs, use conductive containers or metal coated boxes.
2.2 Check that there is no current leakage in electrical facilities, and be sure to ground them.
Also ensure that workbenches and people who handle ICs are grounded.
3. Excessive external noise to the power supply or I/O terminals of CMOS ICs causes latch-up, leading
to faults and damage. If latch-up has occurred, immediately turn off the device, eliminate the cause,
and turn on the device again.
4. Keep the IC away from mechanical vibration, shock, and sudden changes in temperature. These
may cause wires to break.
5. Environment
5.1 Use and store ICs below the absolute maximum rated temperature.
5.2 DO NOT use or store ICs where condensation can occur.
5.3 DO NOT use ICs where they are directly exposed to dust, salt, or acid gas such as SO
These may cause leaks between element leads and cause corrosion.
5.4 To store ICs for a long time, DO NOT process them. During storage, DO NOT apply any load
to ICs.
.
2
1-2
Seiko Instruments Inc.
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
2. Functional Block Diagram
Figure 2-1 shows a functional block diagram of the S-7600A. There are blocks of the Network Stack and
other functions related to it. The S-7600A has the interface for a host MPU and a Physical layer for
various data terminal equipment.
SD(7:0)
CS
PSX
C86
RS
READX
WRITEX
BUSYX
INTCTL
INT1
INT2X
CLK
RESETX
MPU Interface
Network Stack
UDP TCP
IP
PPP
Physical Layer
Interface
16-byte
FIFO
1-byte
BUFFER
SRAM
10Kbytes
SRAM Interface
S2P
DSRXRIRXD
RTSX
The transport and network layers contain:
z Two general sockets that provide connectivity between the application layer and the transport layer.
z TCP/UDP module that allows for reliable (retransmission) and unreliable (no retransmission)
datagram deliveries.
z IP module that provides connectionless packet delivery.
z PPP module that provides point-to-point connection link between two hosts.
Figure 2-1 Block Diagram
Seiko Instruments Inc.
P2S
DCD
DTRX
TXD
CTSX
2-1
TCP/IP Network Stack LSI
S-7600A
3. Terminals
Hardware Specification Revision 1.3
3.1.
Pin Assignment
Figure 3-1 shows Pin Assignment in Package.
36 25
INT1
INT2X
BUSYX
SD7
37
NC
TI2
SD6
TI1
VDD
SD5
SD4
SD3
SD2
SD1
48
SD0
RESETX
CLK
TEST
Figure 3-1Pin Assignment
1
INTCTRL
VSS
WRITEX
CTSX
READX
C86
VSS
PSX
TI4
24
TI5
TI6
TI7
VDD
TO1
TO2
TO3
TO4
TO5
TO6
TO7
13
TXD
RTSX
DTRX
DCD
RXD
RI
DSRX
12
TI3
RS
CS
Table 3-1 shows signal names, listed by Pin Number.
Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
1 RESETX 13 TO7 25 TI3 37 SD7
2 TEST 14 TO6 26 RS 38 NC
3 CLK 15 TO5 27 CS 39 TI2
4 VSS 16 TO4 28 C86 40 SD6
5 CTSX 17 TO3 29 READX 41 TI1
6 DSRX 18 TO2 30 VSS 42 VDD
7 RI 19 TO1 31 PSX 43 SD5
8 RXD 20 VDD 32 WRITEX 44 SD4
9 DCD 21 TI7 33 INTCTRL 45 SD3
10 DTRX 22 TI6 34 INT1 46 SD2
11 RTSX 23 TI5 35 INT2X 47 SD1
12 TXD 24 TI4 36 BUSYX 48 SD0
Table 3-1 Pin Assignment
3-1
Seiko Instruments Inc.
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
3.2. Package Dimensions
S-7600A is housed in a 48-pin QFP package with 0.5mm pin pitch spacing. The package layout is
depicted in Figure 3-2.
9.0±0 .3
.3
0
7.0
2536
5±
0.
.3
0
0±
9.
0
7.
37
48
24
13
112
0
.2
0
0±
4
1.
.
0.15
+0.10
-0.06
+0.10
0.20
-0.05
Figure 3-2 Package Dimensions
0.50
Seiko Instruments Inc.
0
2
0.
0~
max
1.7
UNIT:mm
3-2
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
3.3. Pin Description
The pins and signal descriptions are listed by function in Table 3-2.
Name I/O Description Type
VDD1,VDD2 - Positive power supply
VSS1,VSS2 - GND potential
RESETX I Reset input A
TEST,
TI1 to TI7
TO1 to TO7 O Test output
CLK I Clock input C
CTSX I Clear to send input C
DSRX I Data set ready input C
RI I Ring indicator input C
RXD I Serial received data input C
DCD I Data carrier detect input C
DTRX O Data terminal ready output D
RTSX O Request to send output D
TXD O Serial transmit data output D
RS I Register selection input C
CS I Chip selection input C
C86 I MPU interface mode selection input
READX I x80 mode : read requirement input
PSX I parallel/serial interface selection input C
WRITEX I x80 mode : write requirement input
INTCTRL I INT1/INT2X drive type(CMOS/OD) selection input C
INT1 *OT Interrupt output(active High) from S-7600A chip to MPU E
INT2X *OT Interrupt output(active Low) from S-7600A chip to MPU E
BUSYX O busy indicator output D
SD7 *B x80/68k mode : data bus
SD6 *B x80/68k mode : data bus
SD5 *B x80/68k mode : data bus
SD0 to SD4 *B Data bus F
I Test input (pull-down resistor is built in)
When normal use, connect to V
When normal use, open
68k mode : 1
x80 mode : 0
68k mode : enable input
68k/Serial mode : read/write selection input
Serial mode : serial data input
Serial mode : serial clock input
Serial mode : serial data output
*OT : Tri-state output
*B : bi-directional
Table 3-2 Pin Description
or open
SS
B
D
C
C
C
F
F
F
3-3
Seiko Instruments Inc.
TCP/IP Network Stack LSI
S-7600A
3.4. Pin Configuration
Figure 3-3 shows configuration of each pin.
A
pad pad
cin
B
Hardware Specification Revision 1.3
cin
Vss
C
E
pad
cin
D
F
pad
in
cin
padpad
inin
oenoen
Figure 3-3 Configuration of Each Pin
Seiko Instruments Inc.
3-4
TCP/IP Network Stack LSI
S-7600A
4. Electrical Characteristics
4.1. Absolute Maximum Ratings
Parameter Symbol Conditions Rating Unit
Hardware Specification Revision 1.3
Storage temperature T
Operating temperature T
Power supply voltage V
Input voltage V
Output voltage V
Table 4-1 Absolute Maximum Ratings
sta
opr
DD
IN
OUT
-40 to +125
-40 to +85
Ta=25°C
Ta=25°C
Ta=25°C
4.2. Recommended Operating Conditions
Parameter Symbol Conditions Min. Typ. Max. Unit Note
Operating Frequency
range
Clock Pulse
width
Operating voltage
range
F
V
OPR
Pw
DD
Ta=-40 to +85°C
Ta=-40 to +85°C
Ta=-40 to +85°C
°C
°C
-0.3 to +4.0 V
V
-0.3 to VDD+0.3 V
SS
V
SS
to V
DD
V
- 0.256 5 MHz 1
80 - - nS
2.4 - 3.6 V
Input voltage V
Note1: The clock is given by the CLK pin and needs to be as four times or more fast as the BAUD rate.
(The multiplier is an integer whose tolerance is <±2%)
IN
Ta=-40 to +85°C
0 - V
DD
V
Table 4-2 Recommended Operating Conditions
4-1
Seiko Instruments Inc.
TCP/IP Network Stack LSI
S-7600A
4.3. DC Characteristics
Parameter Symbol Conditions Min. Typ. Max. Unit
Hardware Specification Revision 1.3
Unless otherwise specified: VDD=3.0V, VSS=0V, Ta=25°C
Low level input
voltage
High level input
voltage
Low level input
leakage current
High level input
leakage current
High level input
current
Low level output
current
High level output
current
Schmitt Hysteresis
voltage
V
IL
V
IH
I
LL
I
LH
All input terminals without
0.2×
V
- -
VIN=V
SS
-1.0 - 1.0 µA
-1.0 - 1.0 µA
DD
- - V
0.8×
V
DD
V
pull-down resister
V
IN=VDD
I
IH
All input terminals with
18 70 220 µA
pull-down resister
V
IN=VDD
I
OL
I
OH
V
WD
VOL=0.4V 5.0 - - mA
VOH=2.6V - - -3.5 mA
- 0.46 - V
Table 4-3 DC Characteristics
4.4. Power Current Consumption
Parameter Symbol Conditions Min. Typ. Max. Unit
Full-transmitting
Operating current
consumption
Non-transmitting
Operating current
consumption
Standby current
consumption
I
DD1
I
DD2
Is
Table 4-4 Power Current Consumption
Unless otherwise specified: VDD=3.0V, VSS=0V, Ta=25°C
Ta=-40 to +85°C
=256KHz
F
OPR
Ta=-40 to +85°C
=256KHz
F
OPR
RESETX=V
SS
Ta=-10 to +70°C
- 0.9 2.2 mA
- 150 300 µA
- 1.0 15.0
µA
Ta=-40 to +85°C
30.0
Seiko Instruments Inc.
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S-7600A
Hardware Specification Revision 1.3
5. MPU Interface
5.1. Overview
The S-7600A supports two MPU interfaces: parallel and serial. In parallel interface mode, S-7600A can
interface with x80 Family MPU or 68k Family MPU.
PSX CS RS READXWRITEX BUSYX C86 SD7 SD6 SD5 SD4 to SD0
H:
parallel x80
H:
parallel 68k
L:
serial
CS RS READXWRITEX BUSYX
CS RS
CS RS H or L R/WX BUSYX H or L SI SCL SO
E R/WX BUSYX H D7 D6 D5 D4 to D0
Table 5-1 Interface Selection
L D7 D6 D5 D4 to D0
Hi-Z
5.2. Parallel Interface
Setting PSX to “H” select the parallel interface. In parallel interface mode the S-7600A can interface with
either x80 Family MPU or 68k Family MPU. The desired MPU mode can be selected by setting the C86
pin to “H” or “L”.
RS 68k Family MPU
R/WX
1
1
0
0
1
0
1
0
Table 5-2 Connection Relationship between MPU and Pins
x80 Family MPU
READX WRITEX
0
1
0
1
1
0
1
0
Function
Read Register
Write Register
Read Index Register
Write Index Register
5-1
Seiko Instruments Inc.
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