S-7600A TCP/IP NETWORK STACK LSI - Revision 1.3
Hardware Specification
S-7600A
TCP/IP Network Stack LSI
Components Marketing Dept.
Marketing Section 2
Phone +81-43-211-1028
Fax +81-43-211-8035
8, Nakase 1-chome, Mihama-ku
Chiba-shi, Chiba 261-8507, Japan
Seiko Instruments Inc.
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
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TABLE OF CONTENTS |
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1. |
INTRODUCTION........................................................................................................................... |
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1-1 |
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1.1. |
PRODUCT OVERVIEW ............................................................................................................... |
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1-1 |
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1.2. |
FEATURES ............................................................................................................................... |
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1-1 |
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1.3. |
BENEFITS................................................................................................................................. |
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1-1 |
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1.4. |
TRADEMARKS........................................................................................................................... |
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1-2 |
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1.5. |
DEFINITIONS ............................................................................................................................ |
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1-2 |
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1.6. |
APPLICABLE DOCUMENTS ......................................................................................................... |
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1-2 |
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1.7. |
CAUTIONS................................................................................................................................ |
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1-2 |
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2. |
FUNCTIONAL BLOCK DIAGRAM ............................................................................................... |
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2-1 |
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3. |
TERMINALS |
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3-1 |
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3.1. |
PIN ASSIGNMENT...................................................................................................................... |
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3-1 |
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3.2. |
PACKAGE .............................................................................................................DIMENSIONS |
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3-2 |
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3.3. |
PIN DESCRIPTION..................................................................................................................... |
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3-3 |
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3.4. |
PIN CONFIGURATION ................................................................................................................ |
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3-4 |
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4. |
ELECTRICAL .............................................................................................CHARACTERISTICS |
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4-1 |
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4.1. |
ABSOLUTE ..................................................................................................MAXIMUM RATINGS |
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4-1 |
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4.2. RECOMMENDED .................................................................................OPERATING CONDITIONS |
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4-1 |
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4.3. |
DC CHARACTERISTICS ............................................................................................................. |
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4-2 |
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4.4. |
POWER C .............................................................................................URRENT CONSUMPTION |
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4-2 |
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5. |
MPU INTERFACE......................................................................................................................... |
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5-1 |
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5.1. |
OVERVIEW ............................................................................................................................... |
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5-1 |
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5.2. |
PARALLEL ...............................................................................................................INTERFACE |
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5-1 |
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5.2.1. |
68k ....................................................................................................Family MPU Mode |
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5-2 |
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5.2.1.1. ................................................................................................................ |
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5-2 |
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5.2.1.2. ................................................................................................................ |
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5-3 |
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5.2.2. x80 ....................................................................................................Family MPU Mode |
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5-4 |
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5.2.2.1. ................................................................................................................ |
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5-4 |
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5.2.2.2. ................................................................................................................ |
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5-5 |
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5.3. |
SERIAL INTERFACE ................................................................................................................... |
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5-6 |
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5.3.1. |
Write ..........................................................................................................Cycle Timing |
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5-6 |
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5.3.2. |
Read ..........................................................................................................Cycle Timing |
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5-7 |
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5.4. |
INTERRUPT............................................................................................................................... |
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5-8 |
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6. |
MEMORY REQUIREMENTS ........................................................................................................ |
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6-1 |
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6.1. |
OVERVIEW ............................................................................................................................... |
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6-1 |
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6.2. |
MEMORY ........................................................................................INTERFACE ARCHITECTURE |
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6-1 |
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6.3. |
MEMORY ..........................................................................................................................MAP |
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6-2 |
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7. |
S-7600A REGISTER .............................................................................................DEFINITIONS |
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7-1 |
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7.1. |
OVERVIEW ............................................................................................................................... |
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7-1 |
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7.2. |
IAPI REGISTER .................................................................................................................MAP |
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7-1 |
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7.3. |
REGISTER ............................................................................................................DEFINITIONS |
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7-4 |
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7.3.1. |
Revision ................................................................................................Register (0x00) |
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7-4 |
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7.3.2. |
General ....................................................................................Control Register (0x01) |
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7-4 |
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7.3.3. |
Generic ......................................................................Socket Location Register |
(0x02) |
7-5 |
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7.3.4. |
Master ..................................................................................................Interrupt (0x04) |
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7-5 |
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7.3.5. |
Serial .........................................................Port Configuration / Status Register (0x08) |
7-6 |
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7.3.6. |
Serial ..............................................................................Port Interrupt Register (0x09) |
7-8 |
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7.3.7. |
Serial ....................................................................Port Interrupt Mask Register |
(0x0A) |
7-8 |
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7.3.8. |
Serial ....................................................................................Port Data Register (0x0B) |
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7-9 |
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7.3.9. |
BAUD ...................................................................Rate Divider Registers (0x0C-0x0D) |
7-9 |
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Seiko Instruments Inc. |
i |
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
7.3.10. |
Our IP Address Registers |
(0x10-0x13) ...................................................................... |
7-9 |
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7.3.11. |
Clock Divider Registers (0x1C-0x1D) ...................................................................... |
7-10 |
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7.3.12. |
Index Register (0x20) ............................................................................................... |
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7-10 |
7.3.13. |
Type of Service Register (TOS) (0x21).................................................................... |
7-10 |
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7.3.14. |
Socket Config Status Low Register (0x22)............................................................... |
7-11 |
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7.3.15. |
Socket Status Mid Register |
(0x23)........................................................................... |
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7-13 |
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7.3.16. |
Socket Activate Register |
(0x24) ............................................................................... |
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7-14 |
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7.3.17. |
Socket Interrupt Register |
(0x26) .............................................................................. |
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7-14 |
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7.3.18. |
Socket Data Available Register (0x28)..................................................................... |
7-15 |
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7.3.19. |
Socket Interrupt Mask Low Register |
(0x2A)............................................................. |
7-16 |
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7.3.20. |
Socket Interrupt Mask High Register |
(0x2B)............................................................ |
7-16 |
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7.3.21. |
Socket Interrupt Low Register |
(0x2C) ...................................................................... |
7-17 |
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7.3.22. |
Socket Interrupt High Register |
(0x2D) ..................................................................... |
7-17 |
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7.3.23. |
Socket Data Register (0x2E).................................................................................... |
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7-18 |
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7.3.24. |
TCP Data Send and Buffer Out Length Registers (0x30-0x31) ............................... |
7-18 |
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7.3.25. |
Buffer In Length Registers (0x32-0x33) ................................................................... |
7-18 |
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7.3.26. |
Urgent Data Pointer Registers |
(0x34-0x35) ............................................................. |
7-18 |
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7.3.27. |
Their Port Registers (0x36-0x37) ............................................................................. |
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7-19 |
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7.3.28. |
Our Port Registers (0x38-0x39) ............................................................................... |
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7-19 |
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7.3.29. |
Socket Status High Register |
(0x3A)......................................................................... |
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7-19 |
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7.3.30. |
Their IP Address Registers |
(0x3C-0x3F) ................................................................. |
7-20 |
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7.3.31. |
PPP Control and Status Register (0x60).................................................................. |
7-21 |
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7.3.32. |
PPP Interrupt Code (0x61) ....................................................................................... |
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7-22 |
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7.3.33. |
PPP Max Retry, (0x62).............................................................................................. |
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7-22 |
7.3.34. |
PAP String (0x64)..................................................................................................... |
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7-23 |
8. DATA COMMUNICATIONS.......................................................................................................... |
8-1 |
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8.1. |
OVERVIEW ............................................................................................................................... |
8-1 |
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8.2. SERIAL PORT REGISTER MAP ................................................................................................... |
8-1 |
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8.2.1. Hardware Flow Control (RTS/CTS Handshaking) .......................................................... |
8-2 |
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8.2.2. |
Serial Port Control........................................................................................................... |
8-2 |
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8.3. |
TCP/UDP DATA COMMUNICATIONS.......................................................................................... |
8-3 |
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8.3.1. |
TCP Data Communications ............................................................................................ |
8-3 |
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8.3.2. |
UDP Data Communications............................................................................................ |
8-4 |
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9. RESET FUNCTIONS .................................................................................................................... |
9-1 |
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9.1. OVERVIEW ............................................................................................................................... |
9-1 |
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9.1.1. |
Hardware Reset Function ............................................................................................... |
9-1 |
9.1.2. |
Software Reset Function................................................................................................. |
9-1 |
10. APPLICATION EXAMPLES........................................................................................................ |
10-1 |
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10.1.1. In Case of x80 Family MPU with LCD Controller .......................................................... |
10-1 |
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10.1.2. |
In Case of 68k Family MPU with LCD Controller .......................................................... |
10-2 |
10.1.3. |
In Case of Serial Interface with LCD Controller ............................................................ |
10-3 |
ii |
Seiko Instruments Inc. |
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
LIST OF FIGURES
FIGURE 2-1 |
BLOCK DIAGRAM ............................................................................................................... |
2-1 |
FIGURE 3-1 |
PIN ASSIGNMENT .............................................................................................................. |
3-1 |
FIGURE 3-2 |
PACKAGE DIMENSIONS ...................................................................................................... |
3-2 |
FIGURE 3-3 |
CONFIGURATION OF EACH PIN ........................................................................................... |
3-4 |
FIGURE 5-1 |
68K FAMILY MPU WRITE TIMING ....................................................................................... |
5-2 |
FIGURE 5-2 |
68K FAMILY MPU READ TIMING......................................................................................... |
5-3 |
FIGURE 5-3 |
X80 FAMILY MPU WRITE CYCLE TIMING............................................................................ |
5-4 |
FIGURE 5-4 |
X80 FAMILY MPU READ CYCLE TIMING.............................................................................. |
5-5 |
FIGURE 5-5 |
SERIAL INTERFACE WRITE TIMING ..................................................................................... |
5-6 |
FIGURE 5-6 |
SERIAL INTERFACE READ TIMING ....................................................................................... |
5-7 |
FIGURE 5-7 |
INT1 INTERRUPT TIMING ................................................................................................... |
5-8 |
FIGURE 6-1 |
MEMORY INTERFACE ARCHITECTURE ................................................................................. |
6-1 |
FIGURE 8-1 |
SERIAL DATA FORMAT....................................................................................................... |
8-1 |
FIGURE 9-1 |
HARDWARE RESET TIMING ................................................................................................ |
9-1 |
FIGURE 9-2 |
SOFTWARE RESET TIMING................................................................................................. |
9-1 |
FIGURE 10-1 |
EXAMPLE FOR X80 FAMILY MPU...................................................................................... |
10-1 |
FIGURE 10-2 |
EXAMPLE FOR 68K FAMILY MPU...................................................................................... |
10-2 |
FIGURE 10-3 |
EXAMPLE FOR SERIAL INTERFACE .................................................................................... |
10-3 |
Seiko Instruments Inc. |
iii |
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
LIST OF TABLES
TABLE 3-1 PIN ASSIGNMENT .................................................................................................................. |
3-1 |
TABLE 3-2 PIN DESCRIPTION.................................................................................................................. |
3-3 |
TABLE 4-1 ABSOLUTE MAXIMUM RATINGS .............................................................................................. |
4-1 |
TABLE 4-2 RECOMMENDED OPERATING CONDITIONS .............................................................................. |
4-1 |
TABLE 4-3 DC CHARACTERISTICS .......................................................................................................... |
4-2 |
TABLE 4-4 POWER CURRENT CONSUMPTION.......................................................................................... |
4-2 |
TABLE 5-1 INTERFACE SELECTION.......................................................................................................... |
5-1 |
TABLE 5-2 CONNECTION RELATIONSHIP BETWEEN MPU AND PINS .......................................................... |
5-1 |
TABLE 5-3 68K FAMILY MPU WRITE CYCLE TIMING................................................................................ |
5-2 |
TABLE 5-4 68K FAMILY MPU READ CYCLE TIMING ................................................................................. |
5-3 |
TABLE 5-5 X80 FAMILY MPU WRITE CYCLE TIMING................................................................................ |
5-4 |
TABLE 5-6 X80 FAMILY MPU READ CYCLE TIMING ................................................................................. |
5-5 |
TABLE 5-7 SERIAL INTERFACE WRITE CYCLE TIMING .............................................................................. |
5-6 |
TABLE 5-8 SERIAL INTERFACE READ CYCLE TIMING................................................................................ |
5-7 |
TABLE 5-9 INTERRUPT SELECTION TABLE ............................................................................................... |
5-8 |
TABLE 6-1 S-7600A MEMORY MAP (BANK 0) ......................................................................................... |
6-2 |
TABLE 6-2 S-7600A MEMORY MAP (BANK 1) ......................................................................................... |
6-2 |
TABLE 7-1 IAPI REGISTER MAP ............................................................................................................. |
7-2 |
TABLE 7-2 IAPI REGISTER MAP (CONTINUED) ........................................................................................ |
7-3 |
TABLE 7-3 REVISION REGISTER BIT DEFINITIONS.................................................................................... |
7-4 |
TABLE 7-4 REVISION REGISTER DESCRIPTION ........................................................................................ |
7-4 |
TABLE 7-5 GENERAL CONTROL REGISTER BIT DEFINITIONS .................................................................... |
7-4 |
TABLE 7-6 GENERAL CONTROL REGISTER DESCRIPTION......................................................................... |
7-4 |
TABLE 7-7 GENERIC SOCKET LOCATION REGISTER BIT DEFINITIONS ....................................................... |
7-5 |
TABLE 7-8 GENERIC SOCKET LOCATION REGISTER DESCRIPTION ........................................................... |
7-5 |
TABLE 7-9 MASTER INTERRUPT REGISTER BIT DEFINITIONS.................................................................... |
7-5 |
TABLE 7-10 MASTER INTERRUPT REGISTER DESCRIPTIONS (CONTINUED) ............................................... |
7-6 |
TABLE 7-11 CONF STATUS REGISTER BIT DEFINITIONS........................................................................... |
7-6 |
TABLE 7-12 CONF STATUS REGISTER DESCRIPTION ............................................................................... |
7-7 |
TABLE 7-13 SERIAL PORT INTERRUPT REGISTER BIT DEFINITIONS .......................................................... |
7-8 |
TABLE 7-14 SERIAL PORT INTERRUPT REGISTER DESCRIPTION............................................................... |
7-8 |
TABLE 7-15 SERIAL PORT INTERRUPT MASK REGISTER BIT DEFINITIONS................................................. |
7-8 |
TABLE 7-16 SERIAL PORT INTERRUPT MASK REGISTER DESCRIPTION ..................................................... |
7-8 |
TABLE 7-17 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X10) .......................................................... |
7-9 |
TABLE 7-18 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X11) .......................................................... |
7-9 |
TABLE 7-19 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X12) ........................................................ |
7-10 |
TABLE 7-20 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X13) ........................................................ |
7-10 |
TABLE 7-21 INDEX REGISTER BIT DEFINITION ....................................................................................... |
7-10 |
TABLE 7-22 INDEX REGISTER DESCRIPTION.......................................................................................... |
7-10 |
TABLE 7-23 SOCKET CONFIG STATUS LOW REGISTER BIT DEFINITIONS ................................................ |
7-11 |
TABLE 7-24 SOCKET CONFIG STATUS LOW REGISTER DESCRIPTION..................................................... |
7-12 |
TABLE 7-25 SOCKET STATUS MID REGISTER BIT DEFINITIONS .............................................................. |
7-13 |
TABLE 7-26 SOCKET STATUS MID REGISTER DESCRIPTION................................................................... |
7-13 |
TABLE 7-27 SOCKET ACTIVATE REGISTER BIT DEFINITIONS .................................................................. |
7-14 |
TABLE 7-28 SOCKET ACTIVATE REGISTER DESCRIPTION....................................................................... |
7-14 |
TABLE 7-29 SOCKET INTERRUPT REGISTER BIT DEFINITIONS ................................................................ |
7-14 |
TABLE 7-30 SOCKET INTERRUPT REGISTER DESCRIPTION .................................................................... |
7-15 |
TABLE 7-31 SOCKET DATA AVAIL REGISTER BIT DEFINITIONS ............................................................... |
7-15 |
TABLE 7-32 SOCKET DATA AVAIL REGISTER DESCRIPTION ................................................................... |
7-15 |
TABLE 7-33 SOCKET INTERRUPT MASK LOW REGISTER BIT DEFINITIONS .............................................. |
7-16 |
TABLE 7-34 SOCKET INTERRUPT MASK LOW REGISTER DESCRIPTION................................................... |
7-16 |
TABLE 7-35 SOCKET INTERRUPT MASK HIGH REGISTER BIT DEFINITIONS.............................................. |
7-16 |
TABLE 7-36 SOCKET INTERRUPT MASK HIGH REGISTER DESCRIPTION .................................................. |
7-16 |
TABLE 7-37 SOCKET INTERRUPT LOW REGISTER BIT DEFINITIONS ........................................................ |
7-17 |
TABLE 7-38 SOCKET INTERRUPT LOW REGISTER DESCRIPTION............................................................. |
7-17 |
TABLE 7-39 SOCKET INTERRUPT HIGH REGISTER BIT DEFINITIONS ....................................................... |
7-17 |
iv |
Seiko Instruments Inc. |
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
TABLE 7-40 SOCKET INTERRUPT HIGH REGISTER DESCRIPTION............................................................ |
7-18 |
TABLE 7-41 THEIR PORT REGISTER BIT DEFINITIONS (0X36) ................................................................ |
7-19 |
TABLE 7-42 THEIR PORT REGISTER BIT DEFINITIONS (0X37) ................................................................ |
7-19 |
TABLE 7-43 OUR PORT REGISTER BIT DEFINITIONS (0X38)................................................................... |
7-19 |
TABLE 7-44 OUR PORT REGISTER BIT DEFINITIONS (0X39)................................................................... |
7-19 |
TABLE 7-45 SOCKET STATUS HIGH REGISTER BIT DEFINITIONS............................................................. |
7-19 |
TABLE 7-46 SOCKET STATUS HIGH REGISTER DESCRIPTION................................................................. |
7-20 |
TABLE 7-47 THEIR IP ADDRESS REGISTER BIT DEFINITIONS (0X3C) ..................................................... |
7-20 |
TABLE 7-48 THEIR IP ADDRESS REGISTER BIT DEFINITIONS (0X3D) ..................................................... |
7-20 |
TABLE 7-49 THEIR IP ADDRESS REGISTER BIT DEFINITIONS (0X3E)...................................................... |
7-20 |
TABLE 7-50 THEIR IP ADDRESS REGISTER BIT DEFINITIONS (0X3F)...................................................... |
7-20 |
TABLE 7-51 PPP CONTROL AND STATUS REGISTER BIT DEFINITIONS (0X60) ........................................ |
7-21 |
TABLE 7-52 PPP CONTROL STATUS REGISTER DESCRIPTION ............................................................... |
7-21 |
TABLE 7-53 PPP INTERRUPT CODE REGISTER BIT DEFINITIONS ........................................................... |
7-22 |
TABLE 7-54 PPP INTERRUPT ERROR CODES........................................................................................ |
7-22 |
TABLE 7-55 PPP MAX RETRY REGISTER.............................................................................................. |
7-22 |
TABLE 7-56 PAP STRING FORMAT ....................................................................................................... |
7-23 |
TABLE 7-57 PAP STRING EXAMPLE...................................................................................................... |
7-23 |
TABLE 8-1 SERIAL PORT REGISTER MAP ................................................................................................ |
8-1 |
TABLE 8-12 HEADER STRUCTURE .......................................................................................................... |
8-5 |
Seiko Instruments Inc. |
v |
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
1. Introduction
1.1. Product Overview
The S-7600A is a LSI that integrates TCP/IP network stack. It offers your devices a quicker and easier connectivity to a network with its on-chip serial interface and a static RAM that operates as a buffer. Implementing this LSI into your system can significantly reduce your software development cost. Also its low operating frequency gives benefits to the power consumption.
The S-7600A also supports a microprocessor interface via the iReady iAPITM register set, and connection to Physical Transport Layer Interface. iAPI consists of a set of register and operating definitions that allow any micro controller system to interface with the internal modules.
1.2. Features
zIndustry standard protocols support :
TCP/IP |
(Ver. 4.0) |
PPP |
(STD-51-compliant) |
UDP |
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zGeneral purpose sockets : Configured for two sockets
zMPU interface :
68k/x80(MOTO/Intel) bus interface or Synchronous serial interface
zPhysical Transport Layer Interface :
Universal Asynchronous Receiver/Transmitter (UART)
zLow clock rate :
Multiplied four by the bit-rate
zOperating frequency : 256kHz typical
zLow power consumption :
Full-transmitting Operating current consumption : 0.9mA typ. Non-transmitting Operating current consumption : 150µA typ. Standby current consumption : 1.0µA typ.
zStand-by mode : held by RESET signal
zWide operating voltage range :
2.4V to 3.6V
zEasier application development : portable iAPITM support
1.3. Benefits
zOff-loads MIPS allowing system to operate with low end and low cost processors.
zConsumes minimal power-up to 1/100 of competing solution.
Seiko Instruments Inc. |
1-1 |
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
1.4. Trademarks
iReady iAPITM and iAPITM is a trademark of iReady Corporation. All other products and brand names are trademarks and registered trademarks of their respective companies.
1.5. Definitions
z IP |
Internet Protocol |
zPPP Point-to-Point Protocol
z |
TCP |
Transmission Control Protocol |
z |
UDP |
User Datagram Protocol |
z |
API |
Application Programming Interface |
1.6. Applicable Documents
zS-7600A Functional Specification
zS-7600A API Application Manual
1.7. Cautions
1.DO NOT apply a voltage or current that exceeds the absolute maximum ratings to terminals. If applied, the IC may malfunction or be destroyed.
The standard values are set with sufficient margins, but use the IC within the recommended operating conditions to optimize device quality.
2.Measures against static electricity
2.1When transporting or storing ICs, use conductive containers or metal coated boxes.
2.2Check that there is no current leakage in electrical facilities, and be sure to ground them. Also ensure that workbenches and people who handle ICs are grounded.
3.Excessive external noise to the power supply or I/O terminals of CMOS ICs causes latch-up, leading to faults and damage. If latch-up has occurred, immediately turn off the device, eliminate the cause, and turn on the device again.
4.Keep the IC away from mechanical vibration, shock, and sudden changes in temperature. These may cause wires to break.
5.Environment
5.1Use and store ICs below the absolute maximum rated temperature.
5.2DO NOT use or store ICs where condensation can occur.
5.3DO NOT use ICs where they are directly exposed to dust, salt, or acid gas such as SO2. These may cause leaks between element leads and cause corrosion.
5.4To store ICs for a long time, DO NOT process them. During storage, DO NOT apply any load to ICs.
1-2 |
Seiko Instruments Inc. |
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
2. Functional Block Diagram
Figure 2-1 shows a functional block diagram of the S-7600A. There are blocks of the Network Stack and other functions related to it. The S-7600A has the interface for a host MPU and a Physical layer for various data terminal equipment.
SD(7:0)
CS
PSX
C86
RS 
READX 
WRITEX
BUSYX 
INTCTL 
INT1 
INT2X 
CLK
RESETX
MPU Interface
Network Stack
UDP 
TCP
IP
PPP
Physical Layer
Interface
16-byte 1-byte FIFO BUFFER
S2P P2S
SRAM Interface
SRAM
10Kbytes
DSRX RTSX RXD RI DCD DTRX TXD CTSX |
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Figure 2-1 |
Block Diagram |
The transport and network layers contain:
zTwo general sockets that provide connectivity between the application layer and the transport layer.
zTCP/UDP module that allows for reliable (retransmission) and unreliable (no retransmission) datagram deliveries.
zIP module that provides connectionless packet delivery.
zPPP module that provides point-to-point connection link between two hosts.
Seiko Instruments Inc. |
2-1 |
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
3. Terminals
3.1. Pin Assignment
Figure 3-1 shows Pin Assignment in Package.
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36 |
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25 |
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BUSYX |
INT2X |
INT1 |
INTCTRL |
WRITEX |
PSX |
VSS |
READX |
C86 |
CS |
RS |
TI3 |
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37 |
SD7 |
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NC |
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TI2 |
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SD6 |
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TI1 |
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VDD |
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SD5 |
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SD4 |
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SD3 |
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SD2 |
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SD1 |
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48 |
SD0 |
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RESETX |
TEST |
CLK |
VSS |
CTSX |
DSRX |
RI |
RXD |
DCD |
DTRX |
RTSX |
TXD |
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1 |
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12 |
||||
Figure 3-1Pin Assignment
Table 3-1 shows signal names, listed by Pin Number.
TI4 24
TI5
TI6
TI7
VDD
TO1
TO2
TO3
TO4
TO5
TO6
TO7 13
Pin No. |
Pin name |
Pin No. |
|
Pin name |
Pin No. |
Pin name |
Pin No. |
Pin name |
1 |
RESETX |
13 |
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TO7 |
25 |
TI3 |
37 |
SD7 |
2 |
TEST |
14 |
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TO6 |
26 |
RS |
38 |
NC |
3 |
CLK |
15 |
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TO5 |
27 |
CS |
39 |
TI2 |
4 |
VSS |
16 |
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TO4 |
28 |
C86 |
40 |
SD6 |
5 |
CTSX |
17 |
|
TO3 |
29 |
READX |
41 |
TI1 |
6 |
DSRX |
18 |
|
TO2 |
30 |
VSS |
42 |
VDD |
7 |
RI |
19 |
|
TO1 |
31 |
PSX |
43 |
SD5 |
8 |
RXD |
20 |
|
VDD |
32 |
WRITEX |
44 |
SD4 |
9 |
DCD |
21 |
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TI7 |
33 |
INTCTRL |
45 |
SD3 |
10 |
DTRX |
22 |
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TI6 |
34 |
INT1 |
46 |
SD2 |
11 |
RTSX |
23 |
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TI5 |
35 |
INT2X |
47 |
SD1 |
12 |
TXD |
24 |
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TI4 |
36 |
BUSYX |
48 |
SD0 |
|
|
Table 3-1 |
Pin Assignment |
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||
3-1 |
Seiko Instruments Inc. |
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
3.2. Package Dimensions
S-7600A is housed in a 48-pin QFP package with 0.5mm pin pitch spacing. The package layout is depicted in Figure 3-2.
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9.0±0.3 |
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0.3 |
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7.0 |
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0.5± |
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36 |
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25 |
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24 |
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9.0±0.3 |
7.0 |
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0.15 |
+0.10 |
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1 |
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12 |
1.40±0.20 |
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-0.06 |
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0.20 |
+0.10 |
0.50 |
-0.05 |
0~0.20
UNIT:mm
Figure 3-2 |
Package Dimensions |
Seiko Instruments Inc. |
3-2 |
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
3.3. Pin Description
The pins and signal descriptions are listed by function in Table 3-2.
Name |
I/O |
|
Description |
Type |
VDD1,VDD2 |
- |
Positive power supply |
|
|
VSS1,VSS2 |
- |
GND potential |
|
|
RESETX |
I |
Reset input |
|
A |
TEST, |
I |
Test input (pull-down resistor is built in) |
B |
|
TI1 to TI7 |
|
When normal use, connect to VSS or open |
|
|
TO1 to TO7 |
O |
Test output |
|
D |
|
|
When normal use, open |
|
|
CLK |
I |
Clock input |
|
C |
CTSX |
I |
Clear to send input |
|
C |
DSRX |
I |
Data set ready input |
|
C |
RI |
I |
Ring indicator input |
|
C |
RXD |
I |
Serial received data input |
C |
|
DCD |
I |
Data carrier detect input |
C |
|
DTRX |
O |
Data terminal ready output |
D |
|
RTSX |
O |
Request to send output |
D |
|
TXD |
O |
Serial transmit data output |
D |
|
RS |
I |
Register selection input |
C |
|
CS |
I |
Chip selection input |
|
C |
C86 |
I |
MPU interface mode selection input |
C |
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68k mode : 1 |
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x80 mode : 0 |
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READX |
I |
x80 mode : read requirement input |
C |
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68k mode : enable input |
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PSX |
I |
parallel/serial interface selection input |
C |
|
WRITEX |
I |
x80 mode : write requirement input |
C |
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68k/Serial mode : read/write selection input |
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INTCTRL |
I |
INT1/INT2X drive type(CMOS/OD) selection input |
C |
|
INT1 |
*OT |
Interrupt output(active High) from S-7600A chip to MPU |
E |
|
INT2X |
*OT |
Interrupt output(active Low) from S-7600A chip to MPU |
E |
|
BUSYX |
O |
busy indicator output |
|
D |
SD7 |
*B |
x80/68k mode : data bus |
F |
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Serial mode : serial data input |
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SD6 |
*B |
x80/68k mode : data bus |
F |
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Serial mode : serial clock input |
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SD5 |
*B |
x80/68k mode : data bus |
F |
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Serial mode : serial data output |
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SD0 to SD4 |
*B |
Data bus |
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F |
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*OT : Tri-state output |
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*B : bi-directional |
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Table 3-2 |
Pin Description |
|
3-3 |
Seiko Instruments Inc. |
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
3.4. Pin Configuration
Figure 3-3 shows configuration of each pin.
A |
B |
pad |
pad |
cin |
cin |
|
Vss |
C |
D |
pad |
pad |
cin |
in |
E |
F |
|
cin |
pad |
pad |
in |
in |
oen |
oen |
Figure 3-3 |
Configuration of Each Pin |
Seiko Instruments Inc. |
3-4 |
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
4. Electrical Characteristics
4.1. Absolute Maximum Ratings
Parameter |
Symbol |
Conditions |
Rating |
Unit |
Storage temperature |
Tsta |
|
-40 to +125 |
° C |
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Operating temperature |
Topr |
|
-40 to +85 |
° C |
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Power supply voltage |
VDD |
Ta=25° C |
-0.3 to +4.0 |
V |
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Input voltage |
VIN |
Ta=25° C |
VSS-0.3 to VDD+0.3 |
V |
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Output voltage |
VOUT |
Ta=25° C |
VSS to VDD |
V |
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Table 4-1 |
Absolute Maximum Ratings |
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4.2. Recommended Operating Conditions
Parameter |
Symbol |
Conditions |
Min. |
Typ. |
Max. |
Unit |
Note |
Operating Frequency |
FOPR |
Ta=-40 to +85° C |
- |
0.256 |
5 |
MHz |
1 |
range |
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Clock Pulse |
Pw |
Ta=-40 to +85° C |
80 |
- |
- |
nS |
|
width |
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Operating voltage |
VDD |
Ta=-40 to +85° C |
2.4 |
- |
3.6 |
V |
|
range |
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Input voltage |
VIN |
Ta=-40 to +85° C |
0 |
- |
VDD |
V |
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Note1: The clock is given by the CLK pin and needs to be as four times or more fast as the BAUD rate. (The multiplier is an integer whose tolerance is <± 2%)
Table 4-2 Recommended Operating Conditions
4-1 |
Seiko Instruments Inc. |
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
4.3. DC Characteristics
Unless otherwise specified: VDD=3.0V, VSS=0V, Ta=25° C
Parameter |
Symbol |
|
Conditions |
Min. |
Typ. |
Max. |
Unit |
Low level input |
VIL |
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0.2× |
- |
- |
V |
voltage |
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VDD |
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High level input |
VIH |
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- |
- |
0.8× |
V |
voltage |
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VDD |
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Low level input |
ILL |
|
VIN=VSS |
-1.0 |
- |
1.0 |
µA |
leakage current |
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High level input |
ILH |
|
All input terminals without |
-1.0 |
- |
1.0 |
µA |
leakage current |
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pull-down resister |
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VIN=VDD |
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High level input |
IIH |
|
All input terminals with |
18 |
70 |
220 |
µA |
current |
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pull-down resister |
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VIN=VDD |
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Low level output |
IOL |
|
VOL=0.4V |
5.0 |
- |
- |
mA |
current |
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|
|
High level output |
IOH |
|
VOH=2.6V |
- |
- |
-3.5 |
mA |
current |
|
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|
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Schmitt Hysteresis |
VWD |
|
|
- |
0.46 |
- |
V |
voltage |
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Table 4-3 |
DC Characteristics |
|
|
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|
|
4.4. Power Current Consumption
Unless otherwise specified: VDD=3.0V, VSS=0V, Ta=25° C
Parameter |
Symbol |
|
Conditions |
Min. |
Typ. |
Max. |
Unit |
Full-transmitting |
IDD1 |
|
Ta=-40 to +85° C |
- |
0.9 |
2.2 |
mA |
Operating current |
|
|
FOPR=256KHz |
|
|
|
|
consumption |
|
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|
|
Non-transmitting |
IDD2 |
|
Ta=-40 to +85° C |
- |
150 |
300 |
µA |
Operating current |
|
|
FOPR=256KHz |
|
|
|
|
consumption |
|
|
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|
|
|
|
|
RESETX=VSS |
|
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|
|
Ta=-10 to +70° C |
- |
1.0 |
15.0 |
|
Standby current |
Is |
|
|
|
|
|
µA |
|
|
|
|
|
|||
consumption |
|
Ta=-40 to +85° C |
|
|
30.0 |
||
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|
|
|
Table 4-4 |
Power Current Consumption |
|
|
|
||
Seiko Instruments Inc. |
4-2 |
TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
5. MPU Interface
5.1. Overview
The S-7600A supports two MPU interfaces: parallel and serial. In parallel interface mode, S-7600A can interface with x80 Family MPU or 68k Family MPU.
PSX |
CS |
RS |
READ |
WRITEX |
BUSYX |
C86 |
SD7 |
SD6 |
SD5 |
SD4 to SD0 |
|
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X |
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|
H: |
CS |
RS |
READ |
WRITEX |
BUSYX |
L |
D7 |
D6 |
D5 |
D4 to D0 |
|
parallel x80 |
|
|
X |
|
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|
H: |
CS |
RS |
E |
|
R/WX |
BUSYX |
H |
D7 |
D6 |
D5 |
D4 to D0 |
parallel 68k |
|
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|
L: |
CS |
RS |
H or L |
|
R/WX |
BUSYX |
H or L |
SI |
SCL |
SO |
Hi-Z |
serial |
|
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Table 5-1 |
Interface Selection |
|
|
|
|
|||
5.2. Parallel Interface
Setting PSX to “H” select the parallel interface. In parallel interface mode the S-7600A can interface with either x80 Family MPU or 68k Family MPU. The desired MPU mode can be selected by setting the C86 pin to “H” or “L”.
RS |
68k Family MPU |
x80 Family MPU |
Function |
|
|
R/WX |
|
|
|
|
|
|
|
|
|
|
READX |
WRITEX |
|
|
|
|
|
|
1 |
1 |
0 |
1 |
Read Register |
|
|
|
|
|
1 |
0 |
1 |
0 |
Write Register |
|
|
|
|
|
0 |
1 |
0 |
1 |
Read Index Register |
|
|
|
|
|
0 |
0 |
1 |
0 |
Write Index Register |
|
|
|
|
|
Table 5-2 Connection Relationship between MPU and Pins
5-1 |
Seiko Instruments Inc. |
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