MF1215-01
CMOS 8-BIT SINGLE CHIP MICROCOMPUTER
E0C88832/88862 T
ECHNICAL
M
ANU AL
E0C88832/88862 Technical Hardware
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material
or due to its application or use in any product or circuit and, further, there is no representation that this material
is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any
intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that
anything made in accordance with this material will be free from any patent or copyright infringement of a third
party. This material or portions thereof may contain technology or the subject relating to strategic products under
the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
© SEIKO EPSON CORPORATION 2000 All rights reserved.
E0C88832/88862 TECHNICAL MANUAL EPSON i
CONTENTS
Contents
1 INTRODUCTION .............................................................................................. 1
1.1 Configuration.....................................................................................................................1
1.2 Features .............................................................................................................................2
1.3 Block Diagram ...................................................................................................................3
1.4 Pin Layout Diagram ..........................................................................................................4
1.5 Mask Option.......................................................................................................................8
2 POWER SUPPLY.............................................................................................. 11
2.1 Operating Voltage.............................................................................................................11
2.2 Internal Power Supply Circuit ..........................................................................................11
2.3 Heavy Load Protection Mode ...........................................................................................12
3 CPU AND MEMORY CONFIGURATION ..................................................... 13
3.1 CPU ..................................................................................................................................13
3.2 Internal Memory ...............................................................................................................13
3.2.1 ROM ........................................................................................................................................13
3.2.2 RAM......................................................................................................................................... 13
3.2.3 I/O memory.............................................................................................................................. 13
3.2.4 Display memory....................................................................................................................... 13
3.3 Exception Processing Vectors ..........................................................................................13
3.4 CC (Customized Condition Flag) .....................................................................................14
4 INITIAL RESET ............................................................................................... 15
4.1 Initial Reset Factors..........................................................................................................15
4.1.1 RESET terminal....................................................................................................................... 15
4.1.2 Simultaneous LOW level input at input port terminals K00–K03...........................................15
4.1.3 Supply voltage detection (SVD) circuit ................................................................................... 16
4.1.4 Initial reset sequence...............................................................................................................16
4.2 Initial Settings After Initial Reset......................................................................................17
5 PERIPHERAL CIRCUITS AND THEIR OPERATION................................ 18
5.1 I/O Memory Map ..............................................................................................................18
5.2 Watchdog Timer................................................................................................................27
5.2.1 Configuration of watchdog timer ............................................................................................ 27
5.2.2 Interrupt function ....................................................................................................................27
5.2.3 Control of watchdog timer ......................................................................................................27
5.2.4 Programming notes .................................................................................................................27
5.3 Oscillation Circuits and Operating Mode ........................................................................28
5.3.1 Configuration of oscillation circuits ....................................................................................... 28
5.3.2 Mask option .............................................................................................................................28
5.3.3 OSC1 oscillation circuit ..........................................................................................................28
5.3.4 OSC3 oscillation circuit ..........................................................................................................29
5.3.5 Operating mode ....................................................................................................................... 29
5.3.6 Switching the CPU clocks ....................................................................................................... 30
5.3.7 Control of oscillation circuit and operating mode.................................................................. 31
5.3.8 Programming notes .................................................................................................................32
5.4 Input Ports (K ports).........................................................................................................33
5.4.1 Configuration of input ports....................................................................................................33
5.4.2 Mask option .............................................................................................................................33
5.4.3 Interrupt function and input comparison register................................................................... 34
ii EPSON E0C88832/88862 TECHNICAL MANUAL
CONTENTS
5.4.4 Control of input ports .............................................................................................................. 36
5.4.5 Programming note................................................................................................................... 38
5.5 Output Ports (R ports) ......................................................................................................39
5.5.1 Configuration of output ports.................................................................................................. 39
5.5.2 Mask option ............................................................................................................................. 39
5.5.3 High impedance control .......................................................................................................... 39
5.5.4 DC output ................................................................................................................................39
5.5.5 Special output .......................................................................................................................... 39
5.5.6 Control of output ports ............................................................................................................ 42
5.5.7 Programming notes ................................................................................................................. 45
5.6 I/O Ports (P ports) ............................................................................................................46
5.6.1 Configuration of I/O ports....................................................................................................... 46
5.6.2 Mask option ............................................................................................................................. 46
5.6.3 I/O control registers and I/O mode ......................................................................................... 46
5.6.4 Control of I/O ports.................................................................................................................47
5.6.5 Programming note................................................................................................................... 47
5.7 Serial Interface .................................................................................................................48
5.7.1 Configuration of serial interface.............................................................................................48
5.7.2 Mask option ............................................................................................................................. 49
5.7.3 Transfer modes ........................................................................................................................ 49
5.7.4 Clock source ............................................................................................................................ 50
5.7.5 Transmit-receive control ......................................................................................................... 51
5.7.6 Operation of clock synchronous transfer ................................................................................52
5.7.7 Operation of asynchronous transfer ....................................................................................... 56
5.7.8 Interrupt function ....................................................................................................................60
5.7.9 Control of serial interface .......................................................................................................62
5.7.10 Programming notes ...............................................................................................................66
5.8 Clock Timer.......................................................................................................................67
5.8.1 Configuration of clock timer ................................................................................................... 67
5.8.2 Interrupt function ....................................................................................................................67
5.8.3 Control of clock timer ............................................................................................................. 69
5.8.4 Programming notes ................................................................................................................. 71
5.9 Stopwatch Timer ...............................................................................................................72
5.9.1 Configuration of stopwatch timer ........................................................................................... 72
5.9.2 Count up pattern...................................................................................................................... 72
5.9.3 Interrupt function ....................................................................................................................73
5.9.4 Control of stopwatch timer...................................................................................................... 74
5.9.5 Programming notes ................................................................................................................. 76
5.10 Programmable Timer........................................................................................................77
5.10.1 Configuration of programmable timer .................................................................................. 77
5.10.2 Count operation and setting basic mode...............................................................................77
5.10.3 Setting of input clock ............................................................................................................. 79
5.10.4 Timer mode............................................................................................................................ 79
5.10.5 Event counter mode ............................................................................................................... 80
5.10.6 Pulse width measurement timer mode................................................................................... 80
5.10.7 Interrupt function .................................................................................................................. 81
5.10.8 Setting of TOUT output ......................................................................................................... 81
5.10.9 Transmission rate setting of serial interface.........................................................................82
5.10.10 Control of programmable timer ..........................................................................................83
5.10.11 Programming notes ............................................................................................................. 88
5.11 LCD Controller.................................................................................................................89
5.11.1 Configuration of LCD controller ..........................................................................................89
5.11.2 Mask option ...........................................................................................................................89
5.11.3 LCD power supply................................................................................................................. 90
5.11.4 LCD driver ............................................................................................................................90
5.11.5 Display memory..................................................................................................................... 93
E0C88832/88862 TECHNICAL MANUAL EPSON iii
CONTENTS
5.11.6 Display control ..................................................................................................................... 100
5.11.7 Control of LCD controller.................................................................................................... 101
5.11.8 Programming note................................................................................................................ 102
5.12 Sound Generator..............................................................................................................103
5.12.1 Configuration of sound generator........................................................................................ 103
5.12.2 Control of buzzer output.......................................................................................................103
5.12.3 Setting of buzzer frequency and sound level ........................................................................ 104
5.12.4 Digital envelope ................................................................................................................... 105
5.12.5 One-shot output ....................................................................................................................105
5.12.6 Control of sound generator ..................................................................................................106
5.12.7 Programming notes ..............................................................................................................108
5.13 Supply Voltage Detection (SVD) Circuit .........................................................................109
5.13.1 Configuration of SVD circuit ............................................................................................... 109
5.13.2 Operation of SVD circuit...................................................................................................... 109
5.13.3 Control of SVD circuit.......................................................................................................... 111
5.13.4 Programming notes ..............................................................................................................112
5.14 Interrupt and Standby Status ...........................................................................................113
5.14.1 Interrupt generation conditions ........................................................................................... 114
5.14.2 Interrupt factor flag..............................................................................................................114
5.14.3 Interrupt enable register ...................................................................................................... 115
5.14.4 Interrupt priority register and interrupt priority level......................................................... 115
5.14.5 Exception processing vectors ...............................................................................................116
5.14.6 Control of interrupt .............................................................................................................. 117
5.14.7 Programming notes ..............................................................................................................118
5.15 Notes for Low Current Consumption...............................................................................119
6 BASIC EXTERNAL WIRING DIAGRAM..................................................... 120
7 ELECTRICAL CHARACTERISTICS............................................................ 122
7.1 Absolute Maximum Rating...............................................................................................122
7.2 Recommended Operating Conditions ..............................................................................122
7.3 DC Characteristics ..........................................................................................................123
7.4 Analog Circuit Characteristics ........................................................................................124
7.5 Power Current Consumption ...........................................................................................127
7.6 AC Characteristics...........................................................................................................128
7.7 Oscillation Characteristics ..............................................................................................134
7.8 Characteristics Curves (reference value) ........................................................................135
8 PACKAGE ........................................................................................................ 142
8.1 Plastic Package................................................................................................................142
8.2 Ceramic Package .............................................................................................................144
9 PAD LAYOUT .................................................................................................. 145
9.1 Diagram of Pad Layout ...................................................................................................145
9.2 Pad Coordinates ..............................................................................................................147
10 PRECAUTIONS ON MOUNTING ................................................................. 149
E0C88832/88862 TECHNICAL MANUAL EPSON 1
1 INTRODUCTION
1 INTRODUCTION
The E0C88832/88862 microcomputer
features the E0C88 (Model 3) CMOS 8-bit core CPU
along with ROM, RAM, three different timers and a
serial interface with optional asynchronization or
clock synchronization.
The E0C88832/88862 fully operable over a wide
range of voltages, and can perform high speed
operations even at low voltage. Like all the
equipment in the E0C Family, these microcomputers have low power consumption.
1.1 Configuration
In this manual, the E0C88832/88862 is associated
with E0C88832 and E0C88862. In these models,
there are differences in built-in ROM capacity,
number of output ports and number of LCD drive
segments, but the other peripheral circuits are
made with the same configuration.
Table 1.1.1 Configuration
Model
E0C88832
E0C88862
Internal ROM
32K bytes
60K bytes
Output port
5 bits
4 bits
LCD segment
*
1
1,632 (Max.)
1,312 (Max.)
*1: Maximum number of drive segments
when the 32 common is selected.
2 EPSON E0C88832/88862 TECHNICAL MANUAL
1 INTRODUCTION
1.2 Features
Table 1.2.1 lists the features of the E0C88832/88862.
Table 1.2.1 Main features
Model
Core CPU
OSC1 Oscillation circuit
OSC3 Oscillation circuit
Instruction set
Min. instruction execution time
Internal ROM capacity
Internal RAM capacity
Input port
Output port
I/O port
Serial interface
Timer
Power supply circuit to
drive liquid crystals
LCD driver
Sound generator
Watchdog timer
Supply voltage detection
(SVD) circuit
Interrupt
Supply voltage
Consumed
current
Supply form
E0C88 (MODEL3) CMOS 8-bit core CPU
Crystal oscillation circuit/CR oscillation circuit/external clock input 32.768 kHz (Typ.)
Crystal oscillation circuit/ceramic oscillation circuit/CR oscillation circuit/external clock input 8.2 MHz (Max.)
608 types (usable for multiplication and division instructions)
0.244 µsec/8.2 MHz (2 clock)
32K bytes
1.5K bytes/RAM, 3,216 bits/display memory
9 bits (1 bit can be set for event counter external clock input)
5 bits (can be set for buzzer output, TOUT signal and
FOUT output)
8 bits (4 bits can be set for serial interface input/output)
1ch (Optional clock synchronous system or asynchronous system)
Programmable timer (8 bits):
(1ch can be set as a an event counter or 2ch as a 16 bits programmable timer for 1ch)
Clock timer (8 bits):
Stopwatch timer (8 bits):
Built-in (booster type, 5 potentials/4 potentials)
Dot matrix type (compatible with 5 × 8 or 5 × 5 fonts)
51 segments × 32 common
67 segments × 16 common
67 segments × 8 common
Envelope function, equipped with volume control
Built-in
Can detect up to 16 different voltage levels
External interrupt:
Internal interrupt:
Normal mode:
Low power mode:
High speed mode:
60K bytes
1.5K bytes/RAM, 2,736 bits/display memory
4 bits (can be set for buzzer output and TOUT signal
output)
41 segments × 32 common
57 segments × 16 common
57 segments × 8 common
E0C88832 E0C88862
0.3 µA (Typ./normal mode)
1.5 µA (Typ./normal mode)
9 µA (Typ./normal mode)
1.1 mA (Typ./normal mode)
QFP8-128pin, QFP15-128pin or chip
SLEEP
HALT
In operation
In operation
2ch
1ch
1ch
Input interrupt
Timer interrupt
Serial interface interrupt
2.4 V–5.5 V (Max. 4.2 MHz)
1.8 V–3.5 V (Max. 80 kHz)
3.5 V–5.5 V (Max. 8.2 MHz)
2 systems (3 types)
3 systems (9 types)
1 system (3 types)
(32.768 kHz)
(32.768 kHz)
(4 MHz)
E0C88832/88862 TECHNICAL MANUAL EPSON 3
1 INTRODUCTION
1.3 Block Diagram
Core CPU E0C88
Interrupt Controller
Input Port
Oscillator
OSC1, 2
OSC3, 4
Reset/Test
RESET
TEST
Watchdog Timer
K00–K07
K10 (EVIN)
I/O Port
Serial Interface
Output Port
Programmable Timer
/Event Counter
Clock Timer
Stopwatch Timer
Power Generator
V
DD
V
SS
V
D1
V
OSC
VC1–V
C5
Supply Voltage Detector
RAM
1.5KB
LCD Driver
ROM
60KB
P10 (SIN)
P11 (SOUT)
P12 (SCLK)
P13 (SRDY)
R26 (TOUT *)
R50 (BZ)
R27 (TOUT)
R51 (BZ *)
Sound Generator
SEG0–SEG40
COM16–COM31 (SEG66–SEG51)
COM0–COM15
P14–P17
CA–CG
∗ Selectable by mask option
E0C88832
Fig. 1.3.1 E0C88832 block diagram
E0C88862
Fig. 1.3.2 E0C88862 block diagram
Core CPU E0C88
Interrupt Controller
Input Port
Oscillator
OSC1, 2
OSC3, 4
Reset/Test
Watchdog Timer
K00–K07
K10 (EVIN)
I/O Port
Serial Interface
Output Port
Programmable Timer
/Event Counter
Clock Timer
Stopwatch Timer
Power Generator
Supply Voltage Detector
RAM
1.5KB
LCD Driver
ROM
32KB
P10 (SIN)
P11 (SOUT)
P12 (SCLK)
P13 (SRDY)
Sound Generator
SEG0–SEG50
COM16–COM31 (SEG66–SEG51)
COM0–COM15
P14–P17
R26 (TOUT *)
R34 (FOUT)
R50 (BZ)
R27 (TOUT)
R51 (BZ *)
∗ Selectable by mask option
RESET
TEST
V
DD
V
SS
V
D1
V
OSC
VC1–V
C5
CA–CG
4 EPSON E0C88832/88862 TECHNICAL MANUAL
1 INTRODUCTION
1.4 Pin Layout Diagram
Fig. 1.4.1 E0C88832 pin layout
E0C88832
QFP8-128pin QFP15-128pin
6596
33
64
INDEX
321
128
97
6596
33
64
INDEX
321
128
97
Pin No. Pin name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin No. Pin name
OSC3
OSC4
V
OSC
V
D1
V
DD
V
SS
OSC1
OSC2
TEST
RESET
K10/EVIN
K07
K06
K05
K04
K03
K02
K01
K00
P17
P16
P15
P14
P13/SRDY
P12/SCLK
P11/SOUT
P10/SIN
R26/TOUT
R27/TOUT
R34/FOUT
R50/BZ
R51/BZ
COM19/SEG63
COM18/SEG64
COM17/SEG65
COM16/SEG66
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
CG
CF
CE
CD
CC
CB
CA
V
C5
V
C4
V
C3
V
C2
V
C1
Pin No. Pin name
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
N.C.
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
N.C.: No Connection
Pin No. Pin name
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
COM31/SEG51
COM30/SEG52
COM29/SEG53
COM28/SEG54
COM27/SEG55
COM26/SEG56
COM25/SEG57
COM24/SEG58
COM23/SEG59
COM22/SEG60
COM21/SEG61
COM20/SEG62
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
E0C88832/88862 TECHNICAL MANUAL EPSON 5
1 INTRODUCTION
Table 1.4.1 E0C88832 pin description
Pin No.
V
DD
VSS
VD1
VOSC
VC1–VC5
CA–CG
OSC1
OSC2
OSC3
OSC4
K00–K07
K10/EVIN
R26/TOUT
R27/TOUT
R34/FOUT
R50/BZ
R51/BZ
P10/SIN
P11/SOUT
P12/SCLK
P13/SRDY
P14–P17
COM0–COM15
COM16–COM31
/SEG66–SEG51
SEG0–SEG50
RESET
TEST
∗1
Pin name In/out Function
37
38
36
35
32–28
27–21
39
40
33
34
51–44
43
60
61
62
63
64
59
58
57
56
55–52
20–5
4–1, 128–117
66–116
42
41
–
–
–
–
O
–
I
O
I
O
I
I
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
Power supply (+) terminal
Power supply (GND) terminal
Regulated voltage for internal circuit
Regulated voltage for OSC1 oscillation circuit
LCD drive voltage output terminals
Voltage boost/reduce-capacitor connection terminals for LCD
OSC1 oscillation input terminal
(select crystal oscillation/CR oscillation/external clock input with mask option)
OSC1 oscillation output terminal
OSC3 oscillation input terminal
(select crystal/ceramic/CR oscillation/external clock input with mask option)
OSC3 oscillation output terminal
Input terminals (K00–K07)
Input terminal (K10) or event counter external clock input terminal (EVIN)
Output terminal (R26) or programmable timer underflow signal inverted
output terminal (TOUT) (selectable by mask option)
Output terminal (R27)
or programmable timer underflow signal output terminal (TOUT)
Output terminal (R34) or clock output terminal (FOUT)
Output terminal (R50) or buzzer output terminal (BZ)
Output terminal (R51) or buzzer inverted output terminal (BZ)
(selectable by mask option)
I/O terminal (P10) or serial I/F data input terminal (SIN)
I/O terminal (P11) or serial I/F data output terminal (SOUT)
I/O terminal (P12) or serial I/F clock I/O terminal (SCLK)
I/O terminal (P13) or serial I/F ready signal output terminal (SRDY)
I/O terminals (P14–P17)
LCD common output terminals
LCD common output terminals (when 1/32 duty is selected)
or LCD segment output terminal (when 1/16 or 1/8 duty is selected)
LCD segment output terminals
Initial reset input terminal
Test input terminal
∗1 TEST is the terminal used for shipping inspection of the IC. For normal operation be sure it is connected to VDD.
6 EPSON E0C88832/88862 TECHNICAL MANUAL
1 INTRODUCTION
6596
33
64
INDEX
321
128
97
6596
33
64
INDEX
321
128
97
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
N.C.
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
CG
CF
CE
CD
CC
CB
CA
V
C5
V
C4
V
C3
V
C2
V
C1
OSC3
OSC4
N.C.
N.C.
N.C.
N.C.
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
COM31/SEG51
COM30/SEG52
COM29/SEG53
COM28/SEG54
COM27/SEG55
COM26/SEG56
COM25/SEG57
COM24/SEG58
COM23/SEG59
COM22/SEG60
COM21/SEG61
COM20/SEG62
COM19/SEG63
COM18/SEG64
COM17/SEG65
COM16/SEG66
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
N.C.
V
OSC
V
D1
V
DD
V
SS
OSC1
OSC2
TEST
RESET
K10/EVIN
K07
K06
K05
K04
K03
K02
K01
K00
P17
P16
P15
P14
P13/SRDY
P12/SCLK
P11/SOUT
P10/SIN
R26/TOUT
R27/TOUT
R50/BZ
R51/BZ
N.C.
N.C.
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
N.C.
N.C.
N.C.
N.C.
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
N.C.: No Connection
Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
E0C88862
QFP8-128pin QFP15-128pin
Fig. 1.4.2 E0C88862 pin layout
E0C88832/88862 TECHNICAL MANUAL EPSON 7
1 INTRODUCTION
Pin No.
V
DD
VSS
VD1
VOSC
VC1–VC5
CA–CG
OSC1
OSC2
OSC3
OSC4
K00–K07
K10/EVIN
R26/TOUT
R27/TOUT
R50/BZ
R51/BZ
P10/SIN
P11/SOUT
P12/SCLK
P13/SRDY
P14–P17
COM0–COM15
COM16–COM31
/SEG66–SEG51
SEG0–SEG40
RESET
TEST
∗1
Pin name In/out Function
68
69
67
66
61–57
56–50
70
71
62
63
82–75
74
91
92
93
94
90
89
88
87
86–83
49–34
32–17
101–128, 4–16
73
72
–
–
–
–
O
–
I
O
I
O
I
I
O
O
O
O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
Power supply (+) terminal
Power supply (GND) terminal
Regulated voltage for internal circuit
Regulated voltage for OSC1 oscillation circuit
LCD drive voltage output terminals
Voltage boost/reduce-capacitor connection terminals for LCD
OSC1 oscillation input terminal
(select crystal oscillation/CR oscillation/external clock input with mask option)
OSC1 oscillation output terminal
OSC3 oscillation input terminal
(select crystal/ceramic/CR oscillation/external clock input with mask option)
OSC3 oscillation output terminal
Input terminals (K00–K07)
Input terminal (K10) or event counter external clock input terminal (EVIN)
Output terminal (R26) or programmable timer underflow signal inverted
output terminal (TOUT) (selectable by mask option)
Output terminal (R27)
or programmable timer underflow signal output terminal (TOUT)
Output terminal (R50) or buzzer output terminal (BZ)
Output terminal (R51) or buzzer inverted output terminal (BZ)
(selectable by mask option)
I/O terminal (P10) or serial I/F data input terminal (SIN)
I/O terminal (P11) or serial I/F data output terminal (SOUT)
I/O terminal (P12) or serial I/F clock I/O terminal (SCLK)
I/O terminal (P13) or serial I/F ready signal output terminal (SRDY)
I/O terminals (P14–P17)
LCD common output terminals
LCD common output terminals (when 1/32 duty is selected)
or LCD segment output terminal (when 1/16 or 1/8 duty is selected)
LCD segment output terminals
Initial reset input terminal
Test input terminal
Table 1.4.2 E0C88862 pin description
∗1 TEST is the terminal used for shipping inspection of the IC. For normal operation be sure it is connected to VDD.
8 EPSON E0C88832/88862 TECHNICAL MANUAL
1 INTRODUCTION
1.5 Mask Option
Mask options shown below are provided for the
E0C88832/88862. Several hardware specifications
are prepared in each mask option, and one of them
can be selected according to the application. The
function option generator WINFOG, that has been
prepared as the development software tool of the
E0C88832/88862, is used for this selection. Mask
pattern of the IC is finally generated based on the
data created by the WINFOG. Refer to the "E0C88
Family Development Tool Manual" for details on
the WINFOG.
Functions selectable with E0C88832/88862 mask options
(1)RESET terminal pull-up resistor
This mask option can select whether the pull-up
resistor for the RESET terminal is used or not.
(2)External reset by simultaneous LOW
input to the input port (K00–K03)
This function resets the IC when several keys
are pressed simultaneously. The mask option is
used to select whether this function is used or
not. Further when the function is used, a
combination of the input ports (K00–K03),
which are connected to the keys to be pressed
simultaneously, can be selected. Refer to Section
4.1.2, "Simultaneous LOW level input at input
port terminals K00–K03", for details.
(3)OSC1 oscillation circuit
The specification of the OSC1 oscillation circuit
can be selected from among four types: "Crystal
oscillation", "CR oscillation", "Crystal oscillation
(gate capacitor built-in)" and "External clock
input". Refer to Section 5.3.3, "OSC1 oscillation
circuit", for details.
(4)OSC3 oscillation circuit
The specification of the OSC3 oscillation circuit
can be selected from among four types: "Crystal
oscillation", "Ceramic oscillation", "CR
oscillation" and "External clock input". Refer to
Section 5.3.4, "OSC3 oscillation circuit", for
details.
(5)Input port pull-up resistor
This mask option can select whether the pull-up
resistor for the input port terminal is used or
not. It is possible to select for each bit of the
input ports. Refer to Section 5.4, "Input Ports (K
ports)", for details.
(6)R26, R51 output port specifications
The R26 port can be configured as a generalpurpose output port or as the TOUT output
port (TOUT inverted output).
The R51 port can be configured as a generalpurpose output port or as the BZ output port
(BZ inverted output). Refer to Section 5.5,
"Output Ports (R ports)", for details.
(7)I/O port pull-up resistor
This mask option can select whether the pull-up
resistor for the I/O port terminal (it works
during input mode) is used or not. It is possible
to select for each bit of the I/O ports. Refer to
Section 5.6, "I/O Ports (P ports)", for details.
Since P10 to P13 are shared with the serial
interface I/O terminals, the selected P10 and
P12 terminal configuration is applied to the
serial input (SIN) terminal and serial clock input
terminal (SCLK in clock synchronous mode)
when the serial interface is used. Refer to
Section 5.7, "Serial Interface", for details.
(8)LCD drive duty
The drive duty for the built-in LCD driver can
be selected whether it will be 1/32 and 1/16
software-switched or fixed at 1/8. Refer to
Section 5.11, "LCD Controller", for details.
(9)LCD power supply
Either the internal power supply or an external
power supply can be selected as the LCD
system power source. Furthermore, when using
the internal power supply, the LCD drive
voltage can be set for a 4.5 V panel or a 5.5 V
panel and the drive bias to 1/5 or 1/4. Refer to
Section 5.11, "LCD Controller", for details.
(10) Initial reset by SVD circuit
The SVD circuit has a function that generates an
initial reset signal when the supply voltage
drops to level 0 or less. The mask option is used
to select whether this function is used or not.
Refer to Section 5.13, "Supply Voltage Detection
(SVD) Circuit", for details.
E0C88832/88862 TECHNICAL MANUAL EPSON 9
1 INTRODUCTION
Option list
The following options can be set for the E0C88832/88862. Multiple specifications are available in each
option item as indicated in the Option List. Select the specifications that meet the target system and check
the appropriate box.
The option selection is done interactively on the screen during WINFOG execution, using this option list as
reference.
E0C88832/88862 mask option list (1/2)
1 OSC1 SYSTEM CLOCK
■■ 1. Crystal
■■ 2. External Clock
■■ 3. CR
■■ 4. Crystal (with Gate Capacity)
2 OSC3 SYSTEM CLOCK
■■ 1. Crystal
■■ 2. Ceramic
■■ 3. CR
■■ 4. External Clock
3 MULTIPLE KEY ENTRY RESET
• Combination ... ■■ 1. Not Use
■■ 2. Use K00, K01
■■ 3. Use K00, K01, K02
■■ 4. Use K00, K01, K02, K03
4 SVD RESET
■■ 1. Not Use
■■ 2. Use
5 INPUT PORT PULL UP RESISTOR
• K00 ................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K01 ................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K02 ................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K03 ................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K04 ................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K05 ................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K06 ................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K07 ................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K10 ................... ■■ 1. With Resistor ■■ 2. Gate Direct
• RESET .............. ■■ 1. With Resistor ■■ 2. Gate Direct
6 I/O PORT PULL UP RESISTOR
• P10 .................... ■■ 1. With Resistor ■■ 2. Gate Direct
• P11 .................... ■■ 1. With Resistor ■■ 2. Gate Direct
• P12 .................... ■■ 1. With Resistor ■■ 2. Gate Direct
• P13 .................... ■■ 1. With Resistor ■■ 2. Gate Direct
• P14 .................... ■■ 1. With Resistor ■■ 2. Gate Direct
• P15 .................... ■■ 1. With Resistor ■■ 2. Gate Direct
• P16 .................... ■■ 1. With Resistor ■■ 2. Gate Direct
• P17 .................... ■■ 1. With Resistor ■■ 2. Gate Direct
10 EPSON E0C88832/88862 TECHNICAL MANUAL
1 INTRODUCTION
E0C88832/88862 mask option list (2/2)
7 LCD DRIVE DUTY
■■ 1. 1/32 & 1/16 Duty
■■ 2. 1/8 Duty
8 LCD POWER SUPPLY
■■ 1. Internal TYPE A (V
C2 Standard, 1/5 Bias, 4.5 V)
■■ 2. External
■■ 3. Internal TYPE B (VC2 Standard, 1/5 Bias, 5.5 V)
■■ 4. Internal TYPE C (VC2 Standard, 1/4 Bias, 4.5 V)
■■ 5. Internal TYPE D (VC1 Standard, 1/4 Bias, 4.5 V)
9 R51 OUTPUT PORT SPECIFICATION
■■ 1. With BZ (Use)
■■ 2. Without BZ (Not Use)
10 R26 OUTPUT PORT SPECIFICATION
■■ 1. With TOUT (Use)
■■ 2. Without TOUT (Not Use)
E0C88832/88862 TECHNICAL MANUAL EPSON 11
2 POWER SUPPLY
2 POWER SUPPLY
In this section, we will explain the operating
voltage and the configuration of the internal power
supply circuit of the E0C88832/88862.
2.1 Operating Voltage
The E0C88832/88862 operating power voltage is as
follows:
Normal mode: 2.4 V to 5.5 V
Low power mode: 1.8 V to 3.5 V
High speed mode: 3.5 V to 5.5 V
If supply voltage drops below level 0 (see Chapter
7, "ELECTRICAL CHARACTERISTICS"), the
system is automatically reset by a supply voltage
detection (SVD) circuit described in the latter. This
function can be selected by mask option.
2.2 Internal Power Supply Circuit
The E0C88832/88862 incorporates the power supply
circuit shown in Figure 2.2.1. When voltage within
the range described above is supplied to VDD (+) and
VSS (GND), all the voltages needed for the internal
circuit are generated internally in the IC.
Roughly speaking, the power supply circuit is
divided into three sections.
The internal logic voltage regulator generates the
operating voltage <VD1> for driving the internal
logic circuits and the OSC3 oscillation circuit. The
VD1 voltage can be selected from the following
three types: 1.3 V for low-power mode, 2.2 V for
normal mode and 3.3 V for high-speed mode.
It should be selected by a program to switch
according to the supply voltage and oscillation
frequency.
See Section 5.3, "Oscillation Circuits and Operating
Mode", for the switching of operating mode.
The oscillation system voltage regulator generates
the operating voltage <VOSC> for the OSC1
oscillation circuit.
The LCD system power supply circuit generates the
LCD drive voltages <VC1> to <VC5>. In 1/5 bias
mode, VC1 is generated by halving VC2 output from
the LCD system voltage regulator and VC3 to VC5 are
generated by boosting VC2. These five voltages can
be supplied from outside the IC by mask option.
Furthermore, 1/4 bias drive can be selected by
mask option. In this case, the VC2 voltage level
becomes equal to the VC3 voltage level. When using
with 1/4 bias configuration, the mask option also
allows selection of VC1 standard mode that
generates VC2 to VC5 by boosting VC1.
See Chapter 7, "ELECTRICAL CHARACTERISTICS" for the voltage values.
In the E0C88832/88862, the LCD drive voltage is
supplied to the built-in LCD driver which drives
the LCD panel connected to the SEG and COM
terminals.
Note: Do not use the VC1–VC5 outputs for driving
external circuits.
Fig. 2.2.1 Configuration of power supply circuit
V
DD
V
V
OSC
D1
V
C1
V
C3
V
C4
V
C5
CA
CB
CC
CD
CE
CF
CG
V
SS
LCD system
power supply
circuit
LCD driver
V
D1
VC1–V
C5
V
OSC
V
C2
External
power
supply
OSC3, OSC4
OSC1, OSC2
Regulator
Booster/reducer
Internal logic
voltage regulator
OSC3
oscillation circuit
Internal voltage
setting circuit
Oscillation system
voltage regulator
Internal circuit
OSC1
oscillation circuit
COM0~COM15
COM16~COM31/SEG66~SEG51
SEG0~SEG50
COM0~COM15
COM16~COM31/SEG66~SEG51
SEG0~SEG40
E0C88832
E0C88862
12 EPSON E0C88832/88862 TECHNICAL MANUAL
2 POWER SUPPLY
2.3 Heavy Load Protection Mode
The E0C88832/88862 has a heavy load protection
function for stable operation even when the supply
voltage fluctuates by driving a heavy load. The
heavy load protection mode becomes valid when
the peripheral circuits are in the following status:
(1) The OSC3 oscillation circuit is switched ON
(OSCC = "1" and not in SLEEP)
(2) The buzzer output is switched ON
(BZON = "1" or BZSHT = "1")
SLEEP status
Heavy load
protection mode
OSCC
BZON
BZSHT
Fig. 2.3.1 Configuration of heavy load protection mode
control circuit
For details of the OSC3 oscillation circuit and
buzzer output, see "5.3 Oscillation Circuits and
Operating Mode" and "5.12 Sound Generator",
respectively.
E0C88832/88862 TECHNICAL MANUAL EPSON 13
3 CPU AND MEMORY CONFIGURATION
3 CPU AND MEMORY CONFIGURATION
In this section, we will explain the CPU and memory configuration.
3.1 CPU
The E0C88832/88862 utilize the E0C88 8-bit core
CPU whose resistor configuration, command set,
etc. are virtually identical to other units in the
family of processors incorporating the E0C88.
See the "E0C88 Core CPU Manual" for the E0C88.
The E0C88832/88862 supports Model 3/minimum
mode of the E0C88 CPU which allows accessing of
the internal memory mapped within the physical
space from 000000H to 00FFFFH.
3.2 Internal Memory
The E0C88832/88862 is equipped with internal
ROM and RAM as shown in Figure 3.2.1.
3.2.1 ROM
The internal ROM capacity is shown in Table
3.2.1.1.
Table 3.2.1.1 Internal ROM capacity
Fig. 3.2.1 Internal memory map
I/O memory
Display memory
Unused area
RAM
(1.5K bytes)
ROM
(60K bytes)
E0C88832 E0C88862
00FFFFH
00FF00H
00FD42H
00F800H
00F7FFH
00F600H
00F5FFH
00F000H
00EFFFH
008000H
007FFFH
000000H
I/O memory
Display memory
Unused area
RAM
(1.5K bytes)
Unused area
ROM
(32K bytes)
Model
E0C88832
E0C88862
ROM capacity
32K bytes
60K bytes
Address
000000H–007FFFH
000000H–00EFFFH
3.2.2 RAM
The internal ROM capacity is shown in Table
3.2.2.1.
Table 3.2.2.1 Internal ROM capacity
Model
E0C88832
E0C88862
RAM capacity
1.5K bytes
1.5K bytes
Address
00F000H–00F5FFH
00F000H–00F5FFH
3.2.3 I/O memory
A memory mapped I/O method is employed in the
E0C88832/88862 for interfacing with internal
peripheral circuit. Peripheral circuit control bits and
data register are arranged in data memory space.
Control and data exchange are conducted via
normal memory access. The I/O memory is
arranged from address 00FF00H to address
00FFFFH. See Section 5.1, "I/O Memory Map", for
details of the I/O memory.
3.2.4 Display memory
The E0C88832/88862 is equipped with an internal
display memory which stores a display data for
LCD driver.
The display memory is arranged from address
00F800H to address 00FD42H (including the
unused area). See Section 5.11, "LCD Controller",
for details of the display memory.
3.3 Exception Processing Vectors
Address 000000H to address 000023H in the
program area of the E0C88832/88862 is assigned as
exception processing vectors. Furthermore, from
address 000026H to address 0000FFH, software
interrupt vectors are assignable to any two bytes
which begin with an even address.
Table 3.3.1 lists the vector addresses and the
exception processing factors to which they
correspond.
14 EPSON E0C88832/88862 TECHNICAL MANUAL
3 CPU AND MEMORY CONFIGURATION
Table 3.3.1 Vector addresses and
exception processing factors
3.4 CC (Customized Condition Flag)
The E0C88832/88862 does not use the customized
condition flag (CC) in the core CPU. Accordingly, it
cannot be used as a branching condition for the
conditional branching instruction (JRS, CARS).
Vector
address
000000H
000002H
000004H
000006H
000008H
00000AH
00000CH
00000EH
000010H
000012H
000014H
000016H
000018H
00001AH
00001CH
00001EH
000020H
000022H
000024H
000026H
:
0000FEH
Priority
High
↑
↓
Low
No
priority
rating
Exception processing factor
Reset
Zero division
Watchdog timer (NMI)
Programmable timer 1 interrupt
Programmable timer 0 interrupt
K10 input interrupt
K04–K07 input interrupt
K00–K03 input interrupt
Serial I/F error interrupt
Serial I/F receiving complete interrupt
Serial I/F transmitting complete interrupt
Stopwatch timer 100 Hz interrupt
Stopwatch timer 10 Hz interrupt
Stopwatch timer 1 Hz interrupt
Clock timer 32 Hz interrupt
Clock timer 8 Hz interrupt
Clock timer 2 Hz interrupt
Clock timer 1 Hz interrupt
System reserved (cannot be used)
Software interrupt
For each vector address and the address after it, the
start address of the exception processing routine is
written into the subordinate and super ordinate
sequence. When an exception processing factor is
generated, the exception processing routine is
executed starting from the recorded address.
When multiple exception processing factors are
generated at the same time, execution starts with
the highest priority item.
The priority sequence shown in Table 3.3.1 assumes
that the interrupt priority levels are all the same.
The interrupt priority levels can be set by software
in each system. (See Section 5.14 "Interrupt and
Standby Status".)
Note: For exception processing other than reset,
SC (system condition flag) and PC (program
counter) are evacuated to the stack and
branches to the exception processing
routines. Consequently, when returning to
the main routine from exception processing
routines, please use the RETE instruction.
See the "E0C88 Core CPU Manual" for information
on CPU operations when an exception processing
factor is generated.
E0C88832/88862 TECHNICAL MANUAL EPSON 15
4 INITIAL RESET
4.1.1 RESET terminal
Initial reset can be done by executed externally
inputting a LOW level to the RESET terminal.
Be sure to maintain the RESET terminal at LOW
level for the regulation time after the power on to
assure the initial reset.
In addition, be sure to use the RESET terminal for
the first initial reset after the power is turned on.
The RESET terminal is equipped with a pull-up
resistor. You can select whether or not to use by
mask option.
4.1.2 Simultaneous LOW level input at
input port terminals K00–K03
Another way of executing initial reset externally is to
input a LOW level simultaneously to the input ports
(K00–K03) selected by mask option.
Since there is a built-in time authorize circuit, be
sure to maintain the designated input port terminal
at LOW level for two seconds (when the oscillation
frequency fOSC1 = 32.768 kHz) or more to perform
the initial reset by means of this function.
However, the time authorize circuit is bypassed
during the SLEEP (standby) status and oscillation
stabilization waiting period, and initial reset is
executed immediately after the simultaneous LOW
level input to the designated input ports.
The combination of input ports (K00–K03) that can
be selected by mask option are as follows:
(1) Not use
(2) K00 & K01
(3) K00 & K01 & K02
(4) K00 & K01 & K02 & K03
For instance, if mask option (4) "K00 & K01 & K02
& K03" is selected, initial reset will take place when
the input level at input ports K00–K03 is simultaneously LOW.
When using this function, make sure that the
designated input ports do not simultaneously
switch to LOW level while the system is in normal
operation.
4 INITIAL RESET
Initial reset in the E0C88832/88862 is required in order to initialize circuits. This chapter describes
initial reset factors and the initial settings for internal registers.
4.1 Initial Reset Factors
There are three initial reset factors for the
E0C88832/88862 as shown below.
(1) RESET terminal
(2) Simultaneous LOW level input at input port
terminals K00–K03.
(3) Supply voltage detection (SVD) circuit
Figure 4.1.1 shows the configuration of the initial
reset circuit.
The CPU and peripheral circuits are initialized by
means of initial reset factors. When the factor is
canceled, the CPU commences reset exception
processing. (See "E0C88 Core CPU Manual".)
When this occurs, reset exception processing
vectors, Bank 0, 000000H–000001H from program
memory are read out and the program (initialization routine) which begins at the readout address is
executed.
K00
Input port K00
K01
Input port K01
K02
Input port K02
K03
Input port K03
V
DD
RESET
V
DD
V
DD
SLEEP status
Time authorize
circuit
Oscillation stability waiting signal
Internal initial reset
Mask option
Supply voltage detection
(SVD) circuit
Fig. 4.1.1 Configuration of initial reset circuit
16 EPSON E0C88832/88862 TECHNICAL MANUAL
4 INITIAL RESET
4.1.3 Supply voltage detection (SVD) circuit
When the SVD circuit detects that supply voltage
has dropped below level 0 four successive times
(see Chapter 7, "ELECTRICAL CHARACTERISTICS"), it outputs an initial reset signal until the
supply voltage has been restored to level 2.
You can select whether or not to use the initial reset
according to the SVD circuit by mask option. If you
use it, the supply voltage must be at least level 2 for
the first sampling of the SVD circuit, when the
power is turned on. At this time, if the power
voltage level is less than level 2, the initial reset
status will not be canceled and instead the SVD
circuit will continue sampling until the supply
voltage reaches level 2 or more.
For more information, see "5.13 Supply Voltage
Detection (SVD) Circuit" in this Manual.
4.1.4 Initial reset sequence
After cancellation of the LOW level input to the
RESET terminal, when the power is turned on, the
start-up of the CPU is held back until the oscillation
stabilization waiting time (8,192/fOSC1 sec.) has
elapsed. When the initial reset by the SVD circuit
has been used, an initial sampling time (248/fOSC1
sec.) is added as additional waiting time.
Figure 4.1.4.1 shows the operating sequence
following initial reset release.
Also, when using the initial reset by simultaneous
LOW level input into the input port, you should be
careful of the following points.
(1) During SLEEP status, since the time authoriza-
tion circuit is bypassed, an initial reset is
triggered immediately after a LOW level
simultaneous input value. In this case, the CPU
starts after waiting the oscillation stabilization
time and the SVD circuit initial sampling time
(when used with the mask option), following
cancellation of the LOW level simultaneous
input.
(2) Other than during SLEEP status, an initial reset
will be triggered 1–2 seconds after a LOW level
simultaneous input. In this case, since a reset
differential pulse (64/f
OSC1 sec.) is generated
within the E0C88832/88862, the CPU will start
even if the LOW level simultaneous input status
is not canceled.
PC PC PC 00-0000
Dummy Dummy VECL
f
OSC1
RESET
Internal initial reset
Internal address bus
Internal data bus
Internal read signal
8192/f
OSC1
[sec]
Oscillation stable waiting time
248/f
OSC1
[sec]
First SVD sampling time * Dummy cycle Reset exception processing
∗
When the initial reset by the SVD circuit with the mask option has been used, this cycle is inserted as the waiting time.
Fig. 4.1.4.1 Initial reset sequence
E0C88832/88862 TECHNICAL MANUAL EPSON 17
4 INITIAL RESET
Register name
Code Setting value
Data register A
Data register B
Index (data) register L
Index (data) register H
Index register IX
Index register IY
Program counter
Stack pointer
Base register
Zero flag
Carry flag
Overflow flag
Negative flag
Decimal flag
Unpack flag
Interrupt flag 0
Interrupt flag 1
New code bank register
Code bank register
Expand page register
Expand page register for IX
Expand page register for IY
A
B
L
H
IX
IY
PC
SP
BR
Z
C
V
N
D
U
I0
I1
NB
CB
EP
XP
YP
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
0
0
0
0
0
1
1
01H
Undefined
00H
00H
00H
Bit length
8
8
8
8
16
16
16
16
8
1
1
1
1
1
1
1
1
8
8
8
8
8
*
*
4.2 Initial Settings After Initial Reset
The CPU internal registers are initialized as follows
during initial reset.
Table 4.2.1 Initial settings
* Reset exception processing loads the preset
values stored in 0 bank, 000000H–000001H into
the PC. At the same time, 01H of the NB initial
value is loaded into CB.
Initialize the registers which are not initialized at
initial reset using software.
Since the internal RAM and display memory are
not initialized at initial reset, be sure to initialize
using software.
The respectively stipulated initializations are done
for internal peripheral circuits. If necessary, the
initialization should be done using software.
For initial value at initial reset, see the sections on
the I/O memory map and peripheral circuit
descriptions in the following chapter of this
Manual.
18 EPSON E0C88832/88862 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
5 PERIPHERAL CIRCUITS AND
THEIR OPERATION
The peripheral circuits of the E0C88832/88862 is interfaced with the CPU by means of the memory
mapped I/O method. For this reason, just as with other memory access operations, peripheral circuits can
be controlled by manipulating I/O memory. Below is a description of the operation and control method for
each individual peripheral circuit.
5.1 I/O Memory Map
Table 5.1.1(a) I/O Memory map (00FF00H–00FF10H)
Address Bit Name
00FF00 D7
D6
D5
D4
D3
D2
D1
D0
BSMD1
BSMD0
CEMD1
CEMD0
CE3
CE2
CE1
CE0
SR R/WFunction Comment
General-purpose register
General-purpose register
General-purpose register
General-purpose register
General-purpose register
General-purpose register
General-purpose register
General-purpose register
Reserved register
(Note)
10
0
0
1
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1 0
00FF01 D7
D6
D5
D4
D3
D2
D1
D0
SPP7
SPP6
SPP5
SPP4
SPP3
SPP2
SPP1
SPP0
General-purpose register
General-purpose register
General-purpose register
General-purpose register
General-purpose register
General-purpose register
General-purpose register
General-purpose register
Reserved register
(Note)
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
10
00FF02 D7
D6
D5
D4
D3
D2
D1
D0
EBR
WT2
WT1
WT0
CLKCHG
OSCC
VDC1
VDC0
General-purpose register
General-purpose register
General-purpose register
General-purpose register
CPU operating clock switch
OSC3 oscillation On/Off control
Operating mode selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
OSC3
On
0
OSC1
Off
VDC1
1
0
0
VDC0
×
1
0
High speed (VD1=3.3V)
Low power (V
D1
=1.3V)
Normal (V
D1
=2.2V)
Operating mode
00FF10 D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
LCCLK
LCFRM
DTFNT
LDUTY
SGOUT
–
–
–
General-purpose register
General-purpose register
LCD dot font selection
LCD drive duty selection
General-purpose register
Constantry "0" when
being read
Reserved register
–
–
–
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
–
–
–
1
5 x 5 dots
1/16 duty
1
–
–
–
0
5 x 8 dots
1/32 duty
0
*1
Reserved register
*1 When 1/8 duty has been selected by mask option, setting of this register becomes invalid.
Note) When debugging using the E0C88 Family debugging tools ICE88R (ICE88) and PRC88348,
all the interrupts including NMI are disabled until values are written to addresses "00FF00H"
and "00FF01H".
Reserved register
E0C88832/88862 TECHNICAL MANUAL EPSON 19
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(b) I/O Memory map (00FF11H–00FF22H)
Address Bit Name SR R/WFunction Comment10
00FF11 D7
D6
D5
D4
D3
D2
D1
D0
–
DSPAR
LCDC1
LCDC0
LC3
LC2
LC1
LC0
–
LCD display memory area selection
LCD display control
LCD contrast adjustment
"0" when being read
These bits are reset
to (0, 0) when
SLP instruction
is executed.
–
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
Display area 1–Display area 0
LCDC1
1
1
0
0
LCDC0
1
0
1
0
LCD display
All LCDs lit
All LCDs out
Normal display
Drive off
LC3
1
1
:
0
LC2
1
1
:
0
LC1
1
1
:
0
LC0
1
0
:
0
Contrast
Dark
:
:
Light
00FF12 D7
D6
D5
D4
D3
D2
D1
D0
–
–
SVDSP
SVDON
SVD3
SVD2
SVD1
SVD0
–
–
SVD auto-sampling control
SVD continuous sampling control/status
SVD detection level
Constantry "0" when
being read
These registers are
reset to "0" when
SLP instruction
is executed.
*2
–
–
0
1→0*1
0
X
X
X
X
R/W
R/W
R
R
R
R
–
–
On
Busy
On
–
–
Off
Ready
Off
R
W
SVD3
1
1
:
0
SVD2
1
1
:
0
SVD1
1
1
:
0
SVD0
1
0
:
0
Detection level
Level 15
Level 14
:
Level 0
*1 After initial reset, this status is set "1" until conclusion of hardware first sampling.
*2 Initial values are set according to the supply voltage detected at first sampling by hardware.
Until conclusion of first sampling, SVD0–SVD3 data are undefined.
00FF20 D7
D6
D5
D4
D3
D2
D1
D0
PK01
PK00
PSIF1
PSIF0
PSW1
PSW0
PTM1
PTM0
K00–K07 interrupt priority register
Serial interface interrupt priority register
Stopwatch timer interrupt priority register
Clock timer interrupt priority register
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PK01
PSIF1
PSW1
PTM1
1
1
0
0
PK00
PSIF0
PSW0
PTM0
1
0
1
0
Priority
level
Level 3
Level 2
Level 1
Level 0
00FF21 D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
–
PPT1
PPT0
PK11
PK10
–
–
–
–
Programmable timer interrupt priority register
K10 interrupt priority register
Constantly "0" when
being read
–
–
–
–
0
0
0
0
R/W
R/W
R/W
R/W
–
–
–
–
–
–
–
–
PPT1
PK11
1
1
0
0
PPT0
PK10
1
0
1
0
Priority
level
Level 3
Level 2
Level 1
Level 0
00FF22 D7
D6
D5
D4
D3
D2
D1
D0
–
ESW100
ESW10
ESW1
ETM32
ETM8
ETM2
ETM1
–
Stopwatch timer 100 Hz interrupt enable register
Stopwatch timer 10 Hz interrupt enable register
Stopwatch timer 1 Hz interrupt enable register
Clock timer 32 Hz interrupt enable register
Clock timer 8 Hz interrupt enable register
Clock timer 2 Hz interrupt enable register
Clock timer 1 Hz interrupt enable register
"0" when being read
–
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
Interrupt
enable
–
Interrupt
disable
20 EPSON E0C88832/88862 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(c) I/O Memory map (00FF23H–00FF31H)
Address Bit Name SR R/WFunction Comment10
D7
D6
D5
D4
D3
D2
D1
D0
00FF24 D7
D6
D5
D4
D3
D2
D1
D0
–
FSW100
FSW10
FSW1
FTM32
FTM8
FTM2
FTM1
–
Stopwatch timer 100 Hz interrupt factor flag
Stopwatch timer 10 Hz interrupt factor flag
Stopwatch timer 1 Hz interrupt factor flag
Clock timer 32 Hz interrupt factor flag
Clock timer 8 Hz interrupt factor flag
Clock timer 2 Hz interrupt factor flag
Clock timer 1 Hz interrupt factor flag
"0" when being read
–
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
(R)
Interrupt
factor is
generated
(W)
Reset
–
(R)
No interrupt
factor is
generated
(W)
No operation
00FF25 D7
D6
D5
D4
D3
D2
D1
D0
FPT1
FPT0
FK1
FK0H
FK0L
FSERR
FSREC
FSTRA
Programmable timer 1 interrupt factor flag
Programmable timer 0 interrupt factor flag
K10 interrupt factor flag
K04–K07 interrupt factor flag
K00–K03 interrupt factor flag
Serial I/F (error) interrupt factor flag
Serial I/F (receiving) interrupt factor flag
Serial I/F (transmitting) interrupt factor flag
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(R)
Interrupt
factor is
generated
(W)
Reset
(R)
No interrupt
factor is
generated
(W)
No operation
00FF23 EPT1
EPT0
EK1
EK0H
EK0L
ESERR
ESREC
ESTRA
Programmable timer 1 interrupt enable register
Programmable timer 0 interrupt enable register
K10 interrupt enable register
K04–K07 interrupt enable register
K00–K03 interrupt enable register
Serial I/F (error) interrupt enable register
Serial I/F (receiving) interrupt enable register
Serial I/F (transmitting) interrupt enable register
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt
enable
Interrupt
disable
00FF30 D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
MODE16
CHSEL
PTOUT
CKSEL1
CKSEL0
–
–
–
8/16-bit mode selection
TOUT output channel selection
TOUT output control
Prescaler 1 source clock selection
Prescaler 0 source clock selection
Constantry "0" when
being read
–
–
–
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
–
–
–
16-bit x 1
Timer 1
On
f
OSC3
f
OSC3
–
–
–
8-bit x 2
Timer 0
Off
f
OSC1
f
OSC1
00FF31 D7
D6
D5
D4
D3
D2
D1
D0
EVCNT
FCSEL
PLPOL
PSC01
PSC00
CONT0
PSET0
PRUN0
Timer 0 counter mode selection
Timer 0
function selection
Timer 0
pulse polarity
selection
Timer 0 prescaler dividing ratio selection
Timer 0 continuous/one-shot mode selection
Timer 0 preset
Timer 0 Run/Stop control
"0" when being read
0
0
0
0
0
0
–
0
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
Event counter
Pulse width
measurement
With
noise rejector
Rising edge
of K10 input
High level
measurement
for K10 input
Continuous
Preset
Run
Timer
Normal
mode
Without
noise rejector
Falling edge
of K10 input
Low level
measurement
for K10 input
One-shot
No operation
Stop
In timer mode
In event counter mode
Down count timing
in event counter mode
In pulse width
measurement mode
PSC01
1
1
0
0
PSC00
1
0
1
0
Prescaler dividing ratio
Source clock / 64
Source clock / 16
Source clock / 4
Source clock / 1
E0C88832/88862 TECHNICAL MANUAL EPSON 21
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(d) I/O Memory map (00FF32H–00FF36H)
Address Bit Name SR R/WFunction Comment10
00FF32
D7
D6
D5
D4
D3
D2
D1
D0
RLD07
RLD06
RLD05
RLD04
RLD03
RLD02
RLD01
RLD00
Timer 0 reload data D7 (MSB)
Timer 0 reload data D6
Timer 0 reload data D5
Timer 0 reload data D4
Timer 0 reload data D3
Timer 0 reload data D2
Timer 0 reload data D1
Timer 0 reload data D0 (LSB)
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
High Low
00FF33
D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
PSC11
PSC10
CONT1
PSET1
PRUN1
–
–
–
Timer 1 prescaler dividing ratio selection
Timer 1 continuous/one-shot mode selection
Timer 1 preset
Timer 1 Run/Stop control
Constantry "0" when
being read
"0" when being read
–
–
–
0
0
0
–
0
R/W
R/W
R/W
W
R/W
–
–
–
Continuous
Preset
Run
–
–
–
One-shot
No operation
Stop
PSC11
1
1
0
0
PSC10
1
0
1
0
Prescaler dividing ratio
Source clock / 64
Source clock / 16
Source clock / 4
Source clock / 1
D7
D6
D5
D4
D3
D2
D1
D0
RLD17
RLD16
RLD15
RLD14
RLD13
RLD12
RLD11
RLD10
Timer 1 reload data D7 (MSB)
Timer 1 reload data D6
Timer 1 reload data D5
Timer 1 reload data D4
Timer 1 reload data D3
Timer 1 reload data D2
Timer 1 reload data D1
Timer 1 reload data D0 (LSB)
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
High Low
00FF34
D7
D6
D5
D4
D3
D2
D1
D0
PTD07
PTD06
PTD05
PTD04
PTD03
PTD02
PTD01
PTD00
Timer 0 counter data D7 (MSB)
Timer 0 counter data D6
Timer 0 counter data D5
Timer 0 counter data D4
Timer 0 counter data D3
Timer 0 counter data D2
Timer 0 counter data D1
Timer 0 counter data D0 (LSB)
1
1
1
1
1
1
1
1
R
R
R
R
R
R
R
R
High Low
00FF35
D7
D6
D5
D4
D3
D2
D1
D0
PTD17
PTD16
PTD15
PTD14
PTD13
PTD12
PTD11
PTD10
Timer 1 counter data D7 (MSB)
Timer 1 counter data D6
Timer 1 counter data D5
Timer 1 counter data D4
Timer 1 counter data D3
Timer 1 counter data D2
Timer 1 counter data D1
Timer 1 counter data D0 (LSB)
1
1
1
1
1
1
1
1
R
R
R
R
R
R
R
R
High Low
00FF36
22 EPSON E0C88832/88862 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(e) I/O Memory map (00FF40H–00FF44H)
Address Bit Name
00FF40 D7
D6
D5
D4
D3
D2
D1
D0
–
FOUT2
FOUT1
FOUT0
FOUTON
WDRST
TMRST
TMRUN
SR R/WFunction Comment
–
FOUT frequency selection
FOUT output control
Watchdog timer reset
Clock timer reset
Clock timer Run/Stop control
"0" when being read
This is just R/W
register on
E0C88862.
Constantly "0" when
being read
10
–
0
0
0
0
–
–
0
R/W
R/W
R/W
R/W
W
W
R/W
–
On
Reset
Reset
Run
–
Off
No operation
No operation
Stop
00FF41 D7
D6
D5
D4
D3
D2
D1
D0
TMD7
TMD6
TMD5
TMD4
TMD3
TMD2
TMD1
TMD0
Clock timer data
Clock timer data
Clock timer data
Clock timer data
Clock timer data
Clock timer data
Clock timer data
Clock timer data
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
High
Low
1 Hz
2 Hz
4 Hz
8 Hz
16 Hz
32 Hz
64 Hz
128 Hz
FOUT2
0
0
0
0
1
1
1
1
FOUT1
0
0
1
1
0
0
1
1
FOUT0
0
1
0
1
0
1
0
1
Frequency
f
OSC1
/ 1
f
OSC1
/ 2
f
OSC1
/ 4
f
OSC1
/ 8
f
OSC3
/ 1
f
OSC3
/ 2
f
OSC3
/ 4
f
OSC3
/ 8
00FF42 D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
–
–
–
SWRST
SWRUN
–
–
–
–
–
–
Stopwatch timer reset
Stopwatch timer Run/Stop control
Constantly "0" when
being read
–
–
–
–
–
–
–0W
R/W
–
–
–
–
–
–
Reset
Run
–
–
–
–
–
–
No operation
Stop
00FF43 D7
D6
D5
D4
D3
D2
D1
D0
SWD7
SWD6
SWD5
SWD4
SWD3
SWD2
SWD1
SWD0
Stopwatch timer data
BCD (1/10 sec)
Stopwatch timer data
BCD (1/100 sec)
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
00FF44 D7
D6
D5
D4
D3
D2
D1
D0
–
BZSTP
BZSHT
SHTPW
ENRTM
ENRST
ENON
BZON
–
One-shot buzzer forcibly stop
One-shot buzzer trigger/status
One-shot buzzer duration width selection
Envelope attenuation time
Envelope reset
Envelope On/Off control
Buzzer output control
Constantry "0" when
being read
"0" when being read
*1
–
–
0
0
0
–
0
0
W
R/W
R/W
R/W
W
R/W
R/W
–
Forcibly stop
Busy
Trigger
125 msec
1 sec
Reset
On
On
–
No operation
Ready
No operation
31.25 msec
0.5 sec
No operation
Off
Off
R
W
*1 Reset to "0" during one-shot output.
E0C88832/88862 TECHNICAL MANUAL EPSON 23
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(f) I/O Memory map (00FF45H–00FF49H)
Address Bit Name SR R/WFunction Comment10
00FF45 D7
D6
D5
D4
D3
D2
D1
D0
–
DUTY2
DUTY1
DUTY0
–
BZFQ2
BZFQ1
BZFQ0
–
Buzzer signal duty ratio selection
–
Buzzer frequency selection
"0" when being read
"0" when being read
–
0
0
0
–
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
–
–
–
–
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8/16
7/16
6/16
5/16
4/16
3/16
2/16
1/16
4096.0
2048.0
8/20
7/20
6/20
5/20
4/20
3/20
2/20
1/20
3276.8
1638.4
12/24
11/24
10/24
9/24
8/24
7/24
6/24
5/24
2730.7
1365.3
12/28
11/28
10/28
9/28
8/28
7/28
6/28
5/28
2340.6
1170.3
210
Buzzer frequency (Hz)DUTY2–1
BZFQ2
0
0
0
0
1
1
1
1
BZFQ1
0
0
1
1
0
0
1
1
BZFQ0
0
1
0
1
0
1
0
1
Frequency (Hz)
4096.0
3276.8
2730.7
2340.6
2048.0
1638.4
1365.3
1170.3
00FF48 D7
D6
D5
D4
D3
D2
D1
D0
–
EPR
PMD
SCS1
SCS0
SMD1
SMD0
ESIF
–
Parity enable register
Parity mode selection
Clock source selection
Serial I/F mode selection
Serial I/F enable register
"0" when being read
Only for
asynchronous mode
In the clock synchronous slave mode,
external clock is
selected.
–
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
With parity
Odd
Serial I/F
–
Non parity
Even
I/O port
SCS1
1
1
0
0
SCS0
1
0
1
0
Clock source
Programmable timer
f
OSC3
/ 4
f
OSC3
/ 8
f
OSC3
/ 16
SMD1
1
1
0
0
SMD0
1
0
1
0
Mode
Asynchronous 8-bit
Asynchronous 7-bit
Clock synchronous slave
Clock synchronous master
00FF49 D7
D6
D5
D4
D3
D2
D1
D0
–
FER
PER
OER
RXTRG
RXEN
TXTRG
TXEN
–
Framing error flag
Parity error flag
Overrun error flag
Receive trigger/status
Receive enable
Transmit trigger/status
Transmit enable
"0" when being read
Only for
asynchronous mode
–
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
Error
Reset (0)
Error
Reset (0)
Error
Reset (0)
Run
Trigger
Enable
Run
Trigger
Enable
–
No error
No operation
No error
No operation
No error
No operation
Stop
No operation
Disable
Stop
No operation
Disable
R
W
R
W
R
W
R
W
R
W
24 EPSON E0C88832/88862 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(g) I/O Memory map (00FF4AH–00FF54H)
Address Bit Name SR R/WFunction Comment10
00FF4A D7
D6
D5
D4
D3
D2
D1
D0
TRXD7
TRXD6
TRXD5
TRXD4
TRXD3
TRXD2
TRXD1
TRXD0
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
High
Low
Transmit/Receive data D7 (MSB)
Transmit/Receive data D6
Transmit/Receive data D5
Transmit/Receive data D4
Transmit/Receive data D3
Transmit/Receive data D2
Transmit/Receive data D1
Transmit/Receive data D0 (LSB)
00FF50 D7
D6
D5
D4
D3
D2
D1
D0
SIK07
SIK06
SIK05
SIK04
SIK03
SIK02
SIK01
SIK00
K07 interrupt selection register
K06 interrupt selection register
K05 interrupt selection register
K04 interrupt selection register
K03 interrupt selection register
K02 interrupt selection register
K01 interrupt selection register
K00 interrupt selection register
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt
enable
Interrupt
disable
00FF51 D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
–
–
–
SIK11
SIK10
–
–
–
–
–
–
General-purpose register
K10 interrupt selection register
Constantly "0" when
being read
Reserved register
–
–
–
–
–
–
00R/W
R/W
–
–
–
–
–
–
1
Enable
–
–
–
–
–
–
0
Disable
00FF53 D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
–
–
–
KCP11
KCP10
–
–
–
–
–
–
General-purpose register
K10 input comparison register
Constantly "0" when
being read
Reserved register
–
–
–
–
–
–
11R/W
R/W
–
–
–
–
–
–
1
Falling edge
–
–
–
–
–
–
0
Rising edge
00FF52 D7
D6
D5
D4
D3
D2
D1
D0
KCP07
KCP06
KCP05
KCP04
KCP03
KCP02
KCP01
KCP00
K07 input comparison register
K06 input comparison register
K05 input comparison register
K04 input comparison register
K03 input comparison register
K02 input comparison register
K01 input comparison register
K00 input comparison register
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt
generated
at falling
edge
Interrupt
generated
at rising
edge
00FF54 D7
D6
D5
D4
D3
D2
D1
D0
K07D
K06D
K05D
K04D
K03D
K02D
K01D
K00D
K07 input port data
K06 input port data
K05 input port data
K04 input port data
K03 input port data
K02 input port data
K01 input port data
K00 input port data
–
–
–
–
–
–
–
–
R
R
R
R
R
R
R
R
High level
input
Low level
input
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