E-peas AEM10941 User Manual

User guide

Evaluation board for AEM10941

AEM10941

Description

The AEM10941 evaluation board is a printed circuit board (PCB) featuring all the needed components to operate the AEM10941 integrated circuit (IC). Please refer to the datasheet for all the useful details about the AEM10941 (Document

AEM10941).

DS The AEM10941 evaluation board allows users to test the e-peas IC and analyze its performances in a laboratory-like setting. It allows easy connections to the e nergy harvester, the storage element and the low-voltage and high-voltage loads. It also provides all the conﬁguration access to set the device in any one of the modes described in the datasheet. The control and status signals are available on standard pin headers, allowing users to wire for any usage scenario and evaluate the relevant performance. The AEM10941 evaluation board is a plug and play, intuitive and eﬃcient tool for making the appropriate decisions (component selection, operating mode s) for the design of a highly eﬃcient solar energy powered subsystem in your target application.

Applications

• PV cell harvesting • Home automation

• Industrial monitoring • E-health monitoring

• Geolocation • Wireless sensor nodes

Features

Four two-way screw terminals

- Source of energy (PV cell)

- Low-voltage load

- High-voltage load

- Primary energy storage elem e n t

One three-way screw terminal

- Energy storage element (battery or (super)capacitor)

One zero insertion force (ZIF) connector

- Alternative connection for the source

One 2-pin ”Shrouded Header”

- Alternative connection for the storage el e m e n t

Eight 3-pin headers

- Maximum power point (MPP) conﬁguration

- Low drop-out regulators (LDOs) ena b ling

- Energy storage elements and LDOs conﬁguration

- Dual-cell supercapacitor conﬁguration

Three 2-pin headers

- Primary battery conﬁguration

- Cold-start conﬁguration

Provision for ten resistors

- Custom mode conﬁguration

- Cold start conﬁguration

- Primary battery conﬁguration

Three 1-pin headers

- Access to status pins

Appearance

Device information

Part number Dimensions

2AAEM10941C0022 76 mm x 50 mm

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AEM10941

List of Figures

1 Connection diagram . . . . . . . . . . . . . . . . . 3

2 STATUS[0] and HLDO evolution with BATT . . . . 7

3 SRC and STATUS[2] while energy is extracted from

SRC (BATT under Vovch) . . . . . . . . . . . . . . 7

4 LDOs disab led around 600 ms after BATT reaches

Vovdis . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 Switching from SRC to the primary battery . . . . . 8

6 AEM10941 behaviour during cold start . . . . . . . 9

7 HVOUT at 2.5V . . . . . . . . . . . . . . . . . . . 10

8 Boost eﬃciency for ISRC = 1mA . . . . . . . . . . 11

9 PV cell ﬁrst order model . . . . . . . . . . . . . . . 12

10 Typical I-V curve of a PV cell for high and low illu-

mination level 11 Typical power-V curve of a PV cell for high and low

illumination level . . . . . . . . . . . . . . . . . . . 12

. . . . . . . . . . . . . . . . . . . . . 12

List of Tables

1 Pin description . . . . . . . . . . . . . . . . . . . . 4

2 Usage of CFG[2:0] . . . . . . . . . . . . . . . . . . 5

3 LDOs enabling . . . . . . . . . . . . . . . . . . . . 5

4 Usage of SELMPP[1:0] . . . . . . . . . . . . . . . . 5

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Storage element

Mandatory connecon BAL (do



ed line) oponal

If BAL pin is used, use a jumper to connect

«BAL» to «ToCN» or to «GND» if not used

See Sec



on 2.3.4

Source element

Leave oang if not used

Primary baery

Mandatory connecon Connect a jumper to

each «NoPRIM» 2-pins or connect the ba



ery

See Sec



on 2.3.2

High-voltage LDO output

Leave oang if not used

Low-voltage LDO output

Leave oang if not used

+

-

MPP conguraon

Mandatory connecon See Table 4

Baery & LDOs con



guraon

Mandatory connecon

See Table 2

LDOs enabling

Mandatory

connec



on

See Table 3

Cold-start con



guraon

Mandatory connecon Connect a jumper to

«FB_COLD» 2-pins or use the resistors

See Sec



on 2.3.3

PV Cell

+ -

Warning

Please refer to Sec



on 2.1 before connecng the board

A 150 µF capacitor CBATT is already soldered on BATT

High voltage

load

Low voltage

load

Custom mode con



guraon

Leave oang if not used See Sec



on 2.3.1

1

Figure 1: Connection diagram

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 2018 e-peas SA

c

1 Connections Diag ram

User guide

3UG AEM10941 REV1.0

AEM10941

User guide

1.1 Signals description

NAME FUNCTION CONNECTION

Power signals

LVOUT

HVOUT

BAL

BATT

PRIM

SRC

Debug signals

VBOOST

VBUCK

BUFSRC

Conﬁguration signals

CFG[2]

CFG[1]

CFG[0]

SELMPP[1]

SELMPP[0]

FB

PRIM

FB HV

FB COLD

Control signals

ENHV

ENLV

Status signals

STATUS[2]

STATUS[1]

STATUS[0]

Output of the low-voltage L DO regulator.

Output of the high-voltage LDO regulator.

Connection to mid-point of a dual-cell supercapacitor.

Connection to the energy storage element.

Connection to the primary battery.

Connection to the harvested energy source.

Output of the boost converter.

Output of the buck converter.

Connection to an external capacitor buﬀering the boost converter input.

Conﬁguration of the threshold voltages for the energy storage element and the outp ut voltage of the LDOs.

Conﬁguration of the MPP ratio.

Conﬁguration of the primary battery.

Conﬁguration of the high-voltage LDO in the custom mode.

Conﬁguration of the cold start.

Enabling pin for the high-voltage LDO.

Enabling pin for the low-voltage LDO.

Logic output. Asserted when the AEM performs the MPP evaluation. Logic output. Asserted if the battery voltage falls under Vovdis or if the AEM is taking energy from the primary battery.

Logic output. Asserted when the LDOs can be enabled.

If used If not used

Connect a load.

Connect mid-point and jumper BAL to ”ToCN”. Connect storage element in addition to CBATT (150

Connect primary battery.

Connect the source element.

Connect jumper (see Table 2).

Connect jumper (see Table 4).

Use resistors R7-R8 (see Section 2.3.2).

Use resistors R5-R6 (see Section 2.3.1).

Use resistors R9-R10 (see Section 2.3.3).

Connect jumper (see Table 3).

AEM10941

Use a jumper to connect ”BAL” to ”GND”.

Do not remove

µ

F).

CBATT.

Connect a jumper to each NoPRIM 2-pins.

Leave ﬂoating.

Cannot be left ﬂoating (see Table 2).

Cannot be left ﬂoating (see Table 4).

Connect a jumper to each NoPRIM 2-pins.

Leave ﬂoating.

Connect a jumper to FB

COLD 2-pins if

not used.

Cannot be left ﬂoating (see Table 3).

Table 1: Pin description

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User guide

2 General Consideratio ns

2.1 Safety information

Always connect the elements in the following order:

1. Reset the board - see ”How to reset the AEM 10941 evaluation board” on page 7.

2. Completely conﬁgure the PCB (jumpers/resistors);

- MPP conﬁguration (SELMPP[0], SELMPP[1]) - see Table 4,

- Battery and LDOs conﬁguration (CFG[0], CFG[1], CFG[2] and, if needed, R1-R2-R3-R4 -R5-R6) - see Table 2,

- Primary battery conﬁguration (NoPRIM or R 7-R8) - see Section 2.3.2,

- LDOs enabling (ENHV and ENLV) - see Table 3,

- Cold-start conﬁguration (FB COLD or R9-R10) - see Section 2.3.3,

- Balun circuit connection (BAL) - see Section 2.3.4.

3. Connect the storage elements on BATT and optionally the primary battery on PRIM.

4. Connect the high and/or low voltage loads on HVOUT/LVOUT (optional).

5. Connect the source element on SRC.

AEM10941

To avoid damage to the board, users are urged to follow th is procedure.

2.2 Basic conﬁgurations

The MPP conﬁguration is not available on the AEM10941 evaluation board. The MPP is by default conﬁgured to 50 % of

Voc as this ratio optimize the proposed rectiﬁer eﬃciency.

Conﬁguration pins Storage element threshold voltages LDOs output voltages Typical use

CFG[2] CFG[1] CFG[0] Vovch Vchrdy Vovdis Vhv Vlv

H H H 4.12 V 3.67 V 3.60 V 3.3 V 1.8 V Li-ion battery H H L 4.12 V 4.04 V 3.60 V 3.3 V 1.8 V Solid state battery H L H 4.12 V 3.67 V 3.01 V 2.5 V 1.8 V Li-ion/NiMH battery H L L 2.70 V 2.30 V 2.20 V 1.8 V 1.2 V Single-cell (super) capac-

itor L H H 4.50 V 3.67 V 2.80 V 2.5 V 1.8 V Dual-cell supercapacitor L H L 4.50 V 3.92 V 3.60 V 3.3 V 1.8 V Dual-cell supercapacitor L L H 3.63 V 3.10 V 2.80 V 2.5 V 1.8 V LiFePO4 battery L L L Custom mode - see Section 2.3.1 1.8 V

Table 2: Usage of CFG[2:0]

ENLV ENHV LV output HV output

H H Enabled Enabled H L Enabled Disabled

L H Disabled Enabled L L Disabled Disabled

SELMPP[1] SELMPP[0] Vmpp/Voc

L L 70%

L H 75% H L 85% H H 90%

Table 3: LDOs enabling

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Table 4: Usage of SELMPP[1:0]

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AEM10941

2.3 Advanced conﬁgurations

A complete description of the system constraints and conﬁgurations is available in Section 8 ”System conﬁguration” of the AEM10941 datasheet . A reminder on how to compute the conﬁguration resistors value is provided below. Calculation can be made with the help of the spreadsheet found at the e-peas website.

2.3.1 Custom mode

In addition to the pre-deﬁned protection levels, the custom mode allows use rs to deﬁ ne their own levels via resistors R1 to R4 a n d to tune the output of the high voltage LDO via resistors R5-R6. By deﬁning RT = R1+R2+R3+R4 (1 MΩ ≤ RT ≤ 100 MΩ):

• R1 = RT (1 V /

• R2 = RT (1 V /

• R3 = RT (1 V /

• R4 = RT (1 - 1 V /

By deﬁning RV = R5+R6 (1 MΩ ≤ RV ≤ 40 MΩ):

• R5 = RV (1 V /

• R6 = RV (1 - 1 V /

Make sure the protection levels satisfy the following conditions:

Vchrdy + 0.05 V ≤ Vovch ≤ 4.5 V

-

Vovdis + 0.05V ≤ Vchrdy ≤ Vovch - 0.0 5 V

- 2.2 V ≤

- Vhv ≤ Vovdis - 0.3 V

If unused, leave the resistor footprints (R1 to R6) empty.

Vovdis

Vovch)

Vchrdy - 1 V / Vovch)

Vovdis - 1 V / Vchrdy)

Vovdis)

Vhv)

2.3.2 Primary battery conﬁguration

As to the main storage element, the primary battery protection levels have to be deﬁned. To do so , use resistors R7-R8. By deﬁning RP = R7+R8 (100 kΩ ≤ RP ≤ 500 kΩ):

• R7 = (

• R8 = RP - R7

If unused, connect a jumper to each ”NoPRIM” 2-pins.

2.3.3 Cold-start conﬁguration

The cold-start voltage (i.e. the voltage needed at startup to turn on the AEM10941) is by default at its minimum value of 380 mV. This voltage can be tuned by the use of resistors R9-R10. By deﬁning RC = R9+R10 (100 kΩ ≤ RC ≤ 10 MΩ):

• R9 = (

• R10 = RC - R9

If unused, connect a jumper to ”FB COLD” 2-pins.

2.3.4 Balun circuit conﬁguration

When using a dual-cell s u percapacitor (that does not already include a balancing circuit), enable the balun circuit conﬁguration to ensure equal voltage on both cells. To do so:

- Connect the node between the two supercapacitor cells to BAL (on BATT connector)

- Use a jumper to connect ”BAL” to ”ToCN”

If unused, use a jumper to connect ”BAL” to ”GND”.

Vprim min

4

0.38 V

* RC)

Vcs

* RP) / 2.2 V

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5s

User guide

AEM10941

How to reset the AEM10941 evaluation board:

To reset the board, si mp ly

disconnect the storage device and the optional primary battery and connect the 6 ”Reset”

connections (working from the rightmost to the left) to a GND node (i.e. the negative pin of any connector) in order to discharge the internal nodes of the system.

-

3 Functional Tests

HLDO/LLDO: Regulated when voltage on BATT ﬁrst

rises above Vchrdy (see Figure 2).

This section presents a few simple tests that allow the user to understand the functional behavior of the AEM10941.

To avoid damaging the board, follow the procedure found in Section 2.1 ”Safety information”.

If a test has to be restarted, make sure to properly reset the system to obtain reproducible results.

STATUS[0]: Asserted when the LDOs are ready to be

enabled (refer to Section 7.2 ”Normal mo d e” of the AEM10941 datasheet) (see

STATUS[2]: Asserted each time the AEM10941 per-

forms a MPP evaluation (see

Figure 2).

Figure 3). The following functional tests were mad e using the following setup:

- Conﬁguration:

ENLV = H, ENHV = H

SELMPP[1:0] = LL, CFG[2:0] = HLL,

Vchrdy

BATT HLDO

2

STATUS[0]

- Storage element: capacitor (4.7 mF + CBATT)

- Load: 10 kΩ on

-

SRC: current source (1 mA or 100µA) with vol ta ge com-

HVOUT, LVOUT ﬂoating

pliance (4 V)

Feel free to adapt the setup to match your system as long as you respect the input and cold-start constraints (see Section 1 ”Introduction” of AEM10941 datasheet).

3.1 Start-up

The following example allows users to observe the behavior of the AEM10941 in the wake-up mode.

Setup

1. Place the probes on the nodes to be observed.

2. Referring to Section

Observations and measurements

- BATT: Voltage rises as the power provided by the so u rce is transferred to the storage element (see

-

SRC: Regulated at Vmpp, whi c h is a voltage equal to the

open-circuit voltage ( in Table 4. Vsrc equals Voc during MPP evaluation (see Figure 3). N ote that Vsrc must be higher than 380 mV to coldstart.

Figure 1, follow steps 1 to 5 explained in

2.1.

Figure 2).

Voc) times the MPP ratio deﬁned

1

Voltage [V]

0

0 5 10 15 20

Time [s]

Figure 2: STATUS[0] and HLDO evolution with BATT

SRC

Time [s]

Vmpp

Voltage [V]

STATUS[2]

4

Voc

3

2

1

0

0 5 10 15 20

Figure 3: SRC and STATUS[2] while energy is ex- tracted from SRC (BATT under Vovch)

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600ms

User guide

AEM10941

3.2 Shutdown

This test allows users to observe the behavior of the AEM10941 when the system is running out of energy.

Setup

1. Place the probes on the nodes to be observed.

2. Referring to Section and start the system (see Section 3.1). Do not use a primary battery.

3. Let the system reach a steady stat e (i.e. voltage on

BATT between Vchrdy and Vovch and STATUS[0] as-

serted).

4. Remove your source element and let the system discharge through quiescent current and load(s).

Observations and measurements

-

BATT: Voltage decreases as the system consumes the

power accumulated in the s torage element. The voltage remains stable after crossing

-

STATUS[0]: De-asserted when the LDOs are no longer

available as the storage element is running out of energy. This happens 600 ms after

Figure 4).

(see

STATUS[1]: Asserted for 600 ms when the storage ele-

ment voltage (BATT) falls below Vovdis (see Figure 4).

Figure 1, follow steps 1 to 5 explained in

2.1. Conﬁgure the board in the desired state

HVOUT/LVOUT

Vovdis (see Figure 4).

STATUS[1] assertion

Setup

1. Place the probes on the nodes to be observed.

2. Referring to Section 2.1. Conﬁgure the board in the desired state and start the system (see Section battery (example: 3.1 V coin cell with protection level at 2.4 V, R7 = 68 kΩ and R8 = 180 kΩ).

3. Let the system reach a steady state (i.e. voltage on

BATT between Vchrdy and Vovch and STATUS[0] as-

serted).

4. Remove your source element and let the system discharge through quiescent current and load(s).

Observations and measurements

BATT: Voltage decrease s as the system consumes the

power accumula te d in the storage element. The voltage reaches Vovdis and then rise s again to Vchrdy as it is recharged from the primary battery (see

STATUS[0]: Never de-asserted as the LDOs are still

functional (see

HLDO: Stable and not aﬀected by switching on the pri-

mary battery (see

Vchrdy

Vovdis

Voltage [V]

Figure 1, follow steps 1 to 5 explained in

3.1). Connect a primary

HVOUT/LVOUT

Figure 5).

3

2

1

STATUS[0]

BATT HLDO

3

BATT

Vovdis

Figure 4: LDOs disabled around 600 ms after BATT reaches Vovdis

2

1

Voltage [V]

0

0 5 10 15 20

STATUS[1] STATUS[0]

Time [s]

3.3 Switching on primary battery

This example allows users to observe switching from the main storage element to the primary battery when the system is running out of energy.

0

0 5 10 15 20

Time [s]

Figure 5: Switching from SRC to the primary battery

3.4 Cold start

The following test allows users to observe the minimum voltage required to coldstart the AEM10941. Be careful to avoid probing an y unnecessary node to avoid leakage current induced by the probe. Make sure to properly reset the board to observe the cold-start behavior.

Setup

1. Place the probes on the nodes to be observed.

2. Referring Figure 1, follow steps 1 and 2 explained in Section Connect the jumper FB COLD. Do not plug any storage element in addition to CBATT.

3. SRC: Connect your source element.

2.1. Conﬁgure the board in the desired state.

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Observation and measurements

- SRC: Equal to the cold-start voltage during the coldstart phase. Regulated at the selected MPPT percentage of careful that the cold-start phase time will shorten with the input power. Limit it to ease the observation.

BATT: Starts to charge when the cold-start phase is over

(see Figure 6).

Voc wh en cold start is over (see Figure 6). Be

SRC BATT

1

0.75

0.5

Vcs

Voltage [V]

0.25

0

0 1 2 3 4 5 6

Time [s]

Figure 6: AEM10941 behaviour during cold start

3.5 Dual-cell supercapacitor balancing circuit

This test allows users to observe the balancing circuit behavior that maintains the voltage on BAL equilibrated.

Setup

1. Following steps 1 and 2 explained in Section ferring to Figure 1, conﬁgure the board in the desired state. Plug the jumper linking ”BAL” to ”ToCN”.

BATT: Plug capacitor C1 between the positive (+) and

2. the BAL pins and a capacitor C2 between BAL and the negative (-) pins. Select C1 6= C2 such that:

- C1 & C2 > 1 mF

C2∗

Vchrdy

-

3.

SRC: Plug your source element to start the ﬂow of power

to the system.

Measurements

BAL: Equal to half the voltage on BATT.

-

C1

≥ 0.9 V

2.1 and re-

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Warning regarding measurements:

Any item connected to the PCB (load, probe, storage device, etc.) involves a leakage current. This can negatively impact the measurements. Whenever possib le, disconnect unused items to limit this eﬀect.

AEM10941

4 Performance Tests

This section presents the tests to reproduce the performance graphs found in the AEM10941 d a t a sheet and to unde rstand the functionalities of the AEM10941. To be able to reproduce those tests, you will need the following:

- 1 voltage source

- 2 source measure units (SMUs)

- 1 oscilloscope

To avoid damaging the board, follow the procedure found in Section 2.1 ”Safety information”.

make sure to properly reset the system to obtain reproducible results (see on page 7).

”How to reset the AEM10941 evaluation board”

4.1 LDOs

The following example instructs users on how to measure the output voltage stability of the LDOs (Figure 16 and Figure 17 of AEM10941 datasheet).

Setup

1. Referring to Section 2.1. Conﬁgure the board in the desired state and plug your storage element(s).

2. VBOOST: Connect SMU1. Conﬁgure it to sou rce voltage with a current compliance of 200 mA.

3. HVOUT / LVOUT: Connect SMU2 to the LDO you want to measure. Conﬁgure it to sink current with a vo ltage compliance of 5 V for HVOUT or 2.5 V for LVOUT.

Figure 1, follow steps 1 and 2 explained i n

If a test has to be restarted,

2.6

2.5

2.4

VHVOUT [V]

2.3

IHVOUT = 10µA IHVOUT = 10 mA IHVOUT = 80 mA

3 3.5 4 4.5

VBOOST [V]

Figure 7: HVOUT at 2.5V

4.2 BOOST eﬃciency

This test allows users to reproduce the eﬃciency graphs of the boost converter (Figure 14 of AEM1094 1 datasheet).

Setup

1. Following steps 1 and 2 explained in Section 2.1 and referring to state.

2. VBUCK: Connect a 2.3V voltage source to prevent

VBUCK to sink from VBOOST.

3.

SRC: Co n nect SMU1. Conﬁgure it to source current

with a voltage compliance of 0 V.

4. VBOOST: Connect SMU2. Conﬁgure it to source voltage with a current compliance of 200 mA.

STATUS[2]: Connect to one of the SMUs to dete c t

5. falling edge.

Figure 1, conﬁgu re the board in the desired

Manipulations

1. Impose a voltage between force the AEM to start.

2. Sweep voltage on SMU1 from Vovdis + 50 mV to 4.5 V.

3. Repeat with diﬀerent current levels on SMU2 (from 10

µ

A to 80 mA for HVOUT and from 10µA to 20 mA

for LVOUT).

Measurements

HVOUT/LVOUT: Measure the voltage.

-

Vovch and 5 V on SMU1 to

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Manipulations

1. Impose a voltage between force the AEM to start. When done, impose a volta ge between Vovdis + 50 mV and Vovch.

2. Sweep voltage compliance on SMU1 from 50 mV to 5 V.

3. Repeat with diﬀerent current levels on SMU1 (from

µ

A to 100 mA) and with diﬀerent voltage levels on

100 SMU2 (from Vovdis + 50 mV to Vovch).

Measurements

-

STATUS[2]: Do not make any measurements while high

(boost converter is not active during MPP calculation).

- SRC: Measure the current and the voltage.

Vchrdy and 5 V on SMU2 to

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AEM10941

- VBOOST: Measure the current and the voltage. Repeat the measurement a copious number of times to be sure to capture the current peaks. tained by averaging over 100 measurements conﬁgured with a 100 ms integration time.

- Deduce input and output power (P = U ∗ I) and eﬃ ciency (η = P out/P in).

100

80

60

Eﬃciency [%]

40

0 1 2 3 4

VSRC [V]

Figure 8: Boost eﬃciency for ISRC = 1 mA

Figure 8 has been ob-

VBOOST = 2.6 V VBOOST = 3.6 V VBOOST = 4.1 V

4.3 Custom mode conﬁguration

This test allows users to measure the custom protection levels of the storage e lement set by resistors R1 to R6.

Setup

1. Referring to in Section 2.1. Connect CFG[2:0] = LLL to select custom mode and choose R1 to R6 to conﬁgure the battery protection levels and

2. Place the probes on the nodes to be observed.

3.

SRC: Connect your source element to start the ﬂow of

power to the system.

Manipulations

1. Remove the sou rce el e m e n t after the voltage on has reached steady state (between Vchrdy and Vovch).

Measurements

Measure the following nodes to ensure the correct behaviour of the AEM10941 with respect to the custom conﬁguration:

- STATUS[0]: Asserted when the LDOs can be e n abled (i.e. when BATT ﬁrst rises above Vchrdy).

STATUS[1]: Asserted when BATT falls below Vovdis.

-

BATT: Rise up and osci llate around Vovch as long as

the source element has not been removed.

-

HVOUT: Equal to the value set by R5-R6.

Figure 1, follow steps 1 and 2 explained

HVOUT output voltage.

BATT

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AEM10941

5 PV cell characterization

+

Isc

Figure 9: PV cell ﬁrst order model

A photovoltaic cell can be mo deled at ﬁrst approximation by a light-controlled current source in parallel with a diode as illustrated in characteristics of a PV cell: open-circuit voltage (Voc) and short-circuit current (Isc). The open-circuit vol t a ge corresponds to the forward vo ltage of the diode at no load while the short-circuit current is the current delivered by the current source (i.e. when shorting the + and - terminals).

Figure 9. This allows to model the two main

Voc

-

Typical current vs voltage graph of a PV cell for diﬀerent illumination levels can be observed in Figure 10. Knowing that P = I ∗ V , th e associated power vs voltage curves can be drawn as shown in imum extracted power is achieved at a voltage corresponding to a given ratio of the open-circuit voltage (between 70% and 90%). This ratio is, in ﬁrst approximation, independent of the illumination level: as can be seen in As presented in Table 4, the MPP conﬁguration of the AEM10941 allows you to select the voltage ratio that optimizes the power extraction according to the characteristics of your PV cell.

Optimal power

Figure 11. For a given technology, the max-

Figure 11,

High illumination Low illumination

Power

Vmpp VocVoc

Vmpp

Vout

Vmpp

Voc

Vmpp

≈

Voc

.

High illumination Low illumination

Isc

Iout

Isc

Voc Voc

Vout

Figure 10: Typical I-V curve of a PV cell for high and low illumination level

Figure 11: Typical power-V curve of a PV cell for hi gh and low illumination level

As can be seen in Figure 11, the power signiﬁcantly decreases with the voltage beyond the optimum Vmpp. It is then recommended to conﬁgure the than th e theoretical optim u m and therefore avoid a signiﬁcant drop of performance.

Vmpp/Voc ratio to be slightly lower

Copyrightc 2018 e-peas SA

12UG AEM10941 REV1.0

E-peas AEM10941 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

List of Figures

List of Tables

1 Connections Diag ram

1.1 Signals description

2 General Consideratio ns

2.1 Safety information

3 Functional Tests

3.1 Start-up

3.2 Shutdown

3.3 Switching on primary battery

3.4 Cold start

3.5 Dual-cell supercapacitor balancing circuit

4 Performance Tests

4.1 LDOs

5 PV cell characterization