eorex EM6128K800V User Manual

128Kx8 LP SRAM EM6128K800V Series

GENERAL DESCRIPTION

The EM6128K800V is a 1,048,576-bit low power CMOS static random access memory organized as
131,072 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology.
Its standby current is stable within the range of operating temperature.
The EM6128K800V is well designed for low power application, and particularly well suited for battery
back-up nonvolatile memory application.
The EM6128K800V operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are
fully TTL compatible

FEATURES

z Fast access time: 35/55/70ns
z Low power consumption:

Operating current:
12/10/7mA (TYP.)
Standby current: -L/-LL version
20/1µA (TYP.)

z Single 2.7V ~ 3.6V power supply
z All inputs and outputs TTL compatible
z Fully static operation

z Tri-state output
z Data retention voltage: 1.5V (MIN.)
z Package:

32-pin 450 mil SOP
32-pin 600 mil P-DIP
32-pin 8mm x 20mm TSOP-I
32-pin 8mm x 13.4mm STSOP
36-ball 6mm x 8mm TFBGA

FUNCTIONAL BLOCK DIAGRAM

Vcc
Vss

A0-A16

DQ0-DQ7

CE#
WE#
OE#
CE2

DECODER

CURCUIT

CONTROL

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A16 Address Inputs
DQ0 – DQ7 Data Inputs/Outputs
CE#, CE2 Enable Input
WE# Write Enable Input
OE# Output Enable Input
Vcc
Vss Ground

Power Supply

I/O DATA

CIRCUIT

128Kx8

MEMORY

ARRAY

COLUMN I/O

1 DCC-SR-041004-A

128Kx8 LP SRAM EM6128K800V Series

PIN CONFIGURATION

SOP/P-DIP

A4

A3

A2

A1

A0

CE#

DQ0

DQ1

DQ2

DQ3

Vcc

Vss

DQ4

DQ5

DQ6

DQ7

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

A5

A6

A7

OE#

UB#

LB#

DQ15

DQ14

DQ13

DQ12

Vss

Vcc

DQ11

DQ10

DQ9

DQ8

TSOP-I/STSOP

A11
A9
A8
A13
WE#
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3

2 DCC-SR-041004-A

128Kx8 LP SRAM EM6128K800V Series

TFBGA

A A0 A1 CE2 A3 A6 A8
B DQ4 A2 WE# A4 A7 DQ0
C DQ5 NC A5 DQ1
D Vss Vcc
E Vcc Vss

F DQ6 NC NC DQ2
G DQ7 OE# CE# A16 A15 DQ3
H A9 A10 A11 A12 A13 A14

1 2 3 4 5 6

3 DCC-SR-041004-A

128Kx8 LP SRAM EM6128K800V Series

ABSOLUTE MAXIMUN RATINGS*

PARAMETER SYMBOL RATING UNIT

Terminal Voltage with Respect to Vss VTERM -0.5 to 4.6 V

0 to 70(C grade)

Operating Temperature TA

-20 to 80(E grade)

°C

-40 to 85(I grade)

Storage Temperature TSTG -65 to 150 °C

Power Dissipation PD 1 W

DC Output Current IOUT 50 mA

Soldering Temperature (under 10 sec) TSOLDER 260 °C

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device
reliability.

TRUTH TABLE

MODE CE# OE# WE# I/O OPERATION SUPPLY CURRENT

Standby H X X High-Z ISB,ISB1
Output Disable L H H High-Z ICC,ICC1
Read L L H DOUT ICC,ICC1
Write L X L DIN ICC,ICC1

Note: H = VIH, L = VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITION MIN. TYP.

Supply Voltage Vcc
Input High Voltage VIH*1

Input Low Voltage VIL*2
Input Leakage

ILI Vcc ≧ VIN ≧ Vss -1 - +1 µA

2.7 3.0 3.6 V

2.0 - Vcc+

-0.2 - 0.6 V

Current
Output Leakage
Current
Output High

ILO VCC ≧ VOUT ≧ VSS,

Output Disabled

-1 - 1 µA

VOH IOH = -1mA 2.2 2.7 - V

Voltage
Output Low

VOL IOL = 2mA - - 0.4 V

Voltage
Average Operating
Power supply
Current

ICC Cycle time = Min.

CE# = VIL , II/O = 0mA

I

CC1 Cycle time = 1µs

-35 - 12 35 mA

-55 - 10 30 mA

-70 - 7 25 mA

- 1 5 mA

CE#≦0.2V and II/O = 0mA

Standby Power
Supply Current

other pins at 0.2V or V

ISB CE# = VIH

I

SB1 CE# V ≧ VCC - 0.2V

CC-0.2V

- 0.3 0.5 mA

-L - 20 80 µA

-LL 1 10 µA

Notes:

1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.

2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.

3. Over/Undershoot specifications are characterized, not 100% tested.

4. 10µA for special request

5. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25°C

*5 MAX. UNIT

V

0.3

4 DCC-SR-041004-A

128Kx8 LP SRAM EM6128K800V Series

CAPACITANCE (TA = 25°C , f = 1.0MHz)

PARAMETER SYMBOL MIN. MAX. UNIT

Input Capacitance CIN
Input/Output Capacitance CI/O

Note : These parameters are guaranteed by device characterization, but not production tested.

-

-

6 pF
8 pF

AC TEST CONDITIONS

Input Pulse Levels 0.2V to VCC - 0.2V
Input Rise and Fall Times 3ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA

AC ELECTRICAL CHARACTERISTICS

READ CYCLE

PARAMETER SYM.

Read Cycle Time tRC 35 - 55 - 70 - ns
Address Access Time tAA - 35 - 55 - 70 ns
Chip Enable Access Time tACE - 35 - 55 - 70 ns
Output Enable Access Time tOE - 25 - 30 - 35 ns
Chip Enable to Output in Low-Z tCLZ* 10 - 10 - 10 - ns
Output Enable to Output in Low-Z tOLZ* 5 - 5 - 5 - ns
Chip Disable to Output in High-Z tCHZ* - 15 - 20 - 25 ns
Output Disable to Output in High-Z tOHZ* - 15 - 20 - 25 ns
Output Hold from Address Change tOH 10 - 10 - 10 - ns

-35 -55 70

MIN. MAX. MIN. MAX. MIN. MAX.

UNIT

WRITE CYCLE

PARAMETER SYM.

Write Cycle Time tWC 35 - 55 - 70 - ns
Address Valid to End of Write tAW 30 - 50 - 60 - ns
Chip Enable to End of Write tCW 30 - 50 - 60 - ns
Address Set-up Time tAS 0 - 0 - 0 - ns
Write Pulse Width tWP 25 - 45 - 55 - ns
Write Recovery Time twr 0 - 0 - 0 - ns
Data to Write Time Overlap tDW 20 - 25 - 30 - ns
Data Hold from End of Write Time tDH 0 - 0 - 0 - ns
Output Active from End of Write tOW* 5 - 5 - 5 - ns
Write to Output in High-Z tWHZ* - 15 - 20 - 25 ns

*These parameters are guaranteed by device characterization, but not production tested.

-35 -55 70

MIN. MAX. MIN. MAX. MIN. MAX.

UNIT

5 DCC-SR-041004-A