EON EN29F002A, EN29F002AN User Manual

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EN29F002A / EN29F002AN 2 Megabit (256K x 8-bit) Flash Memory

EN29F002A / EN29F002AN

FEATURES

• 5.0V ± 10% for both read/write operation

• Read Access Time

- 45ns, 55ns, 70ns, and 90ns

Fast Read Access Time

•

- 70ns with C

- 45ns, 55ns with C

Sector Architecture:

•

One 16K byte Boot Sector, Two 8K byte

Parameter Sectors, one 32K byte and three 64K byte main Sectors

• Boot Block Top/Bottom Programming Architecture

• High performance program/erase speed

- Byte program time: 10µs typical

- Sector erase time: 500ms typical

- Chip erase time: 3.5s typical

Low Standby Current

•

- 1µA CMOS standby current-typical

- 1mA TTL standby current

• Low Power Active Current

- 30mA active read current

- 30mA program / erase current

• JEDEC Standard program and erase commands

= 100pF

load

= 30pF

• JEDEC standard bits feature

Hardware

•

• Single Sector and Chip Erase

• Sector Protection / Temporary Sector

Unprotect (

Sector Unprotect Mode

•

• Embedded Erase and Program Algorithms

• Erase Suspend / Resume modes:

Read and program another sector during Erase Suspend Mode

0.23 µm triple-metal double-poly

•

triple-well CMOS Flash Technology

• Low Vcc write inhibit < 3.2V

100K endurance cycle

•

Package Options

•

- 32-pin PDIP

- 32-pin PLCC

- 32-pin TSOP (Type 1)

Commercial and Industrial Temperature

•

Ranges

RESET

polling and toggle

DATA

(n/a on EN29F002AN)

= VID)

GENERAL DESCRIPTION

The EN29F002A / EN29F002AN is a 2-Megabit, electrically erasable, read/write non-volatile flash memory. Organized into 256K words with 8 bits per word, the 2M of memory is arranged in seven sectors (with top/bottom configuration), including one 16K Byte Boot Sector, two 8K Byte Parameter sectors, and four main sectors (one 32K Byte and three 64K Byte). Any byte can be programmed typically at 10µs. The EN29F002A / EN29F002AN features 5.0V voltage read and write operation. The access times are as fast as 45ns to eliminate the need for WAIT states in high-performance microprocessor systems.

The EN29F002A / EN29F002AN has separate Output Enable ( Enable ( either single sector or full chip erase operation, where each sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each sector.

) controls which eliminate bus contention issues. This device is designed to allow

), Chip Enable (CE), and Write

Rev. A, Issue Date: 2003/03/26

EN29F002A / EN29F002AN

TABLE 1. PIN DESCRIPTION FIGURE 1. LOGIC DIAGRAM

Pin Name Function

A0-A17 Addresses

DQ0-DQ7 Data Input/Outputs

CE OE

RESET

(n/a for EN29F002AN)

Chip Enable

Output Enable

Write Enable

Hardware Reset Sector Unprotect

Vcc Supply Voltage

(5V ± 10% )

Vss Ground

TABLE 2. BLOCK ARCHITECTURE

RESET

N/A on EN29F002AN

Vcc

EN29F002AT/B

Vss

DQ0 - DQ7A0 - A17

TOP BOOT BLOCK BOTTOM BOOT BLOCK

SECTOR

ADDRESSES

6 3C000h - 3FFFFh 16 30000h - 3FFFFh 64

5 3A000h - 3BFFFh 8 20000h - 2FFFFh 64

4 38000h - 39FFFh 8 10000h - 1FFFFh 64

3 30000h - 37FFFh 32 08000h - 0FFFFh 32

2 20000h - 2FFFFh 64 06000h - 07FFFh 8

1 10000h - 1FFFFh 64 04000h - 05FFFh 8

0 00000h - 0FFFFh 64 00000h - 03FFFh 16

SIZE (Kbytes)

ADDRESSES

SIZE (Kbytes)

Rev. A, Issue Date: 2003/03/26

BLOCK DIAGRAM

N/A on EN29F002AN

Vcc Vss

RESET

CE OE

Control

Command

State

EN29F002A / EN29F002AN

Block Protect

DQ0-DQ7

Erase Voltage Generator

Input/Output Buffers

Program Voltage

Generator

Chip Enable

STB

Output Enable

Logic

Data Latch

A0-A17

Y-Decoder

STB

TimerVcc Detector

X-Decoder

Y- G a t i n g

Cell Matrix

Address Latch

Rev. A, Issue Date: 2003/03/26

FIGURE 2. PDIP

NC on EN29F002AN

FIGURE 3. TSOP

EN29F002A / EN29F002AN

PDIP Top View

VPP

RESET

A16 A15 A12

DQ0 DQ1 DQ2 VSS

A7 A6 A5 A4 A3 A2 A1 A0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

VCC PGM

A14 A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3

NC on EN29F002AN

FIGURE 4. PLCC

RESET

PLCC Top View

A12 A16 VCC A17

A12 A16 VCC

A15 RESET WE

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

4232

5 6 7 8 9 10 11 12 13

14 16 18

DQ2 DQ3 DQ5

DQ1 VSS DQ4

EN29F002A

A15 VPP PGM

3131

15 17 19

DQ6

29 28 27 26 25 24 23 22 21

NC on EN29F002AN at RESET pin

A14 A13 A8 A9 A11 OE A10 CE DQ7

Rev. A, Issue Date: 2003/03/26

EN29F002A / EN29F002AN

TABLE 3. OPERATING MODES

2M FLASH USER MODE TABLE

USER MODE

RESET

(n/a on EN29F002AN)

STANDBY H X X H X X X X X X HI-Z READ L H L H A9 A8 A6 A1 A0 Ax/y DQ(0-7) OUTPUT DISABLE L H H H X X X X X X HI-Z READ MANUFACTURER ID READ DEVICE ID L H L H VID L/H L L H X DEVICE ID(T/B) VERIFY SECTOR PROTECT ENABLE SECTOR PROTECT SECTOR UNPROTECT L L VID H VID X H H L X X WRITE L L H H A9 A8 A6 A1 A0 Ax/y DIN(0-7) TEMPORARY SECTOR UNPROTECT

WE OE

X X X L X X X X X X HI-Z

L H L H VID L/H L L L X MANUFACTURER

L H L H VID X L H L X 01h(protected)

L L VID H VID X L X X X X

X X X VID X X X X X X X

RESET

A9 A8 A6 A1 A0 Ax/y DQ(0-7)

00h(unprotected)

NOTES:

1) L = V

2) X = Don’t care, either V

, H = VIH, VID = 11.0V ± 0.5V

or VIL

TABLE 4. DEVICE IDENTIFICTION

2M FLASH MANUFACTURER/DEVICE ID TABLE

A8 A6 A1 A0 DQ(7-0)

HEX

READ MANUFACTURER ID READ

MANUFACTURER ID READ DEVICE ID

(Top Architecture)

READ DEVICE ID* (Top Architecture) READ DEVICE ID (Bottom Architecture)

READ DEVICE ID* (Bottom Architecture)

NOTES:

These modes (A8=H) are recommended for Manufacture/Device ID check.

L L L L CONTINUATION MANUFACTURER ID

H L L L MANUFACTURER ID

L L L H CONTINUATION DEVICE ID

H L L H DEVICE ID

L L L H CONTINUATION DEVICE ID

H L L H DEVICE ID

Rev. A, Issue Date: 2003/03/26

EN29F002A / EN29F002AN

USER MODE DEFINITIONS

Reset Mode

EN29F002A features a Reset mode that resets the program and erase operation immediately to read mode. If reset (

program or erase which was terminated should be repeated since data will be corrupted. This pin is not available for EN29F002AN.

Standby Mode

The EN29F002A / EN29F002AN has a CMOS-compatible standby mode which reduces the to < 1µA (typical). It is placed in CMOS-compatible standby when

± 0.5 V (CE pin only, for EN29F002AN). The device also has a TTL-compatible standby mode

which reduces the maximum V and

pins are at VIH. Another method of entering standby mode uses only the

RESET

(n/a for EN29F002AN). When standby with current typically reduced to < 1 µA. When compatible standby with current reduced to < 1mA. When in standby modes, the outputs are in a high-impedance state independent of the

Read Mode

The EN29F002A / EN29F002AN has two control functions which must be satisfied in order to obtain data at the outputs. Chip Enable ( Output Enable (

) is the output control and should be used to gate data to the output pins,

provided the device is selected. Read is selected when both the

pin held at VIH. Address access time (t

valid output data. Assuming that addresses are stable, chip enable access time (t delay from stable

enable access time (t addresses have been stable for at least t

Output Disable Mode

When the

or OE pin is at a logic high level (VIH), the output from the EN29F002A /

EN29F002AN is disabled. The output pins are placed in a high impedance state.

Auto Select Identification Mode

The manufacturer and device type can be identified by hardware or software operations. This mode allows applications or programming equipment automatically matching the device with its corresponding interface characteristics.

To activate the Auto Select Identification mode, the programming equipment must force 11.0 V ±

0.5V on address line A9 of the EN29F002AT/B. Two identifier bytes can then be sequenced from the device outputs by toggling address lines A0 and A8 from V

The manufacturer and device identification may also be read via the command register. By following the command sequence referenced in the Command Definition Table (Table 5). This method is desirable for in-system identification (using only + 5.0V).

When A0 = A1 = A6 = V = 7F, 1C (hex) to identify EON . When A0 = V

= L) is executed when program or erase operation were in progress, the

RESET

current

and the

current to < 1mA. It is placed in TTL-compatible standby when CE

pin is at VSS ± 0.3V, the device enters CMOS-compatible

RESET

input.

) is the power control and should be used for device selection.

) is equal to the delay from stable addresses to

ACC

pin is at VIL, the device enters TTL-

and OE pins are held at VIL with

pins are at

RESE

RESET

) is equal to the

to valid data at output pins. Data is available at the outputs after output

) from the falling edge of OE, assuming the CE has been LOW and

and by toggling A8 from VIL to V

ACC

- tOE.

to VIH.

the Manufacturer ID can be read as Eon

IH,

, A1 = A6 = V

and by toggling A8 from V

IL,

to VIH,

Rev. A, Issue Date: 2003/03/26

EN29F002A / EN29F002AN

, is

the Device Code can be read as 7F, 92 (hex) for EN29F002AT or as 7F, 97 (hex) for EN29F002AB (See Table 4). All identifiers for manufacturer and device codes possess odd parity with the DQ7 defined as the parity bit.

Write Mode

Write is used for device programming and erase through the command register. This mode is selected with

the internal state machine. The command register is a set of latches used to store the commands along with the addresses and data information needed to execute that command. Address latching

occurs on the falling edge of rising edge of

= WE = L and OE = H. The contents of the command register are the inputs to

or CE (whichever occurs later) and data latching occurs on the

or CE (whichever occurs first).

Temporary Sector Unprotect Mode

EN29F002A allows protected sectors to be temporarily unprotected for making changes to data stored in a protected sector in system (n/a for EN29F002AN). To activate the temporary sector

unprotect, the can be programmed or erased by selecting the sector addresses. Once the high voltage, V

removed from

RESET

pin must be set to a high voltage of VID (11V). In this mode, protected sectors

pin, all previously protected sectors will revert to their protected state.

RESET Hardware Reset Mode

Resetting the EN29F002A device is performed when the least 500ns. The internal state machine will be reset to the read mode. Any program/erase operation in progress during hardware reset will be terminated and data may be corrupted.

If the

RESET

read mode and enable the system’s microprocessor to read the boot-up firmware from the FLASH memory.

pin is tied to the system reset command, the device will be automatically reset to the

(not available on EN29F002AN)

RESET

pin is set to VIL and kept low for at

COMMAND DEFINITIONS

The operations of the EN29F002A are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Table (Table 5). Incorrect addresses, incorrect data values or improper sequences will reset the device to the read mode.

Rev. A, Issue Date: 2003/03/26

EN29F002A / EN29F002AN

Table 5. EN29F002A Command Definitions

Command Sequence

Read/Reset

AutoSelect Manufacturer ID

AutoSelect Device ID

(Top Boot)

AutoSelect Device ID

(Bottom Boot)

AutoSelect Sector Protect Verify

Byte Program

Chip Erase

Sector Erase

Sector Erase Suspend

Sector Erase Resume

Write

Cycles

Req’d

1 XXXh F0h RA RD 4 555h AAh AAAh 55h 555h F0h RA RD 4 555h AAh AAAh 55h 555h 90h 000h/

4 555h AAh AAAh 55h 555h 90h 001h/

4 555h AAh AAAh 55h 555h 90h SA &

4 555h AAh AAAh 55h 555h A0h PA PD 6 555h AAh AAAh 55h 555h 80h 555h AAh AAAh 55h 555h 10h 6 555h AAh AAAh 55h 555h 80h 555h AAh AAAh 55h SA 30h 1 xxxh B0h 1 xxxh 30h

Write Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Write Cycle

7Fh/

100h

1Ch 7Fh/

101h

92h

7Fh/

101h

97h

00h/

02h

01h

Notes:

RA = Read Address: address of the memory location to be read. This one is a read cycle. RD = Read Data: data read from location RA during Read operation. This one is a read cycle. PA = Program Address: address of the memory location to be programmed PD = Program Data: data to be programmed at location PA SA = Sector Address: address of the sector to be erased. Address bits A17-A13 uniquely select any sector. The data is 00h for an unprotected sector and 01h for a protected sector.

Byte Programming Command

Programming the EN29F002A is performed on a byte-by-byte basis using a four bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. The program operation is terminated automatically by an internal timer. Address is latched on the falling

edge of is first. The program operation is completed when EN29F002A returns the equivalent data to the programmed location.

Programming status may be checked by sampling data on DQ7 ( bit). Changing data from 0 to 1 requires an erase operation. When programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode.

EN29F002A ignores commands written during Byte Programming. If a hardware during Byte Programming, data at the programmed location may get corrupted. Programming is allowed in any sequence and across any sector boundary.

Chip Erase Command

An auto Chip Erase algorithm is employed when the Chip Erase command sequence is performed. Although the Chip Erase command requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles and the chip erase command, the user does not need

, whichever is last; data is latched on the rising edge of CE or WE, whichever

polling) or on DQ6 (toggle

DAT

RESET

6th

Write Cycle

occurs

Rev. A, Issue Date: 2003/03/26

EN29F002A / EN29F002AN

to do anything else after that, except check to see if the operation has completed. The Auto Chip Erase algorithm automatically programs and verifies the entire memory array for an all “0” pattern prior to the erase. Then the EN29F002A will automatically time the erase pulse width, verify the

erase, return the sequence count, provide a erase status through

POLLING (data on DQ7 is

DATA

“0” during the operation and “1” when completed, provided the status is not read from a protected sector), and returns to the READ mode after completion of Chip Erase.

Sector Erase Command

Sector Erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles, and the Sector Erase command. Any sector may be erased by latching any

address within the desired sector on the falling edge of latched on the rising edge of

. This device does not support multiple sector erase commands.

Sector Erase operation will commence immediately after the first 30h command is written. The first sector erase operation must finish before another sector erase command can be given.

The EN29F002A device automatically programs and verifies all memory locations in the selected sector for an all “0” pattern prior to the erase. Unselected sectors are unaffected by the Sector Erase command. The EN29F002A requires no timing signals during sector erase. Erase is completed when data on DQ7 becomes “1”, and the device returns to the READ mode after completion of Sector Erase.

Erase Suspend / Resume Command

Erase suspend allows interruption of sector erase operations to perform data reads from sector not being erased. Erase suspend applies only to Sector Erase operations.

EN29F002A ignores any commands during erase suspend other than the assertion of the pin (n/a for EN29F002AN) or Erase Resume commands. Writing erase resume continues erase operations. Addresses are DON’T CARE when writing Erase Suspend or Erase Resume commands.

EN29F002A takes 0.1 - 15 µs to suspend erase operations after receiving Erase Suspend command. Check completion of erase suspend by polling DQ7 and/or DQ6. EN29F002A ignores redundant writes of erase suspend command.

EN29F0002 defaults to erase-suspend-read mode while an erase operation has been suspended. While in erase-suspend-read mode, EN29F002A allows reading data in any sector not undergoing sector erase, which is treated as standard read mode.

Write the Resume command 30h to continue operation of Sector erase. EN29F002A ignores redundant writes of the Resume command. EN29F002A permits multiple suspend/resume operations during sector erase.

Sector Protect and Unprotect

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operation in previously protected sectors.

Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (V Inc. for an additional supplement on this feature.

) on address pin A9 and the control pins. Contact Eon Silicon Solution,

while the Erase Command (30H) is

RESET

Rev. A, Issue Date: 2003/03/26

EN29F002A / EN29F002AN

WRITE OPERATION STATUS

DQ7

DAT

The EN29F002A provides embedded operations. The

Erase, Chip Erase, Erase Suspend. (See Table 6)

When the Byte Programming is in progress, an attempt to read the device will produce the complement of the data last written to DQ7. Upon the completion of the Byte Programming, an attempt to read the device will produce the true data last written to DQ7. For the Byte Programming,

DATA

When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7

output during the read. For Chip Erase, the

rising edge of the sector erase

DATA

erased and not a protected sector. Otherwise, address used is in a protected sector.

Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable (

one instant of time and valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will be read on the subsequent read attempts.

The flowchart for diagram is shown in Figure 8.

DQ6 Toggle Bit I

The EN29F002A provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the embedded programming and erase operations. (See Table 6)

During an embedded Program or Erase operation, successive attempts to read data from the device at any address (by toggling

the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the

rising edge of the fourth valid after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after the last rising edge of the Sector Erase Command (30h)

2µs, then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all selected sectors are protected, DQ6 will toggle for about 100 µs. The chip will then return to the read mode without changing data in all protected sectors.

Toggling either

Polling

Polling on DQ7 to indicate to the host system the status of the

DATA

Polling feature is active during the Byte Programming, Sector

DATA

polling is valid after the rising edge of the fourth WE or CEpulse in the four-cycle sequence.

polling is valid after the rising edge of the sixth

DATA

or CE pulse in the six-cycle sequence. For Sector Erase,

Polling must be performed at any address within a sector that is being programmed or

) is low. This means that the device is driving status information on DQ7 at

Polling (DQ7) is shown on Flowchart 5. The

DATA

or CE) will result in DQ6 toggling between “zero” and “one”. Once

pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is

In Byte Programming, if the sector being written to is protected, DQ6 will toggle for about

or OE will cause DQ6 to toggle.

pulse.

DATA

polling may give an inaccurate result if the

pulse.

polling is valid after the last

DATA

Polling (DQ7) timing

DATA

Rev. A, Issue Date: 2003/03/26

EN29F002A / EN29F002AN

The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown in Figure 9

DQ5 Exceeded Timing Limits

DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a “1”. (The Toggle Bit (DQ6) should also be checked at this time to make sure that the DQ5 is not a “1” due to the device having returned to read mode.) This is a failure condition which indicates that the program or erase cycle was not

successfully completed. function under this condition. Setting the

conditions. The

The DQ5 failure condition will also appear if the user tries to program a “1” to a location that was previously programmed to a “0”. In this case, the device goes into Hang or Error mode out and never completes the Embedded Program Algorithm. Hence, the system never reads valid data on DQ7 and DQ6 never stops toggling. Once the device exceeds the timing limits, DQ5 will indicate a “1”. Please note that this is not a device failure condition since the device was used incorrectly. If timing limits are exceeded, reset the device. (See Table 6)

and

Polling (DQ7), Toggle Bit (DQ6) and Erase Toggle Bit (DQ2) still

DATA

to VIH will partially power down the device under those

pins will control the output disable functions as described in Table 3.

DQ3 Sector Erase Command Timeout

This device does not support multiple sector erase commands. DQ3 will go high immediately after the first 30h command (the sixth write cycle). Any extra 30h commands will be ignored (or taken as a resume command if erase suspended).

DQ2 Erase Toggle Bit II

In the sector erase operation, DQ2 will toggle with sector that is being erased. DQ2 will not toggle if the read address is not within the sector that is

selected to be erased. In the chip erase operation, however, DQ2 will toggle with regardless of the address given by the user. This is because all sectors are to be erased. (See Table 6)

or CE when a read is attempted within the

or CE

Rev. A, Issue Date: 2003/03/26

+ 24 hidden pages

EON EN29F002A, EN29F002AN User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual