EON EN29F002A, EN29F002AN User Manual

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EN29F002A / EN29F002AN 2 Megabit (256K x 8-bit) Flash Memory

EN29F002A / EN29F002AN

FEATURES

• 5.0V ± 10% for both read/write operation

• Read Access Time

- 45ns, 55ns, 70ns, and 90ns

Fast Read Access Time

•

- 70ns with C

- 45ns, 55ns with C

Sector Architecture:

•

One 16K byte Boot Sector, Two 8K byte

Parameter Sectors, one 32K byte and three 64K byte main Sectors

• Boot Block Top/Bottom Programming Architecture

• High performance program/erase speed

- Byte program time: 10µs typical

- Sector erase time: 500ms typical

- Chip erase time: 3.5s typical

Low Standby Current

•

- 1µA CMOS standby current-typical

- 1mA TTL standby current

• Low Power Active Current

- 30mA active read current

- 30mA program / erase current

• JEDEC Standard program and erase commands

= 100pF

load

= 30pF

• JEDEC standard bits feature

Hardware

•

• Single Sector and Chip Erase

• Sector Protection / Temporary Sector

Unprotect (

Sector Unprotect Mode

•

• Embedded Erase and Program Algorithms

• Erase Suspend / Resume modes:

Read and program another sector during Erase Suspend Mode

0.23 µm triple-metal double-poly

•

triple-well CMOS Flash Technology

• Low Vcc write inhibit < 3.2V

100K endurance cycle

•

Package Options

•

- 32-pin PDIP

- 32-pin PLCC

- 32-pin TSOP (Type 1)

Commercial and Industrial Temperature

•

Ranges

RESET

polling and toggle

DATA

(n/a on EN29F002AN)

= VID)

GENERAL DESCRIPTION

The EN29F002A / EN29F002AN is a 2-Megabit, electrically erasable, read/write non-volatile flash memory. Organized into 256K words with 8 bits per word, the 2M of memory is arranged in seven sectors (with top/bottom configuration), including one 16K Byte Boot Sector, two 8K Byte Parameter sectors, and four main sectors (one 32K Byte and three 64K Byte). Any byte can be programmed typically at 10µs. The EN29F002A / EN29F002AN features 5.0V voltage read and write operation. The access times are as fast as 45ns to eliminate the need for WAIT states in high-performance microprocessor systems.

The EN29F002A / EN29F002AN has separate Output Enable ( Enable ( either single sector or full chip erase operation, where each sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each sector.

) controls which eliminate bus contention issues. This device is designed to allow

), Chip Enable (CE), and Write

Rev. A, Issue Date: 2003/03/26

Page 2

EN29F002A / EN29F002AN

TABLE 1. PIN DESCRIPTION FIGURE 1. LOGIC DIAGRAM

Pin Name Function

A0-A17 Addresses

DQ0-DQ7 Data Input/Outputs

CE OE

RESET

(n/a for EN29F002AN)

Chip Enable

Output Enable

Write Enable

Hardware Reset Sector Unprotect

Vcc Supply Voltage

(5V ± 10% )

Vss Ground

TABLE 2. BLOCK ARCHITECTURE

RESET

N/A on EN29F002AN

Vcc

EN29F002AT/B

Vss

DQ0 - DQ7A0 - A17

TOP BOOT BLOCK BOTTOM BOOT BLOCK

SECTOR

ADDRESSES

6 3C000h - 3FFFFh 16 30000h - 3FFFFh 64

5 3A000h - 3BFFFh 8 20000h - 2FFFFh 64

4 38000h - 39FFFh 8 10000h - 1FFFFh 64

3 30000h - 37FFFh 32 08000h - 0FFFFh 32

2 20000h - 2FFFFh 64 06000h - 07FFFh 8

1 10000h - 1FFFFh 64 04000h - 05FFFh 8

0 00000h - 0FFFFh 64 00000h - 03FFFh 16

SIZE (Kbytes)

ADDRESSES

SIZE (Kbytes)

Rev. A, Issue Date: 2003/03/26

Page 3

BLOCK DIAGRAM

N/A on EN29F002AN

Vcc Vss

RESET

CE OE

Control

Command

State

EN29F002A / EN29F002AN

Block Protect

DQ0-DQ7

Erase Voltage Generator

Input/Output Buffers

Program Voltage

Generator

Chip Enable

STB

Output Enable

Logic

Data Latch

A0-A17

Y-Decoder

STB

TimerVcc Detector

X-Decoder

Y- G a t i n g

Cell Matrix

Address Latch

Rev. A, Issue Date: 2003/03/26

Page 4

FIGURE 2. PDIP

NC on EN29F002AN

FIGURE 3. TSOP

EN29F002A / EN29F002AN

PDIP Top View

VPP

RESET

A16 A15 A12

DQ0 DQ1 DQ2 VSS

A7 A6 A5 A4 A3 A2 A1 A0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

VCC PGM

A14 A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3

NC on EN29F002AN

FIGURE 4. PLCC

RESET

PLCC Top View

A12 A16 VCC A17

A12 A16 VCC

A15 RESET WE

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

4232

5 6 7 8 9 10 11 12 13

14 16 18

DQ2 DQ3 DQ5

DQ1 VSS DQ4

EN29F002A

A15 VPP PGM

3131

15 17 19

DQ6

29 28 27 26 25 24 23 22 21

NC on EN29F002AN at RESET pin

A14 A13 A8 A9 A11 OE A10 CE DQ7

Rev. A, Issue Date: 2003/03/26

Page 5

EN29F002A / EN29F002AN

TABLE 3. OPERATING MODES

2M FLASH USER MODE TABLE

USER MODE

RESET

(n/a on EN29F002AN)

STANDBY H X X H X X X X X X HI-Z READ L H L H A9 A8 A6 A1 A0 Ax/y DQ(0-7) OUTPUT DISABLE L H H H X X X X X X HI-Z READ MANUFACTURER ID READ DEVICE ID L H L H VID L/H L L H X DEVICE ID(T/B) VERIFY SECTOR PROTECT ENABLE SECTOR PROTECT SECTOR UNPROTECT L L VID H VID X H H L X X WRITE L L H H A9 A8 A6 A1 A0 Ax/y DIN(0-7) TEMPORARY SECTOR UNPROTECT

WE OE

X X X L X X X X X X HI-Z

L H L H VID L/H L L L X MANUFACTURER

L H L H VID X L H L X 01h(protected)

L L VID H VID X L X X X X

X X X VID X X X X X X X

RESET

A9 A8 A6 A1 A0 Ax/y DQ(0-7)

00h(unprotected)

NOTES:

1) L = V

2) X = Don’t care, either V

, H = VIH, VID = 11.0V ± 0.5V

or VIL

TABLE 4. DEVICE IDENTIFICTION

2M FLASH MANUFACTURER/DEVICE ID TABLE

A8 A6 A1 A0 DQ(7-0)

HEX

READ MANUFACTURER ID READ

MANUFACTURER ID READ DEVICE ID

(Top Architecture)

READ DEVICE ID* (Top Architecture) READ DEVICE ID (Bottom Architecture)

READ DEVICE ID* (Bottom Architecture)

NOTES:

These modes (A8=H) are recommended for Manufacture/Device ID check.

L L L L CONTINUATION MANUFACTURER ID

H L L L MANUFACTURER ID

L L L H CONTINUATION DEVICE ID

H L L H DEVICE ID

L L L H CONTINUATION DEVICE ID

H L L H DEVICE ID

Rev. A, Issue Date: 2003/03/26

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EN29F002A / EN29F002AN

USER MODE DEFINITIONS

Reset Mode

EN29F002A features a Reset mode that resets the program and erase operation immediately to read mode. If reset (

program or erase which was terminated should be repeated since data will be corrupted. This pin is not available for EN29F002AN.

Standby Mode

The EN29F002A / EN29F002AN has a CMOS-compatible standby mode which reduces the to < 1µA (typical). It is placed in CMOS-compatible standby when

± 0.5 V (CE pin only, for EN29F002AN). The device also has a TTL-compatible standby mode

which reduces the maximum V and

pins are at VIH. Another method of entering standby mode uses only the

RESET

(n/a for EN29F002AN). When standby with current typically reduced to < 1 µA. When compatible standby with current reduced to < 1mA. When in standby modes, the outputs are in a high-impedance state independent of the

Read Mode

The EN29F002A / EN29F002AN has two control functions which must be satisfied in order to obtain data at the outputs. Chip Enable ( Output Enable (

) is the output control and should be used to gate data to the output pins,

provided the device is selected. Read is selected when both the

pin held at VIH. Address access time (t

valid output data. Assuming that addresses are stable, chip enable access time (t delay from stable

enable access time (t addresses have been stable for at least t

Output Disable Mode

When the

or OE pin is at a logic high level (VIH), the output from the EN29F002A /

EN29F002AN is disabled. The output pins are placed in a high impedance state.

Auto Select Identification Mode

The manufacturer and device type can be identified by hardware or software operations. This mode allows applications or programming equipment automatically matching the device with its corresponding interface characteristics.

To activate the Auto Select Identification mode, the programming equipment must force 11.0 V ±

0.5V on address line A9 of the EN29F002AT/B. Two identifier bytes can then be sequenced from the device outputs by toggling address lines A0 and A8 from V

The manufacturer and device identification may also be read via the command register. By following the command sequence referenced in the Command Definition Table (Table 5). This method is desirable for in-system identification (using only + 5.0V).

When A0 = A1 = A6 = V = 7F, 1C (hex) to identify EON . When A0 = V

= L) is executed when program or erase operation were in progress, the

RESET

current

and the

current to < 1mA. It is placed in TTL-compatible standby when CE

pin is at VSS ± 0.3V, the device enters CMOS-compatible

RESET

input.

) is the power control and should be used for device selection.

) is equal to the delay from stable addresses to

ACC

pin is at VIL, the device enters TTL-

and OE pins are held at VIL with

pins are at

RESE

RESET

) is equal to the

to valid data at output pins. Data is available at the outputs after output

) from the falling edge of OE, assuming the CE has been LOW and

and by toggling A8 from VIL to V

ACC

- tOE.

to VIH.

the Manufacturer ID can be read as Eon

IH,

, A1 = A6 = V

and by toggling A8 from V

IL,

to VIH,

Rev. A, Issue Date: 2003/03/26

Page 7

EN29F002A / EN29F002AN

, is

the Device Code can be read as 7F, 92 (hex) for EN29F002AT or as 7F, 97 (hex) for EN29F002AB (See Table 4). All identifiers for manufacturer and device codes possess odd parity with the DQ7 defined as the parity bit.

Write Mode

Write is used for device programming and erase through the command register. This mode is selected with

the internal state machine. The command register is a set of latches used to store the commands along with the addresses and data information needed to execute that command. Address latching

occurs on the falling edge of rising edge of

= WE = L and OE = H. The contents of the command register are the inputs to

or CE (whichever occurs later) and data latching occurs on the

or CE (whichever occurs first).

Temporary Sector Unprotect Mode

EN29F002A allows protected sectors to be temporarily unprotected for making changes to data stored in a protected sector in system (n/a for EN29F002AN). To activate the temporary sector

unprotect, the can be programmed or erased by selecting the sector addresses. Once the high voltage, V

removed from

RESET

pin must be set to a high voltage of VID (11V). In this mode, protected sectors

pin, all previously protected sectors will revert to their protected state.

RESET Hardware Reset Mode

Resetting the EN29F002A device is performed when the least 500ns. The internal state machine will be reset to the read mode. Any program/erase operation in progress during hardware reset will be terminated and data may be corrupted.

If the

RESET

read mode and enable the system’s microprocessor to read the boot-up firmware from the FLASH memory.

pin is tied to the system reset command, the device will be automatically reset to the

(not available on EN29F002AN)

RESET

pin is set to VIL and kept low for at

COMMAND DEFINITIONS

The operations of the EN29F002A are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Table (Table 5). Incorrect addresses, incorrect data values or improper sequences will reset the device to the read mode.

Rev. A, Issue Date: 2003/03/26

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EN29F002A / EN29F002AN

Table 5. EN29F002A Command Definitions

Command Sequence

Read/Reset

AutoSelect Manufacturer ID

AutoSelect Device ID

(Top Boot)

AutoSelect Device ID

(Bottom Boot)

AutoSelect Sector Protect Verify

Byte Program

Chip Erase

Sector Erase

Sector Erase Suspend

Sector Erase Resume

Write

Cycles

Req’d

1 XXXh F0h RA RD 4 555h AAh AAAh 55h 555h F0h RA RD 4 555h AAh AAAh 55h 555h 90h 000h/

4 555h AAh AAAh 55h 555h 90h 001h/

4 555h AAh AAAh 55h 555h 90h SA &

4 555h AAh AAAh 55h 555h A0h PA PD 6 555h AAh AAAh 55h 555h 80h 555h AAh AAAh 55h 555h 10h 6 555h AAh AAAh 55h 555h 80h 555h AAh AAAh 55h SA 30h 1 xxxh B0h 1 xxxh 30h

Write Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Write Cycle

7Fh/

100h

1Ch 7Fh/

101h

92h

7Fh/

101h

97h

00h/

02h

01h

Notes:

RA = Read Address: address of the memory location to be read. This one is a read cycle. RD = Read Data: data read from location RA during Read operation. This one is a read cycle. PA = Program Address: address of the memory location to be programmed PD = Program Data: data to be programmed at location PA SA = Sector Address: address of the sector to be erased. Address bits A17-A13 uniquely select any sector. The data is 00h for an unprotected sector and 01h for a protected sector.

Byte Programming Command

Programming the EN29F002A is performed on a byte-by-byte basis using a four bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. The program operation is terminated automatically by an internal timer. Address is latched on the falling

edge of is first. The program operation is completed when EN29F002A returns the equivalent data to the programmed location.

Programming status may be checked by sampling data on DQ7 ( bit). Changing data from 0 to 1 requires an erase operation. When programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode.

EN29F002A ignores commands written during Byte Programming. If a hardware during Byte Programming, data at the programmed location may get corrupted. Programming is allowed in any sequence and across any sector boundary.

Chip Erase Command

An auto Chip Erase algorithm is employed when the Chip Erase command sequence is performed. Although the Chip Erase command requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles and the chip erase command, the user does not need

, whichever is last; data is latched on the rising edge of CE or WE, whichever

polling) or on DQ6 (toggle

DAT

RESET

6th

Write Cycle

occurs

Rev. A, Issue Date: 2003/03/26

Page 9

EN29F002A / EN29F002AN

to do anything else after that, except check to see if the operation has completed. The Auto Chip Erase algorithm automatically programs and verifies the entire memory array for an all “0” pattern prior to the erase. Then the EN29F002A will automatically time the erase pulse width, verify the

erase, return the sequence count, provide a erase status through

POLLING (data on DQ7 is

DATA

“0” during the operation and “1” when completed, provided the status is not read from a protected sector), and returns to the READ mode after completion of Chip Erase.

Sector Erase Command

Sector Erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles, and the Sector Erase command. Any sector may be erased by latching any

address within the desired sector on the falling edge of latched on the rising edge of

. This device does not support multiple sector erase commands.

Sector Erase operation will commence immediately after the first 30h command is written. The first sector erase operation must finish before another sector erase command can be given.

The EN29F002A device automatically programs and verifies all memory locations in the selected sector for an all “0” pattern prior to the erase. Unselected sectors are unaffected by the Sector Erase command. The EN29F002A requires no timing signals during sector erase. Erase is completed when data on DQ7 becomes “1”, and the device returns to the READ mode after completion of Sector Erase.

Erase Suspend / Resume Command

Erase suspend allows interruption of sector erase operations to perform data reads from sector not being erased. Erase suspend applies only to Sector Erase operations.

EN29F002A ignores any commands during erase suspend other than the assertion of the pin (n/a for EN29F002AN) or Erase Resume commands. Writing erase resume continues erase operations. Addresses are DON’T CARE when writing Erase Suspend or Erase Resume commands.

EN29F002A takes 0.1 - 15 µs to suspend erase operations after receiving Erase Suspend command. Check completion of erase suspend by polling DQ7 and/or DQ6. EN29F002A ignores redundant writes of erase suspend command.

EN29F0002 defaults to erase-suspend-read mode while an erase operation has been suspended. While in erase-suspend-read mode, EN29F002A allows reading data in any sector not undergoing sector erase, which is treated as standard read mode.

Write the Resume command 30h to continue operation of Sector erase. EN29F002A ignores redundant writes of the Resume command. EN29F002A permits multiple suspend/resume operations during sector erase.

Sector Protect and Unprotect

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operation in previously protected sectors.

Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (V Inc. for an additional supplement on this feature.

) on address pin A9 and the control pins. Contact Eon Silicon Solution,

while the Erase Command (30H) is

RESET

Rev. A, Issue Date: 2003/03/26

Page 10

EN29F002A / EN29F002AN

WRITE OPERATION STATUS

DQ7

DAT

The EN29F002A provides embedded operations. The

Erase, Chip Erase, Erase Suspend. (See Table 6)

When the Byte Programming is in progress, an attempt to read the device will produce the complement of the data last written to DQ7. Upon the completion of the Byte Programming, an attempt to read the device will produce the true data last written to DQ7. For the Byte Programming,

DATA

When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7

output during the read. For Chip Erase, the

rising edge of the sector erase

DATA

erased and not a protected sector. Otherwise, address used is in a protected sector.

Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable (

one instant of time and valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will be read on the subsequent read attempts.

The flowchart for diagram is shown in Figure 8.

DQ6 Toggle Bit I

The EN29F002A provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the embedded programming and erase operations. (See Table 6)

During an embedded Program or Erase operation, successive attempts to read data from the device at any address (by toggling

the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the

rising edge of the fourth valid after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after the last rising edge of the Sector Erase Command (30h)

2µs, then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all selected sectors are protected, DQ6 will toggle for about 100 µs. The chip will then return to the read mode without changing data in all protected sectors.

Toggling either

Polling

Polling on DQ7 to indicate to the host system the status of the

DATA

Polling feature is active during the Byte Programming, Sector

DATA

polling is valid after the rising edge of the fourth WE or CEpulse in the four-cycle sequence.

polling is valid after the rising edge of the sixth

DATA

or CE pulse in the six-cycle sequence. For Sector Erase,

Polling must be performed at any address within a sector that is being programmed or

) is low. This means that the device is driving status information on DQ7 at

Polling (DQ7) is shown on Flowchart 5. The

DATA

or CE) will result in DQ6 toggling between “zero” and “one”. Once

pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is

In Byte Programming, if the sector being written to is protected, DQ6 will toggle for about

or OE will cause DQ6 to toggle.

pulse.

DATA

polling may give an inaccurate result if the

pulse.

polling is valid after the last

DATA

Polling (DQ7) timing

DATA

Rev. A, Issue Date: 2003/03/26

Page 11

EN29F002A / EN29F002AN

The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown in Figure 9

DQ5 Exceeded Timing Limits

DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a “1”. (The Toggle Bit (DQ6) should also be checked at this time to make sure that the DQ5 is not a “1” due to the device having returned to read mode.) This is a failure condition which indicates that the program or erase cycle was not

successfully completed. function under this condition. Setting the

conditions. The

The DQ5 failure condition will also appear if the user tries to program a “1” to a location that was previously programmed to a “0”. In this case, the device goes into Hang or Error mode out and never completes the Embedded Program Algorithm. Hence, the system never reads valid data on DQ7 and DQ6 never stops toggling. Once the device exceeds the timing limits, DQ5 will indicate a “1”. Please note that this is not a device failure condition since the device was used incorrectly. If timing limits are exceeded, reset the device. (See Table 6)

and

Polling (DQ7), Toggle Bit (DQ6) and Erase Toggle Bit (DQ2) still

DATA

to VIH will partially power down the device under those

pins will control the output disable functions as described in Table 3.

DQ3 Sector Erase Command Timeout

This device does not support multiple sector erase commands. DQ3 will go high immediately after the first 30h command (the sixth write cycle). Any extra 30h commands will be ignored (or taken as a resume command if erase suspended).

DQ2 Erase Toggle Bit II

In the sector erase operation, DQ2 will toggle with sector that is being erased. DQ2 will not toggle if the read address is not within the sector that is

selected to be erased. In the chip erase operation, however, DQ2 will toggle with regardless of the address given by the user. This is because all sectors are to be erased. (See Table 6)

or CE when a read is attempted within the

or CE

Rev. A, Issue Date: 2003/03/26

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EN29F002A / EN29F002AN

Table 6. Status Register Bits

DQ Name Logic Level Definition

‘1’ Erase Complete or

erase sector in Erase suspend

‘0’ Erase On-Going

‘-1-0-1-0-1-0-1-’ Erase or Program On-going DQ6 Read during Erase Suspend

5 ERROR BIT ‘1’ Program or Erase Error

‘0’ Program or Erase On-going

‘0’ Erase timeout period on-going

2 TOGGLE

Notes:

DQ7 for Program or Erase Success.

DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive reads output complementary data on DQ6 while programming or Erase operation are on-going.

DQ5 Error Bit: set to “1’ if failure in programming or erase

Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5

DATA

POLLING

TOGGLE

TIME BIT

DATA

BIT

ERASE

BIT

‘-1-1-1-1-1-1-1-‘

‘-1-0-1-0-1-0-1-’

DQ7

‘1’ Erase operation start

DQ2

DQ3 Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).

DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased sector.

Program Complete or

data of non-erase sector

during Erase Suspend

Program On-Going

Erase Complete

Chip Erase, Erase or Erase

suspend on currently

addressed

sector. (When DQ5=1, Erase

Error due to currently

addressed sector. Program

during Erase Suspend on-

going at current address

Erase Suspend read on

non Erase Suspend Sector

Rev. A, Issue Date: 2003/03/26

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EN29F002A / EN29F002AN

DATA PROTECTION

< V

, the command register is disabled and all internal program or

LKO

OE, CE

> V

or WE will neither initiate a write cycle nor change the

LKO.

Power-up Write Inhibit

During power-up, the device automatically resets to READ mode and locks out write cycles. Even with

= VIL, WE = VIL and OE = VIH, the device will not accept commands on the rising edge of

Low VCC Write Inhibit

During V

power-up or power-down, the EN29F002A locks out write cycles to protect against any

unintentional writes. If V erase circuits are disabled. Under this condition, the device will reset to the READ mode. Subsequent writes will be ignored until V

Write “Noise” Pulse Protection

Noise pulses less than 5ns on command register.

Logical Inhibit

=VIH or WE=VIH, writing is inhibited. To initiate a write cycle, CE and

“zero”. If

, and OE are all logical zero (not recommended usage), it will be considered a

must be a logical

write.

Sector Protection/Unprotection

When the device is shipped, all sectors are unprotected. Each sector can be separately protected against data changes. Using hardware protection circuitry enabled at user’s site with external programming equipment, both program and erase operations may be disabled for any specified sector or combination of sectors.

Verification of write protection for a specific sector can be achieved with an Auto Select ID read command at location 02h where the address bits A17 - A13 select the defined sector (see Table 5). A logical “1” at DQ0 means a protected sector and a logical “0” means an unprotected sector.

The Sector Unprotect disables sector protection in all sectors in one operation to implement code changes. All sectors must be placed in protection mode using the protection algorithm mentioned above before unprotection can be executed.

Additional details on this feature are provided in a supplement, which can be obtained by contacting a representative of Eon Silicon Solution, Inc.

Rev. A, Issue Date: 2003/03/26

Page 14

EMBEDDED ALGORITHMS

Flowchart 1. Embedded Program

START

Write Program

Command Sequence

(shown below)

Data Poll Device

EN29F002A / EN29F002AN

Increment

Address

Last

Address?

Yes

Programming Done

Flowchart 2. Embedded Program Command Sequence

See the Command Definitions section for more information.

5555H / AAH

2AAAH / 55H

5555H / A0H

PROGRAM ADDRESS / PROGRAM DATA

Rev. A, Issue Date: 2003/03/26

Page 15

Flowchart 3. Embedded Erase

START

Write Erase

Command Sequence

(shown below)

Data Polling Device or Toggle Bit

Successfully Completed

ERASE Done

EN29F002A / EN29F002AN

Rev. A, Issue Date: 2003/03/26

Page 16

EN29F002A / EN29F002AN

Flowchart 4. Embedded Erase Command Sequence

See the Command Definitions section for more information.

Chip Erase Sector Erase

5555H/AAH

2AAAH/55H

5555H/80H

5555H/AAH

2AAAH/55H

5555H/10H

2AAAH/55H

5555H/80H

5555H/AAH

2AAAH/55H

Sector Address/30H

Rev. A, Issue Date: 2003/03/26

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Flowchart 5.

DAT

Read Data

Polling Algorithm

Start

EN29F002A / EN29F002AN

Yes

DQ7 = Data?

DQ5 = 1?

Yes

Read Data

DQ7 = Data?

Fail Pass

Rev. A, Issue Date: 2003/03/26

Page 18

Flowchart 6. Toggle Bit Algorithm

Start

Read Data

EN29F002A / EN29F002AN

DQ6 = Toggle?

Yes

DQ5 = 1?

Yes

Read Data

DQ6 = Toggle?

Yes

Fail Pass

Rev. A, Issue Date: 2003/03/26

Page 19

EN29F002A / EN29F002AN

Flowchart 7. Temporary Sector Unprotect Algorithm

(Not available for EN29F002AN)

Start

RESET = V

(Note 1)

Perform Erase or Program Operations

RESET = V

Temporary Block Unprotect Done

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previous protected sectors are protected once again.

Rev. A, Issue Date: 2003/03/26

Page 20

EN29F002A / EN29F002AN

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to 7.0 V

A9, OE# (Note 2) . . . . . . . . . . . . . . . –0.5 V to 11.5 V

All other pins (Note 1) . . . . . . . . . . . . –0.5 V to Vcc+0.5V

Output Short Circuit Current (Note 3) . . . . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot to –1.0V for periods of up to 50 ns and to –2.0 V for periods of up to 20 ns. See Left Figure below.

Maximum DC voltage on input and I/O pins is V pins may overshoot to V

2. Minimum DC input voltage on A9 pin is –0.5 V. During voltage transitions, A9 and OE# may

undershoot V Figure. Maximum DC input voltage on A9 and OE# is 11.5 V which may overshoot to 12.5 V for periods up to 20 ns.

3. No more than one output shorted to ground at a time. Duration of the short circuit should not be greater

than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

to –1.0V for periods of up to 50 ns and to –2.0 V for periods of up to 20 ns. See Left

+ 2.0 V for periods up to 20 ns. See Right Figure below.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T A ) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T A ). . . . . . . . . . -40°C to +85°C

Supply Voltages

for ± 5% devices . . . . . . . . . . . . +4.75 V to +5.25 V

for ± 10% devices . . . . . . . . . . . +4.50 V to +5.50 V

Operating ranges define those limits between which the functionality of the device is guaranteed.

+ 0.5 V. During voltage transitions, input and I/O

Waveform Waveform

Maximum Negative Overshoot Maximum Positive Overshoot

Rev. A, Issue Date: 2003/03/26

Page 21

EN29F002A / EN29F002AN

Table 7.

(Ta = 0°C to 70°C or - 40°C to 85°C; VCC = 5.0V ± 10%)

Symbol Parameter Test Conditions Min Max Unit

ILI

ILO

CC1

CC2

Supply Current (Standby) CMOS

CC3

CC4

VIL

VIH

VOL

VOH

Output High Voltage CMOS

VID

LIT

LKO

Notes:

(1) RESET# pin input buffer is always enabled so that it draws power if not at full CMOS supply voltages

DC Characteristics

Input Leakage Current

Output Leakage Current

Supply Current (read) TTL Byte

Supply Current (Standby) TTL

(1)

Supply Current (Program or Erase)

Input Low Voltage -0.5 0.8 V

Input High Voltage 2 Vcc ± 0.5 V

Output Low Voltage

Output High Voltage TTL

A9 Voltage (Electronic Signature) and RESET# Voltage (Temporary Sector Unprotect) A9 and RESET# Current (Electronic Signature) Supply voltage (Erase and Program lock-out)

0V≤ VIN ≤ Vcc

0V≤ V

CE# = VIL; OE# = VIH;

RESET# = CE# = Vcc ± 0.2V 5.0 µA

CE# = VIL; OE# = VIH;

Byte program, Sector or Chip

Erase in progress

IOH = -2.5 mA

A9, RESET# = V

≤ Vcc

OUT

f = 6MHz

CE# = VIH

IOL = 2 mA

= -100 µA

10.5 11.5 V

100 µA

±5 µA

30 mA

1.0 mA

0.45 V

2.4 V

Vcc - 0.4V V

3.2 4.2 V

Rev. A, Issue Date: 2003/03/26

Page 22

Table 8. AC CHARACTERISTICS Read-only Operations Characteristics

Parameter

Symbols

JEDEC Standard

AVAV

Description

Read Cycle Time

EN29F002A / EN29F002AN

Speed Options

Test Setup

Min 45 55 70 90 ns

-45 -55 -70 -90 Unit

AVQV

ELQV

GLQV

EHQZ

GHQZ

AXQX

ACC

Ready

Address to Output Delay

Chip Enable To Output Delay

Output Enable to Output Delay

Chip Enable to Output High Z

Output Enable to Output High Z

Output Hold Time from

Addresses, whichever occurs first

RESET

Mode

(n/a for EN29F002AN)

or OE,

Pin Low to Read

= V

CE OE

= VIL

Max 25 30 30 35 ns

Max 10 15 20 20 ns

Min 0 0 0 0 ns

Max 45 55 70 90 ns

Max

Notes:

For -45,-55 Vcc = 5.0V ± 5% Output Load : 1 TTL gate and 30pF Input Rise and Fall Times: 5ns Input Rise Levels: 0.0 V to 3.0 V Timing Measurement Reference Level, Input and Output: 1.5 V

For all others: Vcc = 5.0V ± 10%

Input Rise and Fall Times: 20 ns Input Pulse Levels: 0.45 V to 2.4 V Timing Measurement Reference Level, Input and Output: 0.8 V and 2.0 V

Output Load: 1 TTL gate and 100 pF

20 20 20 20 µs

Rev. A, Issue Date: 2003/03/26

Page 23

Table 9. AC CHARACTERISTICS Write (Erase/Program) Operations

Parameter

Symbols

JEDEC Standard

AVAV

Description

Write Cycle Time

EN29F002A / EN29F002AN

Speed Options

Min 45 55 70 90 ns

-45 -55 -70 -90 Unit

AVWL

WLAX

DVWH

WHDX

Hold Time Toggle and

GHWL

ELWL

WHEH

WLWH

WHDL

WHWH1

OES

OEH

GHWL

WPH

WHWH1

WHWH2

WHWH3

VCS

VIDR

RSP

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Output Enable Setup Time

Output Enable Read

Read Recovery Time before

Write (

Write Pulse Width

Write Pulse Width High

Programming Operation

Sector Erase Operation

Chip Erase Operation

Vcc Setup Time

Rise Time to V

RESET

(n/a for EN29F002AN)

RESET

(n/a for EN29F002AN)

High to WE Low)

SetupTime

Hold Time

Pulse Width

Setup Time

DATA

Polling

Min 0 0 0 0 ns

Min 35 45 45 45 ns

Min 20 25 30 45 ns

Min 0 0 0 0 ns

MIn 0 0 0 0 ns

Min 10 10 10 10 ns

Min

Typ

Max

Typ

Max

Typ

Max

Min

0 0 0 0 ns

25 30 35 45 ns

20 20 20 20 ns

7 7 7 7 µs

200 200 200 200 µs

0.3 0.3 0.3 0.3 s

5 5 5 5 s

3 3 3 3 s

35 35 35 35 s

50 50 50 50 µs

500 500 500 500 ns

4 4 4 4 µs

Rev. A, Issue Date: 2003/03/26

Page 24

Table 10. AC CHARACTERISTICS Write (Erase/Program) Operations

Alternate CE Controlled Writes

Parameter

Symbols

JEDEC Standard

AVAV

Description

Write Cycle Time

EN29F002A / EN29F002AN

Speed Options

Min 45 55 70 90 ns

-45 -55 -70 -90 Unit

AVEL

ELAX

DVEH

EHDX

Hold Time Toggle and

GHEL

WLEL

EHWH

ELEH

EHEL

WHWH1

OES

OEH

GHEL

CPH

WHWH1

WHWH2

WHWH3

VCS

VIDR

RSP

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Output Enable Setup Time

Output Enable Read

Read Recovery Time before Write (

Write Pulse Width

Write Pulse Width High

Programming Operation

Sector Erase Operation

Chip Erase Operation

Vcc Setup Time

Rise Time to V

RESET

(n/a for EN29F002AN)

RESET

(n/a for EN29F002AN)

High to CE Low)

SetupTime

Hold Time

Pulse Width

Setup Time

Data Polling

Min 0 0 0 0 ns

Min 35 45 45 45 ns

Min 20 25 30 45 ns

Min 0 0 0 0 ns

0 0 0 0 0 ns

10 10 10 10 10 ns

Min

Typ

Max

Typ

Max

Typ

Max

Min

0 0 0 0 ns

25 30 35 45 ns

20 20 20 20 ns

7 7 7 7 µs

200 200 200 200 µs

0.3 0.3 0.3 0.3 s

5 5 5 5 s

3 3 3 3 s

35 35 35 35 s

50 50 50 50 µs

500 500 500 500 ns

4 4 4 4 µs

Rev. A, Issue Date: 2003/03/26

Page 25

EN29F002A / EN29F002AN

Table 11. ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter Typ Max Unit Comments

Sector Erase Time 0.3 5 sec Excludes 00H programming prior to

Chip Erase Time 3 35 sec

Byte Programming Time 7 200 µs Excludes system level overhead

Chip Programming Time 2 5 sec

Erase/Program Endurance 100K cycles

Minimum 100K cycles guaranteed

Table 12. LATCH UP CHARACTERISTICS

Parameter Description Min Max

Input voltage with respect to Vss on A9 and OE, and

RESET

-1.0 V 12.0 V

erasure

Input voltage with respect to Vss on all other pins -1.0 V Vcc + 1.0 V

Vcc Current -100 mA 100 mA

Note :

These are latch up characteristics and the device should never be put under

these conditions. Refer to Absolute Maximum ratings for the actual operating limits.

Table 13. 32-PIN PLCC PIN CAPACITANCE @ 25°C, 1.0MHz

Parameter Symbol Parameter Description Test Setup Typ Max Unit

CIN

OUT

IN2

Input Capacitance

Output Capacitance

Control Pin Capacitance

VIN = 0

OUT

VIN = 0

= 0

4 6 pF

8 12 pF

Table 14. 32-PIN TSOP PIN CAPACITANCE @ 25°C, 1.0MHz

Parameter Symbol Parameter Description Test Setup Typ Max Unit

CIN

Input Capacitance

VIN = 0

6 7.5 pF

OUT

IN2

Output Capacitance

Control Pin Capacitance

OUT

VIN = 0

= 0

8.5 12 pF

7.5 9 pF

Rev. A, Issue Date: 2003/03/26

Page 26

EN29F002A / EN29F002AN

Table 15. DATA RETENTION

Parameter Description Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C 10 Years

125°C 20 Years

Rev. A, Issue Date: 2003/03/26

Page 27

EN29F002A / EN29F002AN

SWITCHING WAVEFORMS

Figure 5. AC Waveforms for READ Operations

Figure 6. AC Waveforms for Chip/Sector Erase Operations

Notes:

SA is the sector address for sector erase.

Rev. A, Issue Date: 2003/03/26

Page 28

SWITCHING WAVEFORMS (continued)

Figure 7. Program Operation Timings

EN29F002A / EN29F002AN

Notes:

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. /DQ7 is the output of the complement of the data written to the device.

4. D

5. Figure indicates last two bus cycles of four bus cycle sequence.

is the output of data written to the device.

OUT

Figure 8. AC Waveforms for /DATA Polling During Embedded Algorithm Operations

Notes:

DQ7 = Valid Data (The device has completed the embedded operation).

Rev. A, Issue Date: 2003/03/26

Page 29

EN29F002A / EN29F002AN

Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm Operations

Notes:

stops toggling (The device has completed the embedded operation).

Figure 10. Temporary Sector Unprotect Timing Diagram

11V

Rev. A, Issue Date: 2003/03/26

Page 30

EN29F002A / EN29F002AN

SWITCHING WAVEFORMS (continued)

Figure 11. /RESET Timing Diagram

Figure 12. Alternate /CE Controlled Write Operation Timings

Notes:

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. /DQ7 is the output of the complement of the data written to the device.

4. D

5. Figure indicates last two bus cycles of four bus cycle sequence.

is the output of data written to the device.

OUT

Rev. A, Issue Date: 2003/03/26

Page 31

EN29F002A / EN29F002AN

ORDERING INFORMATION

EN29F002A T - 45 P C P

PACKAGING CONTENT

Blank= Conventional

P=Pb free

TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (-40°C to +85°C)

PACKAGE P = 32 Plastic DIP J = 32 Plastic PLCC T = 32 Plastic TSOP

SPEED 45 = 45ns 55 = 55ns 70 = 70ns 90 = 90ns

BOOT BLOCK ARCHITECTURE T = Top Block

B = Bottom Block

BASE PART NUMBER EN = EON Silicon Solution 29F = FLASH, 5V 002 = 256K x 8 A = Version A

(Blank) = with

N = without

RESET

function

Rev. A, Issue Date: 2003/03/26

Page 32

PHYSICAL DIMENSIONS PL 032

— 32-Pin Plastic Leaded Chip Carrier

EN29F002A / EN29F002AN

Rev. A, Issue Date: 2003/03/26

Page 33

PHYSICAL DIMENSIONS (continued) PD 032

— 32-Pin Plastic DIP

EN29F002A / EN29F002AN

Rev. A, Issue Date: 2003/03/26

Page 34

PHYSICAL DIMENSIONS (continued) TS 032

— 32-Pin Standard Thin Small

EN29F002A / EN29F002AN

Rev. A, Issue Date: 2003/03/26

Page 35

EN29F002A / EN29F002AN

Revisions List

Revision No Description Date

A Initial draft 3/26/2003

Rev. A, Issue Date: 2003/03/26