The EN27C512 is a low-power 512Kbit, 5V-only one-time-programmable (OTP) read-only
memory (EPROM). Organized into 64K words with 8 bits per word, it features QuikRite
address location programm ing, typically at 20µs per byte. Any byte can be accessed in less than
45ns, eliminating the need for W AIT states in high-performance microprocessor systems. The
EN27C512 has separate Output Enable (
bus contention issues.
OE ) and Chip Enable ( CE ) controls which eliminate
TM
single-
FIGURE 1. PDIP
Pin NameFunction
A0-A15Addresses
DQ0-DQ7Outputs
CEChip Enable
OEOutput Enable
NCNo Connect
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EN27C512
FIGURE 2. TSOP
FIGURE 3. PLCC
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EN27C512
FIGURE 4. BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
THE QUIKRITETM PROGRAMMING OF THE EN27C512
When the EN27C512 is delivered, the chip has all 512K bits in the “ONE”, or
HIGH state. “ZEROs” are loaded into the EN27C512 through the procedure of programming.
The programming mode is entered when 12.75 ± 0.25V is applied to the
CEis at V
. For programming, the data to be programmed is applied with 8 bits in parallel to
IL
the data pins.
The QUIKRITE
TM
programming flowchart in Figure 5 shows Eon’s interactive programming
algorithm. The interactive algorithm reduces programming time by using 20 µs to 100 µs
programming pulses and giving each address only as many pulses as is necessary in order to
reliably program the data. After each pulse is applied to a given address, the data in that
address is verified. If the data is not verified, additional pulses are given until it is verified or
until the maximum number of pulses is reached. This process is repeated while sequencing
through each address of the EN27C512. This part of the programming algorithm is done at
= 6.25V to assure that each EPROM bit is programmed to a sufficiently high threshold
V
CC
voltage. This ensures that all bits have sufficient margin. After the final address is completed,
the entire EPROM memory is read at V
= 5.25 ± 0.25V to verify the entire memory.
CC
OE/V
PP
pin and
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EN27C512
PROGRAM INHIBIT MODE
Programming of multiple EN27C512 in parallel with different data is also easily accomplished
by using the Program Inhibit Mode. Except for
may be common. A TTL low-level program pulse applied to an EN27C512
OE/V
= 12.75 ± 0.25V will program that EN27C512. A high-level CEinput inhibits the
PP
other EN27C512 from being programmed.
PROGRAM VERIFY MODE
Verification should be performed on the programmed bits to determining that they were
correctly programmed. The verification should be performed with
should be verified at
t
after the falling edge of CE.
DV
CE, all like inputs of the parallel EN27C512
CEinput with
OE/V
and CEat VIL. Data
PP
AUTO PRODUCT IDENTIFICATION
The Auto Product Identification mode allows the reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode is intended for use by programming equipment
for the purpose of automatically matching the device to be programmed with its corresponding
programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range
that is required when programming the EN27C512.
To activate this mode, the programming equipment must force 12.0 V ± 0.5V on address line A9
of the EN27C512. Two identifier bytes may then be sequenced from the device outputs by
toggling address line A0 from V
V
during Auto Product Identification mode.
IL
Byte 0 (A0 = V
) represents the manufacturer code, and byte 1 (A0 = VIH), the device code. For
IL
the EN27C512, these two identifiers bytes are given in the Mode Select Table. All identifiers for
manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity
When A1 = VIL, the EN27C512 will read out the binary code of 7F, continuation code, to
bit.
signify the unavailability of manufacturer ID codes.
to VIH, when A1 = VIH. All other address lines must be held at
IL
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EN27C512
READ MODE
The EN27C512 has two control functions, both of which must be logically satisfied in order to
obtain data at the outputs. Chip Enable (
device selection. Output Enable (
the output pins, independent of device selection. Assuming that addresses are stable,
address access time (t
the outputs (t
) after the falling edge of OE, assuming the CEhas been LOW and
OE
) is equal to the delay from CE to output (tCE) . Data is available at
ACC
addresses have been stable for at least t
STANDBY MODE
CE) is the power control and should be used for
OE) is the output control and should be used to gate data to
- tOE.
ACC
The EN27C512 has CMOS standby mode which reduces the maximum V
It is placed in CMOS standby when
standby mode which reduces the maximum V
standby when
state, independent of the
CEis at V
. When in standby mode, the outputs are in a high-impedance
IH
OEinput.
CEis at V
± 0.3 V. The EN27C512 also has a TTL-
CC
current to 1.0 mA. It is placed in TTL-
CC
current to 20µA.
CC
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-line control function is provided to allow
for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not occur.
It is recommended that
CEbe decoded and used as the primary device-selection function, while
OEbe made a common connection to all devices in the array and connected to the READ line
from the system control bus. This assures that all deselected memory devices are in their lowpower standby mode and that the output pins are only active when data is desired from a
particular memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions, transient current peaks are produced
on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks
is dependent on the output capacitance loading of the device. At a minimum, a 0.1µF ceramic
capacitor (high frequency, low inherent inductance) should be used on each device between V
CC
and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the
inductive effects of the printed circuit board traces on EPROM arrays, a 4.7µF bulk electrolytic
capacitor should be used between V
and VSS for each eight devices. The location of the
CC
capacitor should be close to where the power supply is connected to the array.
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MODE SELECT TAB
/
EN27C512
ModeCE
Read
Output Disable
Standby (TTL)
Standby (CMOS)
Program
(4)
Program Verify
Program Inhibit
Manufacturer Code
Device Code
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EN27C512
FIGURE 5. QUIKRITETM PROGRAMMING FLOW CHART
NOTE 1: Either 100µs or 20µs pulse.
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ABSOLUTE MAXIMUM RATINGS
EN27C512
Storage Temperature
-65àC to +125àC
Ambient Temperature
with Power Applied-40àC to +85àC
Voltage with Respect to V
All pins except A9, VPP, V
A9, V
PP
V
CC
SS
CC
-0.6V to VCC + 0.5V
-0.6V to +13.5V
-0.6V to +7.0V
OPERATING RANGES
Commercial (C)
Case Temperature(Tc)0àC to +70àC
Industrial (I)
Case Temperature(Tc)-40àC to +85àC
Supply READ Voltages
+4.50V to +5.5V
(Functionality is guaranteed between these limits)
Stresses above those shown above may cause permanent damage to the device. This is a stress rating only and
operation above these specifications for extended periods may affect device reliability. Operation outside the
"OPERATING RANGES" shown above voids any and all warranty provisions.
DC CHARACTERISTICS FOR READ OPERATION
SymbolParameterMin.Max.UnitConditions
V
V
V
V
I
I
I
I
I
I
OH
OL
IH
IL
LI
LO
CC3
CC2
CC1
PP
Output High Voltage2.4VIOH = -0.4mA
Output Low Voltage0.45VIOL = 2.1mA
Input High Voltage2.0