EMLSI EM610FV16 Service Manual

merging Memory & Logic Solutions Inc.merging Memory & Logic Solutions Inc.

Document Title

64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM

Revision History

Revision No. History Draft Date Remark

0.0 Initial Draft May 9 , 2003

0.1 2’nd Draft Add Pb-free part number February 13 , 2004

EM610FV16 Series

Low Power, 64Kx16 SRAM

Emerging Memory & Logic Solutions Inc.

IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160
Tel : [phone]~1766 Fax : [phone] / Homepage : www.emlsi.com

The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.

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merging Memory & Logic Solutions Inc.merging Memory & Logic Solutions Inc.

EM610FV16 Series

Low Power, 64Kx16 SRAM

FEATURES

• Process Technology : 0.18µm Full CMOS

• Organization : 64K x 16 bit

• Power Supply Voltage : 2.7V ~ 3.6V

• Low Data Retention Voltage : 1.5V(Min.)

• Three state output and TTL Compatible

• Package Type : 48-FPBGA 6.0x7.0

PRODUCT FAMILY

Product
Family

EM610FV16

1. The parameter is measured with 30pF test load.

2. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested.

Operating
Temperature

Industrial (-40 ~ 85oC)

Vcc Range Speed

2.7V~3.6V

PIN DESCRIPTION

GENERAL DESCRIPTION

The EM610FV16 families are fabricated by EMLSI’s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The fami­lies also supports low data retention voltage for battery
back-up operation with low data retention current.

Power Dissipation

PKG Type

1)

55

/70ns 0.5µA

Standby
(I

, Typ.)

SB1

Operating
(I

.Max.)

CC1

2)

3 mA 48-FPBGA

FUNCTIONAL BLOCK DIAGRAM

1 2 3 4 5 6

A

LB OE A

B

I/O

9

C

I/O10I/O

D

V

SS

E

V

CC

F I/O

15

G

I/O16DNU A

H

DNU A

UB A

A

11

I/O12 DNU A

I/O13 DNU DNU I/O5V

I/O

14A14

A

8

A

0

A

3

A

5

A

A

12

A

9

1

4

6

7

15

13

10

A

CS2

2

CS1I/O

I/O2I/O

I/O4V

I/O6I/O

WE I/O

A

DNU

11

1

3

CC

SS

7

8

48-FPBGA : Top view (ball down)

Name Function Name Function

CS1,CS2 Chip select inputs Vcc Power Supply

I/O9 ~ I/O16

WE

OE
UB

LB

CS

1

CS

2

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

A

9

I/O1 ~ I/O8

Control Logic

Cont

Cont

Data

Data

Pre-charge Circuit

V

CC

V

Memory Array

Row Select

1024 x 1024

I/O Circuit

Column Select

A10A11A12A13A14A

15

SS

OE Output Enable input Vss Ground

WE Write Enable input UB Upper Byte (I/O

A0~A15 Address Inputs LB Lower Byte (I/O

I/O1~I/O16 Data Inputs/outputs DNU Do Not Use

9~16

1~8

)

)

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merging Memory & Logic Solutions Inc.merging Memory & Logic Solutions Inc.

ABSOLUTE MAXIMUM RATINGS *

Parameter Symbol Ratings Unit

EM610FV16 Series

Low Power, 64Kx16 SRAM

Voltage on Any Pin Relative to Vss VIN, V
Voltage on Vcc supply relative to Vss V
Power Dissipation P
Operating Temperature T

* Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

OUT

CC

D

A

-0.2 to Vcc+0.3(Max. 4.0V) V

-0.2 to 4.0V V

1.0 W

-40 to 85

o

C

FUNCTIONAL DESCRIPTION

CS

H X X X X X High-Z High-Z Deselected Stand by
X L X X X X High-Z High-Z Deselected Stand by
X X X X H H High-Z High-Z Deselected Stand by

L H H H L X High-Z High-Z Output Disabled Active
L H H H X L High-Z High-Z Output Disabled Active
L H L H L H Data Out High-Z Lower Byte Read Active

CS

1

2

OE WE LB UB I/O

1-8

I/O

9-16

Mode Power

L H L H H L High-Z Data Out Upper Byte Read Active
L H L H L L Data Out Data Out Word Read Active
L H X L L H Data In High-Z Lower Byte Write Active
L H X L H L High-Z Data In Upper Byte Write Active
L H X L L L Data In Data In Word Write Active

Note: X means don’t care. (Must be low or high state)

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merging Memory & Logic Solutions Inc.merging Memory & Logic Solutions Inc.

EM610FV16 Series

Low Power, 64Kx16 SRAM

RECOMMENDED DC OPERATING CONDITIONS

1)

Parameter Symbol Min Typ Max Unit

Supply voltage
Ground

Input high voltage
Input low voltage

1. TA= -40 to 85oC, otherwise specified

2. Overshoot: VCC +2.0 V in case of pulse width < 20ns

3. Undershoot: -2.0 V in case of pulse width < 20ns

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE

1)

(f =1MHz, TA=25oC)

Item Symbol Test Condition Min Max Unit

Input capacitance C
Input/Ouput capacitance C

V
V

IO

CC

SS

V

IH

V

IL

IN

2.7 3.3 3.6 V
0 0 0 V

2.2 -

3)

-0.2

VIN=0V - 8 pF

VIO=0V - 10 pF

VCC + 0.2

2)

- 0.6 V

V

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Parameter Symbol Test Conditions Min Typ Max Unit

Input leakage current I

Output leakage current

Operating power supply I

Average operating current

Output low voltage V
Output high voltage V
Standby Current (TTL) I

Standby Current (CMOS)

I

LO

CC

I

CC1

I

CC2

SB

I

SB1

V

LI

CS1=VIH or CS2=VIL or OE=V
VIO=VSS to V

IIO=0mA, CS1=VIL, CS2= WE=VIH, VIN=VIH or V

Cycle time=1µs, 100% duty, IIO=0mA,
CS1< 0.2V, LB<0.2V or/and UB<0.2V, CS2>VCC-0.2V,
VIN< 0.2V or VIN>VCC-0.2V

Cycle time = Min, I

CS1=VIL, CS2=V
VIN=VIL or V

IOL = 2.1mA

OL

I

OH

CS1=VIH, CS2=VIL, Other inputs=VIH or V
CS1> VCC-0.2V, CS2>VCC-0.2V (CS1 controlled)

or 0V< CS2<0.2V (CS2 controlled),
Other inputs = 0~V

(Typ. condition : VCC=3.3V @ 25oC)
(Max. condition : VCC=3.6V @ 85oC)

IN=VSS

= -1.0mA

OH

to V

CC

CC

IO

LB=VIL or/and UB=V

IH,

IH

CC

or WE=V

IH

=0mA, 100% duty,

-1 - 1 µA

or LB=UB=V

IL

IL

IH

-1 - 1 µA

- - 3 mA

- - 3 mA

55ns - - 26

IL ,

70ns - - 20

- - 0.4 V

2.4 - - V

IL - - 0.3 mA

LL

LF

-

0.5

1)

5 µA

mA

NOTES

1. Typical values are measured at Vcc=3.3V, TA=25

o

C and not 100% tested.

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