EMLSI EM610FV16 Service Manual

merging Memory & Logic Solutions Inc.merging Memory & Logic Solutions Inc.

Document Title

64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM

Revision History

Revision No. History Draft Date Remark

0.0 Initial Draft May 9 , 2003

0.1 2’nd Draft Add Pb-free part number February 13 , 2004

EM610FV16 Series

Low Power, 64Kx16 SRAM

Emerging Memory & Logic Solutions Inc.

IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160
Tel : [phone]~1766 Fax : [phone] / Homepage : www.emlsi.com

The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.

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EM610FV16 Series

Low Power, 64Kx16 SRAM

FEATURES

• Process Technology : 0.18µm Full CMOS

• Organization : 64K x 16 bit

• Power Supply Voltage : 2.7V ~ 3.6V

• Low Data Retention Voltage : 1.5V(Min.)

• Three state output and TTL Compatible

• Package Type : 48-FPBGA 6.0x7.0

PRODUCT FAMILY

Product
Family

EM610FV16

1. The parameter is measured with 30pF test load.

2. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested.

Operating
Temperature

Industrial (-40 ~ 85oC)

Vcc Range Speed

2.7V~3.6V

PIN DESCRIPTION

GENERAL DESCRIPTION

The EM610FV16 families are fabricated by EMLSI’s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The fami­lies also supports low data retention voltage for battery
back-up operation with low data retention current.

Power Dissipation

PKG Type

1)

55

/70ns 0.5µA

Standby
(I

, Typ.)

SB1

Operating
(I

.Max.)

CC1

2)

3 mA 48-FPBGA

FUNCTIONAL BLOCK DIAGRAM

1 2 3 4 5 6

A

LB OE A

B

I/O

9

C

I/O10I/O

D

V

SS

E

V

CC

F I/O

15

G

I/O16DNU A

H

DNU A

UB A

A

11

I/O12 DNU A

I/O13 DNU DNU I/O5V

I/O

14A14

A

8

A

0

A

3

A

5

A

A

12

A

9

1

4

6

7

15

13

10

A

CS2

2

CS1I/O

I/O2I/O

I/O4V

I/O6I/O

WE I/O

A

DNU

11

1

3

CC

SS

7

8

48-FPBGA : Top view (ball down)

Name Function Name Function

CS1,CS2 Chip select inputs Vcc Power Supply

I/O9 ~ I/O16

WE

OE
UB

LB

CS

1

CS

2

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

A

9

I/O1 ~ I/O8

Control Logic

Cont

Cont

Data

Data

Pre-charge Circuit

V

CC

V

Memory Array

Row Select

1024 x 1024

I/O Circuit

Column Select

A10A11A12A13A14A

15

SS

OE Output Enable input Vss Ground

WE Write Enable input UB Upper Byte (I/O

A0~A15 Address Inputs LB Lower Byte (I/O

I/O1~I/O16 Data Inputs/outputs DNU Do Not Use

9~16

1~8

)

)

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ABSOLUTE MAXIMUM RATINGS *

Parameter Symbol Ratings Unit

EM610FV16 Series

Low Power, 64Kx16 SRAM

Voltage on Any Pin Relative to Vss VIN, V
Voltage on Vcc supply relative to Vss V
Power Dissipation P
Operating Temperature T

* Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

OUT

CC

D

A

-0.2 to Vcc+0.3(Max. 4.0V) V

-0.2 to 4.0V V

1.0 W

-40 to 85

o

C

FUNCTIONAL DESCRIPTION

CS

H X X X X X High-Z High-Z Deselected Stand by
X L X X X X High-Z High-Z Deselected Stand by
X X X X H H High-Z High-Z Deselected Stand by

L H H H L X High-Z High-Z Output Disabled Active
L H H H X L High-Z High-Z Output Disabled Active
L H L H L H Data Out High-Z Lower Byte Read Active

CS

1

2

OE WE LB UB I/O

1-8

I/O

9-16

Mode Power

L H L H H L High-Z Data Out Upper Byte Read Active
L H L H L L Data Out Data Out Word Read Active
L H X L L H Data In High-Z Lower Byte Write Active
L H X L H L High-Z Data In Upper Byte Write Active
L H X L L L Data In Data In Word Write Active

Note: X means don’t care. (Must be low or high state)

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EM610FV16 Series

Low Power, 64Kx16 SRAM

RECOMMENDED DC OPERATING CONDITIONS

1)

Parameter Symbol Min Typ Max Unit

Supply voltage
Ground

Input high voltage
Input low voltage

1. TA= -40 to 85oC, otherwise specified

2. Overshoot: VCC +2.0 V in case of pulse width < 20ns

3. Undershoot: -2.0 V in case of pulse width < 20ns

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE

1)

(f =1MHz, TA=25oC)

Item Symbol Test Condition Min Max Unit

Input capacitance C
Input/Ouput capacitance C

V
V

IO

CC

SS

V

IH

V

IL

IN

2.7 3.3 3.6 V
0 0 0 V

2.2 -

3)

-0.2

VIN=0V - 8 pF

VIO=0V - 10 pF

VCC + 0.2

2)

- 0.6 V

V

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Parameter Symbol Test Conditions Min Typ Max Unit

Input leakage current I

Output leakage current

Operating power supply I

Average operating current

Output low voltage V
Output high voltage V
Standby Current (TTL) I

Standby Current (CMOS)

I

LO

CC

I

CC1

I

CC2

SB

I

SB1

V

LI

CS1=VIH or CS2=VIL or OE=V
VIO=VSS to V

IIO=0mA, CS1=VIL, CS2= WE=VIH, VIN=VIH or V

Cycle time=1µs, 100% duty, IIO=0mA,
CS1< 0.2V, LB<0.2V or/and UB<0.2V, CS2>VCC-0.2V,
VIN< 0.2V or VIN>VCC-0.2V

Cycle time = Min, I

CS1=VIL, CS2=V
VIN=VIL or V

IOL = 2.1mA

OL

I

OH

CS1=VIH, CS2=VIL, Other inputs=VIH or V
CS1> VCC-0.2V, CS2>VCC-0.2V (CS1 controlled)

or 0V< CS2<0.2V (CS2 controlled),
Other inputs = 0~V

(Typ. condition : VCC=3.3V @ 25oC)
(Max. condition : VCC=3.6V @ 85oC)

IN=VSS

= -1.0mA

OH

to V

CC

CC

IO

LB=VIL or/and UB=V

IH,

IH

CC

or WE=V

IH

=0mA, 100% duty,

-1 - 1 µA

or LB=UB=V

IL

IL

IH

-1 - 1 µA

- - 3 mA

- - 3 mA

55ns - - 26

IL ,

70ns - - 20

- - 0.4 V

2.4 - - V

IL - - 0.3 mA

LL

LF

-

0.5

1)

5 µA

mA

NOTES

1. Typical values are measured at Vcc=3.3V, TA=25

o

C and not 100% tested.

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AC OPERATING CONDITIONS

Test Conditions (Test Load and Test Input/Output Reference)

Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL

CL

1. Including scope and Jig capacitance

2. R1=3070Ω, R2=3150Ω

3. VTM=2.8V

READ CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)

1)

= 30pF + 1 TTL

EM610FV16 Series

Low Power, 64Kx16 SRAM

3)

V

TM

2)

R

1

CL

1)

2)

R

2

Parameter

Read cycle time t

Symbol

RC

Min Max Min Max

Unit

55 - 70 - ns

Address access time tAA - 55 - 70 ns

55ns 70ns

Chip select to output t

co1, tco2

Output enable to valid output t
UB, LB acess time t
Chip select to low-Z output t

LZ1, tLZ2

UB, LB enable to low-Z output t
Output enable to low-Z output t
Chip disable to high-Z output t

HZ1, tHZ2

UB, LB disable to high-Z output t
Output disable to high-Z output t
Output hold from address change t

WRITE CYCLE

(Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)

OE

BA

BLZ

OLZ

BHZ

OHZ

OH

- 55 - 70 ns

- 25 - 35 ns
55 70 ns

10 - 10 - ns
10 - 10 - ns

5 - 5 - ns
0 20 0 25 ns
0 20 0 25 ns
0 20 0 25 ns

10 - 10 - ns

55ns 70ns

Parameter

Write cycle time t
Chip select to end of write t
Address setup time t
Address valid to end of write t
UB, LB valid to end of write t
Write pulse width t
Write recovery time t
Write to ouput high-Z t
Data to write time overlap t
Data hold from write time t
End write to output low-Z t

Symbol

WC

CW1, tCW2

As

AW

BW

WP

WR

WHZ

DW

DH

OW

Min Max Min Max

55 - 70 - ns
45 - 60 - ns

0 - 0 - ns
45 - 60 - ns
45 - 60 - ns
40 - 50 - ns

0 - 0 - ns

0 20 0 20 ns
25 30 ns

0 - 0 - ns

5 - 5 - ns

Unit

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TIMING DIAGRAMS

EM610FV16 Series

Low Power, 64Kx16 SRAM

TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=V

t

RC

Address

t

AA

t

OH

Data Out

TIMING WAVEFORM OF READ CYCLE(2) (WE = V

Address

CS1

Previous Data Valid

)

IH

t

RC

t

AA

t

CO

, CS2=WE=V

IL

Data Valid

t

OH

IH, UB

or/and LB=VIL)

CS2

t

t

BA

HZ

UB,LB

t

t

OE

BHZ

OE

t

OLZ

Data Out

NOTES (READ CYCLE)

1. tHZ and t

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.

are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.

OHZ

High-Z

Data Valid

t

BLZ

t

LZ

t

OHZ

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TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)

t

WC

Address

EM610FV16 Series

Low Power, 64Kx16 SRAM

tCW(2)

CS1

CS2

t

AW

t

BW

UB,LB

tWP(1)

WE

tAS(3)

Data in

Data out

High-Z

Data Undefined

t

WHZ

TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)

t

DW

Data Valid

tWR(4)

t

DH

t

OW

High-Z

Address

CS1

CS2

UB,LB

WE

Data in

Data out

t

WC

tAS(3)

tCW(2)

t

AW

t

BW

tWP(1)

t

DW

Data Valid

High-Z High-Z

tWR(4)

t

DH

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TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)

t

WC

Address

EM610FV16 Series

Low Power, 64Kx16 SRAM

CS1

CS2

UB,LB

WE

Data in

Data out

NOTES (WRITE CYCLE)

tCW(2)

t

AW

t

BW

tAS(3)

tWP(1)

t

DW

Data Valid

High-Z High-Z

tWR(4)

t

DH

1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE
goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double

byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is
measured from the beginning of write to the end of write.

2. tCW is measured from the CS1 going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1
or WE going high.

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DATA RETENTION CHARACTERISTICS

EM610FV16 Series

Low Power, 64Kx16 SRAM

Parameter Symbol Test Condition Min Typ

VCC for Data Retention V

Data Retention Current

Chip Deselect to Data Retention Time t
Operation Recovery Time t

NOTES

1. See the I

2.Typical values are measured at T

measurement condition of datasheet page 4.

SB1

=25

A

DATA RETENTION WAVE FORM

t

SDR

V

cc

2.7V

I

DR

I

DR

SDR

RDR

o

C and not 100% tested.

SB1

(Chip Disabled)

VCC=1.5V, I
(Chip Disabled)

See data retention wave form

Data Retention Mode

Test Condition

1)

Test Condition

SB1

2)

Max Unit

1.5 - 3.6 V

1)

- 0.25 - µA

0 - -

ns

t

RC

t

RDR

- -

2.2V
V

DR

CS

GND

V

cc

2.7V
CS

V

DR

0.4V

GND

CS1 > Vcc-0.2V

1

Data Retention Mode

2

t

SDR

CS2 < 0.2V

t

RDR

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PACKAGE DIMENSION

48 Ball Fine Pitch BGA (0.75mm ball pitch)

EM610FV16 Series

Low Power, 64Kx16 SRAM

Unit: millimeters

#A1

Top View

B

C

C1/2

Bottom View

B
B1 0.5

6 5 4 3 2 1

A
B
C
D
E

F
G
H

B/2

A1 index Mark

0.5

C

C1

Side View

E2

0.26

E

E1

Min Typ Max
A - 0.75 ­B 5.93 6.00 6.03

B1 - 3.75 -

C 6.93 7.00 7.03

C1 - 5.25 -

D 0.30 0.35 0.40
E 1.00 1.04 1.10

E1 - 0.79 ­E2 - 0.25 -

Y - - 0.08

D

C

Detail A

A

0.25 Typ.

0.79 Typ.

NOTES.

1. Bump counts : 48(8row x 6column)

2. Bump pitch : (x,y)=(0.75x0.75) (typ.)

3. All tolerence are +/-0.050 unless
otherwise specified.

4. Typ : Typical

5. Y is coplanarity : 0.08(Max)

Y

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MEMORY FUNCTION GUIDE

EM X XX X X X XX X X - XX XX

EM610FV16 Series

Low Power, 64Kx16 SRAM

1. EMLSI Memory

2. Device Type

3. Density

4. Option

5. Technology

6. Operating Voltage

1. Memory Component

2. Device Type
6 ------------------------ Low Power SRAM
7 ------------------------ STRAM

3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
16 ----------------------- 16M
32 ----------------------- 32M
64 ----------------------- 64M

4. Option
0 ----------------------- Dual CS
1 ----------------------- Single CS

5. Technology
Blank ------------------ CMOS
F ------------------------ Full CMOS

6. Operating Voltage
Blank ------------------ 5.0V
V ------------------------- 2.7V~3.6V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V

11. Power

10. Speed

9. Packages

8. Version

7. Orgainzation

8. Version
Blank ----------------- Mother Die
A ----------------------- First revision
B ----------------------- Second revision
C ----------------------- Third revision
D ----------------------- Fourth revision

9. Package
Blank ---------------------- FPBGA
S ---------------------------- 32 sTSOP1
T ---------------------------- 32 TSOP1
U ---------------------------- 44 TSOP2
W ---------------------------- Wafer

10. Speed
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 --------------------- 100ns
12 --------------------- 120ns

11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power (Pb-free)
L ---------------------- Low Power
S ---------------------- Standard Power

7. Orginzation
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit

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