DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4R128FKE8S
Direct Rambus DRAM SO-RIMMTM Module
128M-BYTE (64M-WORD x 18-BIT)
Description
The Direct Rambus SO-RIMM module is a general-purpose high-performance memory module subsystem suitable
for use in a broad range of applications including computer memory, mobile personal computers, networking
systems, and other applications where high bandwidth and low latency are required.
MC-4R128FKE8S modules consists of four 288M Direct Rambus DRAM (Direct RDRAM) devices (
These are extremely high-speed CMOS DRAMs organized as 16M words by 18 bits. The use of Rambus Signaling
Level (RSL) technology permits 800MHz transfer rates while using conventional system and board design
technologies.
Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10 ns per 16 bytes).
The architecture of the Direct RDRAM enables the highest sustained bandwidth for multiple, simultaneous,
randomly addressed memory transactions. The separate control and data buses with independent row and column
control yield high bus efficiency. The Direct RDRAM's multi-bank architecture supports up to four simultaneous
transactions per device.
Features
PD488588).
µ
• 160 edge connector pads with 0.65mm pad spacing
• 128 MB Direct RDRAM storage
• Each RDRAM
• Gold plated contacts
• RDRAMs use Chip Scale Package (CSP)
• Serial Presence Detect support
• Operates from a 2.5 V supply
• Powerdown self refresh modes
• Separate Row and Column buses for higher efficiency
Document No. E0139N30 (Ver. 3.0)
Date Published June 2002 (K) Japan
URL: http://www.elpida.com
has 32 banks, for 128 banks total on module
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
Elpida Memory,Inc. 2001-2002
Order information
MC-4R128FKE8S
Part number Organization I/O Freq.
MHz
MC-4R128FKE8S - 845 64M x 18 800 45
RAS access time
ns
Package Mounted devices
160 edge connector pads
SO-RIMM with heat spreader
Edge connector: Gold plated
4 pieces of µPD488588FF
BGA) package
µ
FBGA (
2
Data Sheet
E0139N30 (Ver. 3.0)
Module Pad Configuration
MC-4R128FKE8S
GND
LDQA8
GND
LDQA6
GND
LDQA4
GND
LDQA2
GND
LDQA0
GND
LCTM
GND
LCTMN
GND
LROW1
GND
LCOL4
GND
LCOL2
GND
LCOL0
GND
LDQB0
GND
LDQB2
GND
LDQB4
GND
LDQB6
GND
LSCK
GND
SOUT
V
NC
GND
NC
V
CMOS
NC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
DD
A34
A35
A36
A37
A38
A39
A40
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B1
B2
B3
B4
B5
B6
B7
B8
B9
GND
LDQA7
GND
LDQA5
GND
LDQA3
GND
LDQA1
GND
LCFM
GND
LCFMN
GND
LROW2
GND
LROW0
GND
LCOL3
GND
LCOL1
GND
LDQB1
GND
LDQB3
GND
LDQB5
GND
LDQB7
GND
LDQB8
GND
LCMD
GND
SIN
V
DD
NC
GND
NC
V
CMOS
NC
Side B Side A
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
NC
REF
V
SA0
DD
V
SA1
DD
V
SWP
GND
RCMD
GND
RDQB6
GND
RDQB4
GND
RDQB2
GND
RDQB0
GND
RCOL0
GND
RCOL2
GND
RCOL4
GND
RROW1
GND
RCTMN
GND
RCTM
GND
RDQA0
GND
RDQA2
GND
RDQA4
GND
RDQA6
GND
RDQA8
GND
NC
V
REF
SCL
V
SDA
V
SV
GND
RSCK
GND
RDQB8
GND
RDQB7
GND
RDQB5
GND
RDQB3
GND
RDQB1
GND
RCOL1
GND
RCOL3
GND
RROW0
GND
RROW2
GND
RCFMN
GND
RCFM
GND
RDQA1
GND
RDQA3
GND
RDQA5
GND
RDQA7
GND
A41
A42
DD
DD
DD
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
LCFM, LCFMN,
RCFM, RCFMN : Clock from master
LCTM, LCTMN,
RCTM, RCTMN : Clock to master
LCMD, RCMD : Serial Command Pad
LROW2 - LROW0,
RROW2 - RROW0 : Row bus
LCOL4 - LCOL0,
RCOL4 - RCOL0 : Column bus
LDQA8 - LDQA0,
RDQA8 - RDQA0 : Data bus A
LDQB8 - LDQB0,
RDQB8 - RDQB0 : Data bus B
LSCK, RSCK : Clock input
SA0, SA1 : Serial Presence Detect Address
SCL, SDA : Serial Presence Detect Clock
SIN, SOUT : Serial I/O
SVDD : SPD Voltage
SWP : Serial Presence Detect Write Protect
V
: Supply voltage for serial pads
CMOS
VDD : Supply voltage
V
: Logic threshold
REF
GND : Ground reference
NC : These pads are not connected
Data Sheet
E0139N30 (Ver. 3.0)
3
MC-4R128FKE8S
Module Pad Names
Pad Signal Name Pad Signal Name Pad Signal Name Pad Signal Name
A1 GND B1 GND A41 NC B41 NC
A2 LDQA8 B2 LDQA7 A42 V
A3 GND B3 GND A43 SCL B43 SA0
A4 LDQA6 B4 LDQA5 A44 VDD B44 VDD
A5 GND B5 GND A45 SDA B45 SA1
A6 LDQA4 B6 LDQA3 A46 VDD B46 VDD
A7 GND B7 GND A47 SVDD B47 SWP
A8 LDQA2 B8 LDQA1 A48 GND B48 GND
A9 GND B9 GND A49 RSCK B49 RCMD
A10 LDQA0 B10 LCFM A50 GND B50 GND
A11 GND B11 GND A51 RDQB8 B51 RDQB6
A12 LCTM B12 LCFMN A52 GND B52 GND
A13 GND B13 GND A53 RDQB7 B53 RDQB4
A14 LCTMN B14 LROW2 A54 GND B54 GND
A15 GND B15 GND A55 RDQB5 B55 RDQB2
A16 LROW1 B16 LROW 0 A56 GND B56 GND
A17 GND B17 GND A57 RDQB3 B57 RDQB0
A18 LCOL4 B18 LCOL3 A58 GND B58 GND
A19 GND B19 GND A59 RDQB1 B59 RCOL0
A20 LCOL2 B20 LCOL1 A60 GND B60 GND
A21 GND B21 GND A61 RCOL1 B61 RCOL2
A22 LCOL0 B22 LDQB1 A62 GND B62 GND
A23 GND B23 GND A63 RCOL3 B63 RCOL4
A24 LDQB0 B24 LDQB3 A64 GND B64 GND
A25 GND B25 GND A65 RROW0 B65 RROW1
A26 LDQB2 B26 LDQB5 A66 GND B66 GND
A27 GND B27 GND A67 RROW2 B67 RCTMN
A28 LDQB4 B28 LDQB7 A68 GND B68 GND
A29 GND B29 GND A69 RCFMN B69 RCTM
A30 LDQB6 B30 LDQB8 A70 GND B70 GND
A31 GND B31 GND A71 RCFM B71 RDQA0
A32 LSCK B32 LCMD A72 GND B72 GND
A33 GND B33 GND A73 RDQA1 B73 RDQA2
A34 SOUT B34 SIN A74 GND B74 GND
A35 VDD B35 VDD A75 RDQA3 B75 RDQA4
A36 NC B36 NC A76 GND B76 GND
A37 GND B37 GND A77 RDQA5 B77 RDQA6
A38 NC B38 NC A78 GND B78 GND
A39 V
CMOS
B39 V
CMOS
A79 RDQA7 B79 RDQA8
A40 NC B40 NC A80 GND B80 GND
REF
B42 V
REF
4
Data Sheet
E0139N30 (Ver. 3.0)
MC-4R128FKE8S
Module Connector Pad Description (1/2)
Signal I/O Type Description
GND – – Ground reference for RDRAM core and interface.
LCFM I RSL Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
LCFMN I RSL Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
LCMD I V
LCOL4..LCOL0 I RSL Column bus. 5-bit bus containing control and address information for column
LCTM I RSL Clock to master. Interface clock used for transmitting RSL signals to the
LCTMN I RSL Clock to master. Interface clock used for transmitting RSL signals to the
LDQA8..LDQA0 I/O RSL Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
LDQB8..LDQB0 I/O RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
LROW2..LROW0 I RSL Row bus. 3-bit bus containing control and address information for row accesses.
LSCK I V
NC – – These pads are not connected. These 8 connector pads are reserved for future
RCFM I RSL Clock from master. Interface clock used for receiving RSL signals from the
RCFMN I RSL Clock from master. Interface clock used for receiving RSL signals from the
RCMD I V
RCOL4..RCOL0 I RSL Column bus. 5-bit bus containing control and address information for column
RCTM I RSL Clock to master. Interface clock used for transmitting RSL signals to the
RCTMN I RSL Clock to master. Interface clock used for transmitting RSL signals to the
RDQA8..RDQA0 I/O RSL Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
RDQB8..RDQB0 I/O RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
RROW2..RROW0 I RSL Row bus. 3-bit bus containing control and address information for row accesses.
Serial Command used to read from and write to the control registers. Also used
CMOS
for power management.
accesses.
Channel. Positive polarity.
Channel. Negative polarity.
and the RDRAM. LDQA8 is non-functional on modules with x16 RDRAM devices.
and the RDRAM. LDQB8 is non-functional on modules with x16 RDRAM devices.
Serial clock input. Clock source used to read from and write to the RDRAM
CMOS
control registers.
use.
Channel. Positive polarity.
Channel. Negative polarity.
Serial Command Input used to read from and write to the control registers. Also
CMOS
used for power management.
accesses.
Channel. Positive polarity.
Channel. Negative polarity.
and the RDRAM. RDQA8 is non-functional on modules with x16 RDRAM devices.
and the RDRAM. RDQB8 is non-functional on modules with x16 RDRAM devices.
Data Sheet
E0139N30 (Ver. 3.0)
5
MC-4R128FKE8S
(2/2)
Signal I/O Type Description
RSCK I V
Serial clock input. Clock source used to read from and write to the RDRAM
CMOS
control registers.
SA0 I SVDD Serial Presence Detect Address 0.
SA1 I SVDD Serial Presence Detect Address 1.
SCL I SVDD Serial Presence Detect Clock.
SDA I/O SVDD Serial Presence Detect Data (Open Collector I/O).
SIN I/O V
Serial I/O for reading from and writing to the control registers. Attaches to SIO0
CMOS
of the first RDRAM on the module.
SOUT I/O V
Serial I/O for reading from and writing to the control registers. Attaches to SIO1
CMOS
of the last RDRAM on the module.
SVDD — — SPD Voltage. Used for signals SCL, SDA, SWP, SA0, SA1 and SA2.
SWP I SVDD Serial Presence Detect Write Protect (active high). When low, the SPD can be
written as well as read.
V
— — CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT.
CMOS
VDD — — Supply voltage for the RDRAM core and interface logic.
REF
V
— — Logic threshold reference voltage for RSL signals.
6
Data Sheet
E0139N30 (Ver. 3.0)
Block Diagram
V
REF
LCMD
LSCK
SIN
LDQB 7
LDQB 8
DQB 7
DQB 8
SIO 0
SIO 1
SCK
CMD
REF
V
DQB 7
DQB 8
SIO 0
SIO 1
SCK
CMD
REF
V
LDQB 5
LDQB 6
DQB 5
DQB 6
DQB 5
DQB 6
LDQB 3
LDQB 4
DQB 3
DQB 4
DQB 3
DQB 4
LDQB 1
LDQB 2
DQB 1
DQB 2
DQB 1
DQB 2
LDQB 0
LCOL 0
COL 0
DQB 0
COL 0
DQB 0
LCOL 2
LCOL 1
COL 2
COL 1
COL 2
COL 1
LCOL 4
LCOL 3
COL 4
COL 3
COL 4
COL 3
LROW 1
LROW 0
ROW 1
ROW 0
U1
ROW 1
ROW 0
U2
LROW 2
LCTMN
CTMN
ROW 2
CTMN
ROW 2
LCFMN
LCTM
CTM
CFMN
CTM
LCFM
CFM
CFMN
CFM
LDQA 1
LDQA 0
DQA 1
DQA 0
DQA 1
DQA 0
LDQA 3
LDQA 2
DQA 3
DQA 2
DQA 3
DQA 2
MC-4R128FKE8S
LDQA 8
LDQA 7
LDQA 6
LDQA 5
LDQA 4
DQA 5
DQA 4
DQA 5
DQA 4
DQA 7
DQA 6
DQA 7
DQA 6
DQA 8
DQA 8
V
CMOS
V
DD
DQA 8
DQA 7
DQA 6
DQA 5
DQA 4
DQA 3
DQA 2
DQA 1
DQA 0
CFM
CFMN
CTM
CTMN
ROW 2
ROW 1
ROW 0
COL 4
COL 3
COL 2
COL 1
COL 0
DQB 0
DQB 1
DQB 2
DQB 3
DQB 4
DQB 5
DQB 6
DQB 7
DQB 8
SIO 0
RSCK
RCMD
SOUT
SIO 1
SCK
CMD
REF
V
DQB 7
DQB 8
SIO 0
SIO 1
SCK
CMD
REF
V
RDQB 7
RDQB 8
DQB 5
DQB 6
RDQB 5
RDQB 6
DQB 3
DQB 4
RDQB 3
RDQB 4
DQB 1
DQB 2
RDQB 1
RDQB 2
SCL
SWP
COL 0
DQB 0
RCOL 0
RDQB 0
47 kΩ
COL 1
RCOL 1
COL 3
COL 2
RCOL 3
RCOL 2
SCL
WP
SA0
U3
ROW 0
COL 4
U4
RROW 0
RCOL 4
SV
V
CC
U0
A1 A2
A0
SA1 SA2
SERIAL PD
ROW 2
ROW 1
RROW 2
RROW 1
DD
SDA
CTM
CTMN
RCTM
RCTMN
CFM
CFMN
RCFM
RCFMN
DQA 1
DQA 0
RDQA 1
RDQA 0
SDA
DQA 3
DQA 2
RDQA 3
RDQA 2
DQA 5
DQA 4
RDQA 5
RDQA 4
DQA 7
DQA 6
RDQA 7
RDQA 6
DQA 8
RDQA 8
Remarks 1. Rambus Channel signals form a loop through the SO-RIMM module, with the exception of the SIO
chain.
2. See Serial Presence Detection Specification for information on the SPD device and its contents.
Data Sheet
E0139N30 (Ver. 3.0)
7
MC-4R128FKE8S
Electrical Specification
Absolute Maximum Ratings
Symbol Parameter MIN. MAX. Unit
I,ABS
V
Voltage applied to any RSL or CMOS signal pad with respect to GND −0.3 V
DD,ABS
V
Voltage on V
STORE
T
Storage temperature −50 +100 °C
with respect to GND −0.5 V
DD
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Recommended Electrical Conditions
Symbol Parameter and conditions MIN. MAX. Unit
V
Supply voltage 2.50 − 0.13 2.50 + 0.13 V
DD
V
CMOS I/O power supply at pad 2.5V controllers VDD V
CMOS
1.8V controllers 1.8 − 0.1 1.8 + 0.2
REF
V
Reference voltage 1.4 − 0.2 1.4 + 0.2 V
SPD
V
Serial presence detector-positive power supply 2.2 3.6 V
IL
V
RSL input low voltage V
VIH RSL input high voltage V
IL,CMOS
V
CMOS input low voltage −0.3 0.5V
IH,CMOS
V
CMOS input high voltage 0.5V
OL,CMOS
V
CMOS output low voltage, I
OH,CMOS
V
CMOS output high voltage, I
REF
I
V
SCK,CMD
I
CMOS input leakage current, (0 ≤ V
SIN,SOUT
I
CMOS input leakage current, (0 ≤ V
REF
current, V
REF,MAX
OL,CMOS
= 1 mA
OH,CMOS
= −0.25 mA V
−40.0 +40.0
≤ VDD) −40.0 +40.0
CMOS
≤ VDD) −10.0 +10.0
CMOS
REF
− 0.5 V
REF
+ 0.2 V
+0.25 V
CMOS
—
− 0.3
CMOS
+ 0.3 V
DD
+ 1.0 V
DD
DD
V
REF
− 0.2 V
REF
+ 0.5 V
− 0.25 V
CMOS
+ 0.3 V
CMOS
0.3 V
—
V
A
µ
A
µ
A
µ
8
Data Sheet
E0139N30 (Ver. 3.0)
MC-4R128FKE8S
AC Electrical Specifications
Symbol Parameter and Conditions MIN. TYP. MAX. Unit
Z Module Impedance of RSL signals 25.2 28.0 30.8 Ω
Module Impedance of SCK and CMD signals 23.8 28.0 32.2
Average clock delay from finger to fi nger of all RSL clock nets 1.06 ns
PD
T
(CTM, CTMN,CFM, and CFMN)
Note1,2
PD
∆T
PD-CMOS
∆T
PD- SCK,CMD
∆T
Vα/V
VXF/V
VXB/V
IN
Propagation delay variation of RSL signals with respect to TPD
Propagation delay variation of SCK signal with respect to an average clock
Note1
delay
Propagation delay variation of CMD signal with respect to SCK signal -200 +200 ps
Attenuation Limit -845 12.0 %
Forward c rosstalk coeffici ent -845 2.0 %
IN
Backward c rosstalk coeffici ent -845 1.5 %
IN
RDC DC Resistance Limit -845 0.9 Ω
-21 +21 ps
-250 +250 ps
Notes 1.
TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM,
CTMN, CFM, and CFMN).
2. If the SO-RIMM module meets the following specification, then it is compliant to the specification.
If the SO-RIMM module does not meet these specifications, then the specification can be adjusted by the
Specification” table.
“Adjusted ∆T
PD
PD
Adjusted ∆∆∆∆T
Specification
Symbol Parameter and conditions Adjusted MIN./MAX. Absolute Unit
MIN. MAX.
PD
Propagation delay variation of RSL signals with respect to TPD
∆T
N = Number of RDRAM devices installed on the SO-RIMM module.
Note
MIN. Z0) / (MIN. Z0)
∆Z0 = delta Z0% = (MAX. Z0
−
+/− [17+(18*N*∆Z0)]
Note
-30 +30 ps
(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers
on the module.)
Data Sheet
E0139N30 (Ver. 3.0)
9
MC-4R128FKE8S
SO-RIMM Module Current Profile
IDD
DD1
I
DD2
I
DD3
I
DD4
I
DD5
I
DD6
I
One RDRAM in Read
One RDRAM in Read
One RDRAM in Read
One RDRAM in Write, balance in NAP mode
One RDRAM in Write, balance in Standby mode
One RDRAM in Write, balance in Active mode
RIMM module power conditions
Note2
, balance in NAP mode
Note2
, balance in Standby mode
Note2
, balance in Active mode
Notes 1. Actual power will depend on individual RDRAM component specifications, memory controller and usage
patterns. Power does not include Refresh Current.
2. I/O current is a function of the % of 1’s, to add I/O power for 50 % 1’s for a x16 need to add 257 mA or 290
mA for x18 ECC module for the following : V
Note1
= 2.5 V, V
DD
MAX. Unit
-845 712.6 mA
-845 970 mA
-845 1105 mA
-845 732.6 mA
-845 990 mA
-845 1125 mA
TERM
= 1.8 V, V
= 1.4 V and V
REF
DIL
= V
− 0.5 V.
REF
10
Data Sheet
E0139N30 (Ver. 3.0)
Package Drawings
160 EDGE CONNECTOR PADS RIMM (SOCKET TYPE) (1/2)
EEPROM
MC-4R128FKE8S
P
ON M
G
K
288M Direct RDRAM x 4
R
S
L
detail of A part
C1
W
Y
X
A (AREA B)
M1 (AREA B)
Q
A
M2 (AREA A)
T
FDE
B
C
A1 (AREA A)
H
I
R0.75
B1
Z
J
ITEM MILLIMETERS
A
67.60 TYP.
A1
67.60 ± 0.15
B
30.00
B1
0.75 ± 0.10
C
4.00
C1
4.00 ± 0.10
D
25.35
E
13.60
F
25.35
G
1.65
H
21.00
I
17.00
J
21.00
K
4.30
L
0.65 TYP.
M
31.25 ± 0.15
M1
8.75
M2
22.50
N
29.25
O
20.00
P
5.00 ± 0.10
Q
R1.00
R
1.00 ± 0.10
S
φ
2.00
T
1.0 ± 0.10
W
0.43 ± 0.03
X
2.55 MIN.
Y
0.25 MAX.
Z
1.50 ± 0.10
Data Sheet
E0139N30 (Ver. 3.0)
ECA-TS2-0034-02
11
160 EDGE CONNECTOR PADS RIMM (SOCKET TYPE) (2/2)
B
E
MC-4R128FKE8S
Pad A1
ITEM
A1
B
C
D
E
F
G
H
CC
D
A1
DESCRIPTION
PCB length
PCB height
Center-center pad width from pad A1 to A40,
A41 to A80, B1 to B40 or B41 to B80
Spacing from PCB left edge to connector key notch
Spacing from contact pad PCB edge
to side edge retainer notch
PCB thickness
Heat spreader thickness from PCB surface (one side) to
heat spreader top surface
RIMM thickness
MIN.
67.45
31.10
-
-
-
0.90
-
-
Pad A80
TYP.
67.60
31.25
25.35
30.00
20.00
1.00
1.35
2.35
G
H
MAX.
67.75
31.40
-
-
-
1.10
-
-
F
UNIT
mm
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12
Data Sheet
ECA-TS2-0034-02
E0139N30 (Ver. 3.0)
MC-4R128FKE8S
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to V
DD
or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
MDE0202
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
Data Sheet
E0139N30 (Ver. 3.0)
CME0107
13
MC-4R128FKE8S
Rambus, RDRAM and the Rambus logo are registered trademarks of Rambus Inc.
RIMM, SO-RIMM, RaSer and QRSL are trademarks of Rambus Inc.
µµµµ
BGA is a registered trademark of Tessera, Inc.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
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