The Direct Rambus RIMM module is a general-purpose high-performance memory module subsystem suitable for
use in a broad range of applications including computer memory, personal computers, workstations, and other
applications where high bandwidth and low latency are required.
MC-4R128FKE6D modules consists of four 288M Direct Rambus DRAM (Direct RDRAM) devices (
These are extremely high-speed CMOS DRAMs organized as 16M words by 18 bits. The use of Rambus Signaling
Level (RSL) technology permits 600MHz, 711MHz or 800MHz transfer rates while using conventional system and
board design technologies.
Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10 ns per sixteen bytes).
The architecture of the Direct RDRAM enables the highest sustained bandwidth for multiple, simultaneous,
randomly addressed memory transactions. The separate control and data buses with independent row and column
control yield over 95 % bus efficiency. The Direct RDRAM's 32 banks support up to four simultaneous transactions
per device.
Features
PD488588).
µ
• 184 edge connector pads with 1mm pad spacing
• 128 MB Direct RDRAM storage
• Each RDRAM
• Gold plated contacts
• RDRAMs use Chip Scale Package (CSP)
• Serial Presence Detect support
• Operates from a 2.5 V supply
• Powerdown self refresh modes
• Separate Row and Column buses for higher efficiency
• Over Drive Factor (ODF) support
Document No. E0093N20 (Ver. 2.0)
Date Published June 2002 (K) Japan
URL: http://www.elpida.com
has 32 banks, for 128 banks total on module
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Elpida Memory, Inc. i s a joint venture DRAM company of NEC Corporati on and Hi tachi, Ltd.
LCFM, LCFMN,
RCFM, RCFMN : Clock from master
LCTM, LCTMN,
RCTM, RCTMN : Clock to master
LCMD, RCMD : Serial Command Pad
LROW2 - LROW0,
RROW2 - RROW0 : Row bus
LCOL4 - LCOL0,
RCOL4 - RCOL0 : Column bus
LDQA8 - LDQA0,
RDQA8 - RDQA0 : Data bus A
LDQB8 - LDQB0,
RDQB8 - RDQB0 : Data bus B
LSCK, RSCK : Clock input
SA0 - SA2 : Serial Presence Detect Address
SCL, SDA : Serial Presence Detect Clock
SIN, SOUT : Serial I/O
SVDD : SPD Voltage
SWP : Serial Presence Detect Write Protect
V
: Supply voltage for serial pads
CMOS
VDD : Supply voltage
V
: Logic threshold
REF
GND : Ground reference
NC : These pads are not connected
Data Sheet
E0093N20 (Ver. 2.0)
3
MC-4R128FKE6D
Module Pad Names
Pad Signal Name Pad Signal Name Pad Signal Name Pad Signal Name
Signal I/O Type Description
GND – – Ground reference for RDRAM core and interface. 72 P CB connector pads.
LCFM I RSL Clock from master. Interface clock used for receiving RSL si gnal s from the
Channel. Positive polarit y.
LCFMN I RSL Clock from master. Interface clock used for receiving RSL si gnal s from the
Channel. Negative polarity.
LCMD I V
LCOL4..LCOL0 I RSL Column bus. 5-bit bus containing control and addres s information for column
LCTM I RSL Clock to master. Interface cl ock used for transmitti ng RS L signals to the
LCTMN I RSL Clock to master. Interface cl ock used for transmitti ng RS L signals to the
LDQA8..LDQA0 I/O RSL Data bus A. A 9-bit bus c arryi ng a byte of read or write data between the Channel
LDQB8..LDQB0 I/O RSL Data bus B. A 9-bit bus c arryi ng a byte of read or write data between the Channel
LROW2..LROW0 I RSL Row bus. 3-bit bus containing control and address inform ation for row accesses.
LSCK I V
NC – – These pads are not connected. These 24 connector pads are reserved for future
RCFM I RSL Clock from master. Interface clock used for receiving RSL signals from the
RCFMN I RSL Clock from master. Interface cloc k used for receiving RSL signals from the
RCMD I V
RCOL4..RCOL0 I RSL Column bus. 5-bit bus containing control and address inf ormation for column
RCTM I RSL Clock to m aster. Interface clock us ed for transmitting RSL signals to the
RCTMN I RSL Clock to m aster. Interface clock used for transmitting RSL si gnal s to the
RDQA8..RDQA0 I/O RSL Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
RDQB8..RDQB0 I/O RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
RROW2..RROW0 I RSL Row bus. 3-bit bus containing control and address information for row accesses.
Serial Command used t o read from and write to the control registers. Also used
CMOS
for power management.
accesses.
Channel. Positive polarit y.
Channel. Negative polarity.
and the RDRAM. LDQA8 is non-functi onal on modules with x16 RDRAM devices.
and the RDRAM. LDQB8 is non-functi onal on modules with x16 RDRAM devices.
Serial clock input. Clock source used to read from and write to the RDRAM
CMOS
control registers.
use.
Channel. Positive polarit y.
Channel. Negative polarity.
Serial Command Input used to read from and write to the control registers. Also
CMOS
used for power management.
accesses.
Channel. Positive polarit y.
Channel. Negative polarity.
and the RDRAM. RDQA8 is non-functi onal on modules with x16 RDRAM devices.
and the RDRAM. RDQB8 is non-functi onal on modules with x16 RDRAM devices.
Data Sheet
E0093N20 (Ver. 2.0)
5
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