ELPIDA HB52E328EM-A6B, HB52E328EM-B6B, HB52E329EM-A6B, HB52E329EM-B6B DATA SHEET
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DATA SHEET
256MB Unbuffered SDRAM DIMM
HB52E328EM-A6B, -B6B (32M words ×××× 64 bits, 1 bank)
HB52E329EM-A6B, -B6B (32M words ×××× 72 bits, 1 bank)
Description
The HB52E328EM and HB52E329EM belong to 8-byte
DIMM (Dual In-line Memory Module) family, and have
been developed as an optimized main memory solution
for 8-byte processor applications. They are
synchronous Dynamic RAM Module, mounted 256M
bits SDRAMs (HM5225805BTT) sealed in TSOP
package, and 1 piece of serial EEPROM (2k bits) for
Presence Detect (PD). The HB52E328EM is
organized 32M × 64 × 1 bank mounted 8 pieces of
256M bits SDRAM. The HB52E329EM is organized
32M × 72 × 1 bank mounted 9 pieces of 256M bits
SDRAM.
Therefore, they make high density mounting possible
without surface mount technology. They provide
common data inputs and outputs. Decoupling
capacitors are mounted beside each TSOP on the
module board.
Features
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
• Fully compatible with: JEDEC standard outline 8-
byte DIMM
• 168-pin socket type package (dual lead out)
Outline: 133.37mm (Length) × 34.925mm (Height)
× 4.00mm (Thickness)
Lead pitch: 1.27mm
• 3.3V power supply
• Clock frequency: 100MHz (max.)
• LVTTL interface
• Data bus width : × 64 Non parity (HB52E328EM)
: × 72 ECC (HB52E329EM)
• Single pulsed /RAS
• 4 Banks can operates simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8
• 2 variations of burst sequence
Sequential
Interleave
• Programmable /CE latency (CL)
: 2, 3 (HB52E328EM/329EM-A6B)
: 3 (HB52E328EM/329EM-B6B)
Document No. E0185H10 (Ver. 1.0)
Date Published July 2001
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
C
Elpida Memory, Inc. 2001
HB52E328EM-A6B, -B6B, HB52E329EM-A6B, -B6B
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Ordering Information
Part number
HB52E328EM-A6B
HB52E328EM-B6B
HB52E329EM-A6B
HB52E329EM-B6B
Pin Configurations
[HB52E328EM]
Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
1 VSS 43 VSS 85 VSS 127 VSS
2 DQ0 44 NC 86 DQ32 128 CKE0
3 DQ1 45 /S2 87 DQ33 129 NC
4 DQ2 46 DQMB2 88 DQ34 130 DQMB6
5 DQ3 47 DQMB3 89 DQ35 131 DQMB7
6 VCC 48 NC 90 VCC 132 NC
7 DQ4 49 VCC 91 DQ36 133 VCC
8 DQ5 50 NC 92 DQ37 134 NC
9 DQ6 51 NC 93 DQ38 135 NC
10 DQ7 52 NC 94 DQ39 136 NC
11 DQ8 53 NC 95 DQ40 137 NC
12 VSS 54 VSS 96 VSS 138 VSS
13 DQ9 55 DQ16 97 DQ41 139 DQ48
14 DQ10 56 DQ17 98 DQ42 140 DQ49
15 DQ11 57 DQ18 99 DQ43 141 DQ50
16 DQ12 58 DQ19 100 DQ44 142 DQ51
17 DQ13 59 VCC 101 DQ45 143 VCC
18 VCC 60 DQ20 102 VCC 144 DQ52
19 DQ14 61 NC 103 DQ46 145 NC
20 DQ15 62 NC 104 DQ47 146 NC
21 NC 63 NC 105 NC 147 NC
22 NC 64 VSS 106 NC 148 VSS
23 VSS 65 DQ21 107 VSS 149 DQ53
24 NC 66 DQ22 108 NC 150 DQ54
25 NC 67 DQ23 109 NC 151 DQ55
26 VCC 68 VSS 110 VCC 152 VSS
27 /W 69 DQ24 111 /CE 153 DQ56
28 DQMB0 70 DQ25 112 DQMB4 154 DQ57
Clock frequency
MHz (max.)
100
100
/CE latency
2, 3
3
2, 3
3
1 pin 10 pin11 pin 40 pin 41 pin 84 pin
85 pin 94 pin 95 pin 124 pin 125 pin 168 pin
Package
168-pin dual lead out
socket type
Contact pad
Gold
Data Sheet E0185H10 (Ver. 1.0)
2
HB52E328EM-A6B, -B6B, HB52E329EM-A6B, -B6B
Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
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29 DQMB1 71 DQ26 113 DQMB5 155 DQ58
30 /S0 72 DQ27 114 NC 156 DQ59
31 NC 73 VCC 115 /RE 157 VCC
32 VSS 74 DQ28 116 VSS 158 DQ60
33 A0 75 DQ29 117 A1 159 DQ61
34 A2 76 DQ30 118 A3 160 DQ62
35 A4 77 DQ31 119 A5 161 DQ63
36 A6 78 VSS 120 A7 162 VSS
37 A8 79 CK2 121 A9 163 CK3
38 A10 (AP) 80 NC 122 BA0 164 NC
39 BA1 81 WP 123 A11 165 SA0
40 VCC 82 SDA 124 VCC 166 SA1
41 VCC 83 SCL 125 CK1 167 SA2
42 CK0 84 VCC 126 A12 168 VCC
[HB52E329EM]
Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
1 VSS 43 VSS 85 VSS 127 VSS
2 DQ0 44 NC 86 DQ32 128 CKE0
3 DQ1 45 /S2 87 DQ33 129 NC
4 DQ2 46 DQMB2 88 DQ34 130 DQMB6
5 DQ3 47 DQMB3 89 DQ35 131 DQMB7
6 VCC 48 NC 90 VCC 132 NC
7 DQ4 49 VCC 91 DQ36 133 VCC
8 DQ5 50 NC 92 DQ37 134 NC
9 DQ6 51 NC 93 DQ38 135 NC
10 DQ7 52 CB2 94 DQ39 136 CB6
11 DQ8 53 CB3 95 DQ40 137 CB7
12 VSS 54 VSS 96 VSS 138 VSS
13 DQ9 55 DQ16 97 DQ41 139 DQ48
14 DQ10 56 DQ17 98 DQ42 140 DQ49
15 DQ11 57 DQ18 99 DQ43 141 DQ50
16 DQ12 58 DQ19 100 DQ44 142 DQ51
17 DQ13 59 VCC 101 DQ45 143 VCC
18 VCC 60 DQ20 102 VCC 144 DQ52
19 DQ14 61 NC 103 DQ46 145 NC
20 DQ15 62 NC 104 DQ47 146 NC
21 CB0 63 NC 105 CB4 147 NC
22 CB1 64 VSS 106 CB5 148 VSS
23 VSS 65 DQ21 107 VSS 149 DQ53
24 NC 66 DQ22 108 NC 150 DQ54
25 NC 67 DQ23 109 NC 151 DQ55
26 VCC 68 VSS 110 VCC 152 VSS
Data Sheet E0185H10 (Ver. 1.0)
3
HB52E328EM-A6B, -B6B, HB52E329EM-A6B, -B6B
Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
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27 /W 69 DQ24 111 /CE 153 DQ56
28 DQMB0 70 DQ25 112 DQMB4 154 DQ57
29 DQMB1 71 DQ26 113 DQMB5 155 DQ58
30 /S0 72 DQ27 114 NC 156 DQ59
31 NC 73 VCC 115 /RE 157 VCC
32 VSS 74 DQ28 116 VSS 158 DQ60
33 A0 75 DQ29 117 A1 159 DQ61
34 A2 76 DQ30 118 A3 160 DQ62
35 A4 77 DQ31 119 A5 161 DQ63
36 A6 78 VSS 120 A7 162 VSS
37 A8 79 CK2 121 A9 163 CK3
38 A10 (AP) 80 NC 122 BA0 164 NC
39 BA1 81 WP 123 A11 165 SA0
40 VCC 82 SDA 124 VCC 166 SA1
41 VCC 83 SCL 125 CK1 167 SA2
42 CK0 84 VCC 126 A12 168 VCC
Pin Description
[HB52E328EM]
Pin name Function
A0 to A12 Address input
Row address A0 to A12
Column address A0 to A9
BA0, BA1 Bank select address
DQ0 to DQ63 Data input/output
/S0, /S2 Chip select input
/RE Row enable (/RAS) input
/CE Column enable (/CAS) input
/W Write enable input
DQMB0 to DQMB7 Byte data mask
CK0, CK2 Clock input
CKE0 Clock enable input
WP Write protect for serial PD
SDA Data input/output for serial PD
SCL Clock input for serial PD
SA0 to SA2 Serial address input
VCC Primary positive power supply
VSS Ground
NC No connection
Data Sheet E0185H10 (Ver. 1.0)
4
HB52E328EM-A6B, -B6B, HB52E329EM-A6B, -B6B
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[HB52E329EM]
Pin name Function
A0 to A12 Address input
Row address A0 to A12
Column address A0 to A9
BA0, BA1 Bank select address
DQ0 to DQ63 Data input/output
CB0 to CB7 Check bit (Data input/output)
/S0, /S2 Chip select input
/RE Row enable (/RAS) input
/CE Column enable (/CAS) input
/W Write enable input
DQMB0 to DQMB7 Byte data mask
CK0, CK2 Clock input
CKE0 Clock enable input
WP Write protect for serial PD
SDA Data input/output for serial PD
SCL Clock input for serial PD
SA0 to SA2 Serial address input
VCC Primary positive power supply
VSS Ground
NC No connection
Data Sheet E0185H10 (Ver. 1.0)
5
HB52E328EM-A6B, -B6B, HB52E329EM-A6B, -B6B
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Serial PD Matrix*1
Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
1 Total SPD memory size 0 0 0 0 1 0 0 0 08 256 byte
2 Memory type 0 0 0 0 0 1 0 0 04 SDRAM
3 Number of row addresses bits 0 0 0 0 1 1 0 1 0D 13
4 Number of column addresses bits 0 0 0 0 1 0 1 0 0A 10
5 Number of banks 0 0 0 0 0 0 0 1 01 1
6
(HB52E329EM) 0 1 0 0 1 0 0 0 48 72 bit
7 Module data width (continued) 0 0 0 0 0 0 0 0 00 0 (+)
8 Module interface signal levels 0 0 0 0 0 0 0 1 01 LVTTL
9
10
11
(HB52E329EM) 0 0 0 0 0 0 1 0 02 ECC
12 Refresh rate/type 1 0 0 0 0 0 1 0 82
13 SDRAM width 0 0 0 0 1 0 0 0 08 32M × 8
14
(HB52E329EM) 0 0 0 0 1 0 0 0 08 × 8
15
16
17
18
19
20
21 SDRAM device attributes 0 0 0 0 0 0 0 0 00 Non buffer
22 SDRAM device attributes: General 0 0 0 0 1 1 1 0 0E VCC ± 10%
23
(-B6B) 15ns 1 1 1 1 0 0 0 0 F0
24
(-B6B) 9ns 1 0 0 1 0 0 0 0 90
Number of bytes used by module
manufacturer
Module data width
(HB52E328EM)
SDRAM cycle time
(highest /CE latency)
10ns
SDRAM access from Clock
(highest /CE latency)
6ns
Module configuration type
(HB52E328EM)
Error checking SDRAM width
(HB52E328EM)
SDRAM device attributes:
minimum clock delay for back-toback random column addresses
SDRAM device attributes:
Burst lengths supported
SDRAM device attributes: number of
banks on SDRAM device
SDRAM device attributes:
/CE latency
SDRAM device attributes:
/S latency
SDRAM device attributes:
/W latency
SDRAM cycle time
(2nd highest /CE latency)
(-A6B) 10ns
SDRAM access from Clock
(2nd highest /CE latency)
(-A6B) 6ns
1 0 0 0 0 0 0 0 80 128
0 1 0 0 0 0 0 0 40 64 bit
1 0 1 0 0 0 0 0 A0 CL = 3
0 1 1 0 0 0 0 0 60
0 0 0 0 0 0 0 0 00 Non parity
Normal
(7.8125 µs)
Self refresh
0 0 0 0 0 0 0 0 00 —
0 0 0 0 0 0 0 1 01 1 CLK
0 0 0 0 1 1 1 1 0F 1, 2, 4, 8
0 0 0 0 0 1 0 0 04 4
0 0 0 0 0 1 1 0 06 2, 3
0 0 0 0 0 0 0 1 01 0
0 0 0 0 0 0 0 1 01 0
1 0 1 0 0 0 0 0 A0 CL = 2
0 1 1 0 0 0 0 0 60 CL = 2
Data Sheet E0185H10 (Ver. 1.0)
6
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