ELPIDA HB52D88GB-F DATA SHEET
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB52D88GB-F
64 MB Unbuffered SDRAM Micro DIMM
8-Mword × 64-bit, 100 MHz Memory Bus, 1-Bank Module
(4 pcs of 8 M × 16 components)
PC100 SDRAM
E0010H10 (1st edition)
(Previous ADE-203-1148A (Z))
Jan. 19, 2001
Description
The HB52D88GB is a 8M × 64 × 1 banks Synchronous Dynamic RAM Micro Dual In-line Memory Module
(Micro DIMM), mounted 4 pieces of 128-Mbit SDRAM (HM5212165FTD) sealed in TSOP package and 1
piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of the product is 144-pin
Zig Zag Dual tabs socket type compact and thin package. Therefore, it makes high density mounting possible
without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are
mounted beside TSOP on the module board.
Features
• 144-pin Zig Zag Dual tabs socket type
Outline: 38.00 mm (Length) × 30.00 mm (Height) × 3.80 mm (Thickness)
Lead pitch: 0.50 mm
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Data bus width: × 64 Non parity
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length : 1/2/4/8/full page
• 2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
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HB52D88GB-F
Data Sheet E0010H10
2
• Programmable CE latency : 2/3 (HB52D88GB-A6F/A6FL)
: 3 (HB52D88GB-B6F/B6FL)
• Byte control by DQMB
• Refresh cycles: 4096 refresh cycles/64 ms
• 2 variations of refresh
Auto refresh
Self refresh
• Low self refresh current: HB52D88GB-A6FL/B6FL (L-version)
• Full page burst length capability
Sequential burst
Burst stop capability
Ordering Information
Type No. Frequency CE latency Package Contact pad
HB52D88GB-A6F
HB52D88GB-B6F
HB52D88GB-A6FL
HB52D88GB-B6FL
100 MHz
100 MHz
100 MHz
100 MHz
2/3
3
2/3
3
Micro DIMM (144-pin) Gold
Pin Arrangement
Front Side
Back Side
2pin 144pin
1pin 143pin
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HB52D88GB-F
Data Sheet E0010H10
3
Pin Arrangement (cont.)
Front side Back side
Pin No. Signal name Pin No. Signal name Pin No. Signal name Pin No. Signal name
1VSS73 NC 2 V
SS
74 CK1
3 DQ0 75 V
SS
4 DQ32 76 V
SS
5 DQ1 77 NC 6 DQ33 78 NC
7 DQ2 79 NC 8 DQ34 80 NC
9 DQ3 81 V
CC
10 DQ35 82 V
CC
11 V
CC
83 DQ16 12 V
CC
84 DQ48
13 DQ4 85 DQ17 14 DQ36 86 DQ49
15 DQ5 87 DQ18 16 DQ37 88 DQ50
17 DQ6 89 DQ19 18 DQ38 90 DQ51
19 DQ7 91 V
SS
20 DQ39 92 V
SS
21 V
SS
93 DQ20 22 V
SS
94 DQ52
23 DQMB0 95 DQ21 24 DQMB4 96 DQ53
25 DQMB1 97 DQ22 26 DQMB5 98 DQ54
27 V
CC
99 DQ23 28 V
CC
100 DQ55
29 A0 101 V
CC
30 A3 102 V
CC
31 A1 103 A6 32 A4 104 A7
33 A2 105 A8 34 A5 106 A13 (BA0)
35 V
SS
107 V
SS
36 V
SS
108 V
SS
37 DQ8 109 A9 38 DQ40 110 A12 (BA1)
39 DQ9 111 A10 (AP) 40 DQ41 112 A11
41 DQ10 113 V
CC
42 DQ42 114 V
CC
43 DQ11 115 DQMB2 44 DQ43 116 DQMB6
45 V
CC
117 DQMB3 46 V
CC
118 DQMB7
47 DQ12 119 V
SS
48 DQ44 120 V
SS
49 DQ13 121 DQ24 50 DQ45 122 DQ56
51 DQ14 123 DQ25 52 DQ46 124 DQ57
53 DQ15 125 DQ26 54 DQ47 126 DQ58
55 V
SS
127 DQ27 56 V
SS
128 DQ59
57 NC 129 V
CC
58 NC 130 V
CC
59 NC 131 DQ28 60 NC 132 DQ60
61 CK0 133 DQ29 62 CKE0 134 DQ61
63 V
CC
135 DQ30 64 V
CC
136 DQ62
65 RE 137 DQ31 66 CE 138 DQ63
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HB52D88GB-F
Data Sheet E0010H10
4
Front side Back side
Pin No. Signal name Pin No. Signal name Pin No. Signal name Pin No. Signal name
67 W 139 V
SS
68 NC 140 V
SS
69 S0 141 SDA 70 NC 142 SCL
71 NC 143 V
CC
72 NC 144 V
CC
Pin Description
Pin name Function
A0 to A11 Address input
Row addressA0 to A11
Column address A0 to A8
A12/A13 Bank select address BA1, BA0
DQ0 to DQ63 Data-input/output
S0 Chip select
RE Row address asserted bank enable
CE Column address asserted
W Write enable
DQMB0 to DQMB7 Byte input/output mask
CK0/CK1 Clock input
CKE0 Clock enable
SDA Data-input/output for serial PD
SCL Clock input for serial PD
V
CC
Power supply
V
SS
Ground
NC No connection
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HB52D88GB-F
Data Sheet E0010H10
5
Serial PD Matrix*
1
Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0 Number of bytes used by
module manufacturer
1000000080 128
1 Total SPD memory size 0000100008 256 byte
2 Memory type 0000010004 SDRAM
3 Number of row addresses bits 000011000C 12
4 Numbe r of c ol umn addr es ses bi ts 0000100109 9
5 Number of banks 0000000101 1
6 Module data width 0100000040 64
7 Module data width (continued) 0000000000 0 (+)
8 Module interface signal levels 0000000101 LVTTL
9 SDRAM cycle time
(highest CE latency)
10 ns
10100000A0 CL = 3
10 SDRAM access from Clock
(highest CE latency)
6 ns
0110000060 CL = 3
11 Module configuration type 0000000000 Non parity
12 Refresh rate/type 1000000080 Normal
(15.625 µs)
Self refresh
13 SDRAM width 0001000010 8M × 16
14 Error checking SDRAM width 0000000000 —
15 SDRAM device attributes:
minimum clock delay for backto-back random column
addresses
0000000101 1 CLK
16 SDRAM device attributes:
Burst lengths supported
100011118F 1, 2, 4, 8, full
page
17 SDRAM device attributes:
number of banks on SDRAM
device
0000010004 4
18 SDRAM device attributes:
CE latency
0000011006 2, 3
19 SDRAM device attributes:
S latency
0000000101 0
20 SDRAM device attributes:
W latency
0000000101 0
21 SDRAM module attributes 0000000000 Unbuffer
22 SDRAM device attributes:
General
000011100E VCC ± 10%
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HB52D88GB-F
Data Sheet E0010H10
6
Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
23 SDRAM cycle time
(2nd highest CE latency)
(-A6F/A6FL) 10 ns
10100000A0 CL=2
(-B6F/B6FL) 15 ns 11110000F0
24 SDRAM access from Clock
(2nd highest CE latency)
(-A6F/A6FL) 6 ns
0110000060 CL=2
(-B6F/B6FL) 8 ns 1000000080
25 SDRAM cycle time
(3rd highest CE latency)
Undefined
0000000000
26 SDRAM access from Clock
(3rd highest CE latency)
Undefined
0000000000
27 Minimum row precharge time 0001010014 20 ns
28 Row active to row active min 0001010014 20 ns
29 RE to CE delay min 0001010014 20 ns
30 Minimum RE pulse width 0011001032 50 ns
31 Density of each bank on
module
0001000010 64M byte
32 Address and command signal
input setup time
0010000020 2 ns
33 Address and command signal
input hold time
0001000010 1 ns
34 Data signal input setup time 0010000020 2 ns
35 Data signal input hold time 0001000010 1 ns
36 to 61 Superset information 0000000000 Future use
62 SPD data revision code 0001001012 Rev. 1.2A
63 Checksum for bytes 0 to 62
(-A6F/A6FL)
000011010D 13
(-B6F/B6FL) 011111017D 125
64 Manuf ac turer’ s JE DE C ID c ode0000011107 HITACHI
65 to 71 Manuf ac turer’ s JE DE C ID c ode0000000000
72 Manufacturing location ЧЧЧЧЧЧЧЧЧ× *3 (ASCII-
8bit code)
73 Manufacturer’s part number 0100100048 H
74 Manufacturer’s part number 0100001042 B
75 Manufacturer’s part number 0011010135 5
76 Manufacturer’s part number 0011001032 2
77 Manufacturer’s part number 0100010044 D
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HB52D88GB-F
Data Sheet E0010H10
7
Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
78 Manufacturer’s part number 0011100038 8
79 Manufacturer’s part number 0011100038 8
80 Manufacturer’s part number 0100011147 G
81 Manufacturer’s part number 0100001042 B
82 Manufacturer’s part number 001011012D —
83 Manufacturer’s part number
(-A6F/A6FL)
0100000141 A
(-B6F/B6FL) 0100001042 B
84 Manufacturer’s part number 0011011036 6
85 Manufacturer’s part number 0100011046 F
86 Manufacturer’s part number
(L-version)
010011004C L
Manufacturer’s part number 0010000020 (Space)
87 Manufacturer’s part number 0010000020 (Space)
88 Manufacturer’s part number 0010000020 (Space)
89 Manufacturer’s part number 0010000020 (Space)
90 Manufacturer’s part number 0010000020 (Space)
91 Revision code 0011000030 Initial
92 Revision code 0010000020 (Space)
93 Manufacturing date ЧЧЧЧЧЧЧЧЧ× Year code
(BCD)*
4
94 Manufacturing date ЧЧЧЧЧЧЧЧЧ× Week code
(BCD)*
4
95 to 98 Assembly serial number *
6
99 to 125 Manufacturer specific data ————————— *
5
126 Intel specification frequency 0110010064 100 MHz
127 Intel specification CE# latency
support
(-A6F/A6FL)
11000111C7 CL = 2, 3
(-B6F/B6FL) 11000101C5 CL = 3
Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High”
These SPD are based on Intel specification (Rev.1.2A).
2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119.
3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on
ASCII code.)
4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is “Binary
Coded Decimal”.
5. All bits of 99 through 125 are not defined (“1” or “0”).
6. Bytes 95 through 98 are assembly serial number.
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